Part B Presentation Winter 2011 ASIC Tester Performed by : AboRaya Dia Damouny Samer

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Part B Presentation Winter 2011

ASIC Tester

Performed by : AboRaya Dia Damouny Samer

1Supervised by: Ina Rivkin High Speed Digital Systems Lab in collaboration with VLSI LabElectrical Engineering Department, Technion1April 102Overview :Objective: testing the ASICs functional correctness

Comparing the providers input with the expected outputs

Providing options for viewing and analyzing the results3Technical specifications :

The tester supports up to 96 inputs/outputs and up to 48 bi-directional pins. Samples I/O signals up to 50 MHz rate. 1G memory for inputs. 1G memory for outputs.

4Project goals :0. Designing a basic design for sending/receiving data to/from the DUT .

1. Adding the loop mode to the basic design.

2. Adding Embedded Logic Analyzer .

3 . Defining a new GUI .

4. Writing the new GUI .

5Host applicationPCI BUSPSDBDUTBlock Diagram :FPGAPCI BUS77DDR ADDR BFPGAPSDBInternal RAM (cache) FIFODUTRead from RAMControllerFPGA Block Diagram Including Loop Command Register File Write to FIFO outControllerRead from DDRController50 MHz96 bit96 bit96 bit97 bit88DDR ADDR BFPGAPSDBInternal RAM (cache) FIFODUTRead from RAMControllerFPGA Block Diagram Including Loop Command Register File Write to FIFO outControllerRead from DDRController50 MHz96 bit96 bit96 bit97 bit99FPGA Block Diagram Including SignalTap And Configuration unit DDR ADDR BFPGAInternal RAM (cache) FIFOConfig unit Read from RAMControllerRegister File Write to FIFO outControllerRead from DDRController50 MHz96 bitCounter SignalTap Clk0=200MHzClk2=50MHzDUTConfig registers 10Configuration unit-in/out Config unit Data to pin out 96 bitData_in(i)Data_out(i)ConfigurationWhen configuration = 1 then Data_to_pin_out = data_outWhen configuration = 0 thenData_in = data_to_out_pin11Configuration unit-InOut Config unit Data to pin out 96 bitData_in(i)Data_out(i)In 1In 0Config(2 bit)Config[1]Config[0]The same as before, but now with mux that will choose the in/out or real-time configuration.The real-time configuration will be given in the data vector.12Config unit Configuration unit-the whole Unit Tester moudle Config_reg_enConfig unit Config unit Config unit The Config unit is duplicated 96 times.

13Configuration unit-internal connectivity Tester moudle Config_reg_enConfig unit Data_out 96 bitData_in 96 bitConfig 96*2 bitData to pin out 96 bitData_in(i)Data_out(i)In 1In 0Config(i) (2 bit)Data_out(i+48)Config(i) (LSB bit)Config(i) (MSB bit)14Short-circuit on PSDB Short circuit connects 24 pins with each others (12 pins to 12 pins).

This is the basic test of the Tester. PSDBConnectors Short circuit15Connecting DUT to 96 pinsConnecting the DUT should be according to the table.

For example: pin a of the DUT connected to pin number 1 in the data_out vector recalls that the PSDB pin is l1(46) and the pin number on the connector is 81 Should look at the table in the final report to see this mapping and Proce data book page 27

16Connecting the DUT to the clock

Clk2 which is the design clock is connected to the psdb via 2 pins.

Pin number 2 and 120 in j5/j6 connectors .

User can connect DUT clock to these pins and this DUT will be derived by the same clock as the design.

1711Dont care Dont care Every vector is 96 bit. Data out vector is the data that will be injected to the DUT.Data in vector is the DUT output.When pin with index i is an output then Data_out[i] = value and Data_in[i] should be ignored. When pin with index i is an input then Data_out[i] should be ignored and Data_in[i]=result. When pin with index i is inout then Data_out[i+48] must contain the polarity of this pin in every cycle. Data creatingData inData outConfiguration 0100 -> out 01 -> in10 -> inout11 -> not in use When port i is out, the register i should contain the value 00.

When port i is in, the register i should contain the value 01.

When port i is inout, the register i should contain the value 10 .Configuration registers

When ready to acquire is shown , the signal tap is ready to use, to be ready, user should load the design into the PROCe FPGA.Starting: Signal tap To start using signal tap, user should choose this instance (left click) . Setup tabPhysical pins and trigger counter

In this tab, user can see the signals that will be sampled, and choose the trigger condition.96 pins which are connected to the DUT and trigger counter can be used to enable trigger sampling. 2 options :

counter: assign value(n) to the output count, when the nth output is being injected, the trigger will be enabled. pin value/transition : choose a value/transition of one or more pin. Transition means signal changed from 1 to 0 or from 0 to 1 21Signal configuration

User should choose hardware for the trigger: Always choose USB-Blaster.Sampling clock : dont change it. Sampling depth .Storage qualifier .(changing sampling clock or sampling depth requires design compelation )Trigger position : Define percentage of the data storage before And after the trigger, 3 options: Pre : 20% of the data is before the trigger post : 80% of the data is before the trigger center : 50% of the data is before the trigger

ExampleGo to the data tab to see signals values when trigger happen 23The Tester applicationAllow the user to:Determine the test vectorsConfigure the application for the DUT and save the configuration for reuseView results and compare with wanted outputs(list of all the features can be found in the report)Application User Interface:Our application will have two main screens:ConfigurationDebugOur application will interact with the user through these screens

24Main Screen

25Configuration mode screen

26Configuration mode screenThe main part of the application.Allows the user to configure the system parameters to the PSDB and DUT, and to save them in a configuration file (for further use)For each DUT that has a saved configuration file , the user will not need to reconfigure it, only to load the file.Creates the Database for results analysis.The application fills the relevant registers with the configuration information for the HW (according to protocol).

27Configuration mode Loading configuration file

28Configuration mode Pins tableThe user will add inputs and outputs to the pins tableThe pins (or buses) will be added with a name (decided by the user)The user will fill the test values (in the .csv file) according to the names given in this pins table29

Configuration mode Pins table

Header Vector NameType of Vector IN/OUT/INOUTLength of VectorPSDB MappingDUT Mapping30Debug mode ScreenThe I/O part of our application.This mode allows the user to:Load inputs fileLoad Loop command .Generate Wave (Generate new input file based on wave ).Run the tester and save the outputsGenerate expected outputs based on loop . Load wanted outputs (golden model)Load logic analyzer . Compare outputs (in cycles)Single Step ModeAll files created are of .csv (comma-separated values) type.

31Debug mode

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Debug Mode Load inputs file33Debug Mode Load inputs fileThe user will load the inputs (test vectors) through a .csv file.csv is can be created through Microsoft Office Excel (instead of .xslx file)Example:A is an 4 bit input busB is a one bit input pin C is a 3 bit input busEach line represents aninput cycle and producesan output value

34Debug Mode Load Loop commands

35Debug Mode Load Loop commandsThe user will load the loop commands through a .csv file

Start lineEnd linerepeat36Debug Mode Generate Waves

37Debug Mode Generate WavesGenerate new inputs file based on the selected wave and values .Example :

constrandomclkcounter38Data TableAll the input and output data are saved inside a data structure called Data Table:Two types InTable and OutTablecontains vectors of headersCreated while verifying that it is consistent with pins configuration (in Data Conf Data structure)

39Debug mode Run and Save Outputs

40Debug mode Run and Save OutputsThe application will activate the HW, read the outputs from Bank B and create a .csv file with the outputs.

Pin 46 in PSDBPin 95 in PSDB41Debug Mode Functionality test

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242Debug Mode Functionality testLoad Wanted Outputs & Compare :After running the tester and saving the outputs to .csv file , the user can load wanted outputs file ( Golden reference) in order to compare between the two files and produce a comparison report .

43Debug Mode Functionality testLoad Logic Analyzer :The signalTap LA will be loaded :

44Debug Mode Functionality testLoad Logic Analyzer : When running the tester , the user will be asked to click on the Run Analysis button :

45Debug Mode - Single Step mode

Cycles counterNumber of Cycles to runMax Cycles to run Inputs according to input file