DAC50, Designer Track, 156-VB543. Parallel Design Methodology for Video Codec LSI with High-level Synthesis and FPGA-based Platform. Kazuya YOKOHARI, Koyo NITTA, Mitsuo IKEDA, and Atsushi SHIMIZU NTT Media Intelligence Laboratories. Outline. Introduction Proposed Design Methodology - PowerPoint PPT Presentation
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Copyright(c) 2013 Nippon Telegraph and Telephone Corporation
Parallel Design Methodology for Video Codec LSI with High-level Synthesis and FPGA-based
Platform
Kazuya YOKOHARI, Koyo NITTA,Mitsuo IKEDA, and Atsushi SHIMIZUNTT Media Intelligence Laboratories
6/5/2013 1
DAC50, Designer Track, 156-VB543
Copyright(c) 2013 Nippon Telegraph and Telephone Corporation
Outline
• Introduction• Proposed Design Methodology• Case Study: 4K HEVC Intra Codec• Evaluation• Conclusion
6/5/2013 2
Copyright(c) 2013 Nippon Telegraph and Telephone Corporation
Video Codec LSI
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• MPEG-2 and H.264/AVC are major standards of video coding.
• We have developed MPEG-2 video codec LSI (VASA) and H.264/AVC codec LSI (SARA).
• The development of video codec LSI needs many simulations.
Test data
VASA (MPEG-2)
SARA (H.264/AVC)
Bit Stream(Coded Image)
Codec LSI
• Coded image should be evaluated by subjective and objective evaluation.
• Degradations of some coded images are not detected by objective evaluation.
• Subjective evaluation in real-time is important to find these degradations.
The main changed points of each block.• LOOP#1: Version up base algorithm of
each block• LOOP#2: Functional expansion of IPD• LOOP#3: Functional expansion of each
block
• The circuit performances of each expanded function are evaluated at STEP2.
• The feedback data is available from other design loops at STEP2.
Subjective Evaluation Period
Feedback data is available
Subjective Evaluation Period
Copyright(c) 2013 Nippon Telegraph and Telephone Corporation
Evaluation (2/2)
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• Using the proposed parallel design methodology, three design loops were able to be tried in only seven months.
• Using the proposed parallel design methodology, the number of cycle*area was reduced to 1/5 in four months after preliminary design of the LOOP#1 and 1/4 in three months after preliminary design of the LOOP#2.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 160
0.2
0.4
0.6
0.8
1
1.2
STEP1, STEP2(LOOP#1)
STEP2(LOOP#2)
STEP2(LOOP#3)
Design Period (Month)
Cycle*Area
90% down
STEP1
STEP2
LOOP#180% down(four months)
LOOP#275% down(three months)
Copyright(c) 2013 Nippon Telegraph and Telephone Corporation
Conclusion• We proposed that the new design methodology for
video codec LSI. Using the proposed design methodology, we are able to reduce feedback time and run simulation and evaluate coded image in real-time.
• Using the proposed design methodology, three design loops were able to be tried in only seven months.
• Using the proposed design methodology, the number of cycle * area was reduced to 1/5 in four months after preliminary design of the LOOP#1 and 1/4 in three months after preliminary design of the LOOP#2.
• In order to realize a HEVC codec, we need to add or expand some functional tools, checking subjective evaluation of these tools.