PAPER Special Issue on Integrated Electronics and New System … · 2015-07-28 · 1662 IEICETRANS.ELECTRON.,VOL.E82–C,NO.9SEPTEMBER1999 PAPER Special Issue on Integrated Electronics

1662IEICE TRANS. ELECTRON., VOL.E82–C, NO.9 SEPTEMBER 1999

PAPER Special Issue on Integrated Electronics and New System Paradigms

Multiple-Valued Logic-in-Memory VLSI Architecture

Based on Floating-Gate-MOS Pass-Transistor Logic

Takahiro HANYU†a) and Michitaka KAMEYAMA†, Members

SUMMARY A new logic-in-memory VLSI architecturebased on multiple-valued floating-gate-MOS pass-transistor logicis proposed to solve the communication bottleneck between mem-ory and logic modules. Multiple-valued stored data are repre-sented by the threshold voltage of a floating-gate MOS tran-sistor, so that a single floating-gate MOS transistor is effec-tively employed to merge multiple-valued threshold-literal andpass-switch functions. As an application, a four-valued logic-in-memory VLSI for high-speed pattern recognition is also pre-sented. The proposed VLSI detects a stored reference word withthe minimum Manhattan distance between a 16-bit input wordand 16-bit stored reference words. The effective chip area, theswitching delay and the power dissipation of a new four-valuedfull adder, which is a key component of the proposed logic-in-memory VLSI, are reduced to about 33 percent, 67 percent and24 percent, respectively, in comparison with those of the cor-responding binary CMOS implementation under a 0.5-µm flashEEPROM technology.key words: pass-transistor network, oating-gate MOS transis-

tor, logic-in-memory structure, Manhattan distance, ash EEP-

ROM technology, four-valued full adder

1. Introduction

Communication bottleneck between memory and logicmodules is one of the most serious problems in recentdeep submicron VLSI systems, especially in the multi-media VLSI systems on a single chip [1]. A logic-in-memory structure, in which storage functions are dis-tributed over a logic-circuit plane, is a key technologyto solve the above problem [2]. When a small amountof storage is included in each cell of a logic-in-memoryVLSI array, its VLSI array may be regarded either asa logically enhanced memory array, or as a logic arraywhose elementary gates and connections can be pro-grammed to realize a desired logical behavior. How-ever, the VLSI array is more complex to build and haslower storage density than a normal memory because ofthe overhead involved in the storage and logic elements.

On the other hand, a floating-gate MOS transis-tor is generally used as a memory cell device of flashEEPROMs [3]. Since a floating-gate MOS transistorcan be utilized not only as a memory element but alsoas a switching one, the circuit design using floating-gate MOS transistors has a potential advantage to real-

Manuscript received January 25, 1999.Manuscript revised March 29, 1999.

†The authors are with the Department of Computer andMathematical Sciences, Graduate School of Information Sci-ences, Tohoku University, Sendai-shi, 980-8579 Japan.a) E-mail: [email protected]

ize high-performance VLSI systems with less communi-cation bottleneck between storage and logic elements.However, very few VLSI circuits using such floating-gate MOS transistors are designed and implemented ashardware accelerator in a special-purpose VLSI [4]–[6].

In this paper, a new logic-in-memory VLSI basedon pass-transistor logic [7], [8] and floating-gate MOStransistors, called “floating-gate-MOS pass-transistorlogic,” is proposed to merge storage and switchingfunctions in a multiple-valued-input and binary-outputcombinational logic circuit. The proposed logic-in-memory VLSI is useful for the realization of parallelarithmetic and logic circuits. Four basic operationssuch as AND (serial connection of pass transistors), OR(parallel connection of pass transistors), a threshold lit-eral and logic-value conversion are used to representarbitrary switching functions. Multiple-valued storeddata are represented by the threshold voltage of afloating-gate MOS transistor [9], so that both multiple-valued threshold-literal and pass-switch functions canbe merged by using a single floating-gate MOS transis-tor. Consequently, a compact pass-transistor networkcan be designed by using floating-gate MOS transistors.

As an efficient application, a logic-in-memory VLSIbased on four-valued floating-gate-MOS pass-transistorlogic is also presented to detect a stored reference wordwith the minimum Manhattan distance [10] betweena 16-bit input word and 16-bit stored reference words.The basic components of the proposed logic-in-memoryVLSI are mainly a four-valued adder and a winner-take-all (WTA) circuit [11]. The former can be designedcompactly by using floating-gate MOS pass-transistornetwork. Moreover, the use of precharge-evaluate logicin a floating-gate-MOS pass-transistor network makesit possible to reduce the power dissipation as well as toimprove the switching speed with less area penalty.

Since highly parallel logic operations and storagefunctions are merged in the pass-transistor network, thenumber of transistors is greatly reduced in the embed-ded four-valued adder. In fact, the effective chip area,the switching delay and the power dissipation of thefour-valued full adder in the proposed logic-in-memoryVLSI are reduced to about 33 percent, 67 percent and24 percent, respectively, in comparison with those ofthe corresponding binary CMOS implementation un-der a 0.5-µm CMOS technology.

HANYU and KAMEYAMA: MULTIPLE-VALUED LOGIC-IN-MEMORY VLSI1663

Fig. 1 Combinational logic-circuit model.

2. General Structure of a Floating-Gate-MOSPass-Transistor Network

Figure 1 shows a general structure of a combinationallogic circuit. It has two kinds of R-valued inputs,S (n-digit external inputs) and B (n-digit internal(stored constant) inputs), and binary outputs, Z (m-bit external outputs), where sj = {0, 1, · · · , R − 1},bj = {0, 1, · · · , R − 1} (1 ≤ j ≤ n) and zi = {0, 1}(1 ≤ i ≤ m). In the following description, we discussabout this type of a combinational logic circuit model.

2.1 Basic Components in a Four-Valued-Input Binary-Output Pass-Transistor Network

Figure 2(a) shows a general structure of a four-valued-input binary-output pass-transistor network [8]. Fourkinds of operations, AND, OR, a threshold literal andlogic-value conversion (LVC), are basic building blocksin the above pass-transistor network where AND andOR operations are performed by using series and par-allel connections of pass transistors, respectively.

LVC is an input-value converter in which an R-valued input value is converted into an arbitrary R-valued output value. LVC is a one-variable functionwhich is defined by f =< p0, p1, · · · , pn−1 > as

f(s) =

p0 if s = 0,p1 if s = 1,...

...pR−1 if s = R − 1

(1)

where pi ∈ {−1, 0, · · · , R−2, R−1}. Only a four-valuedLVC, f =< 3, 2, 1, 0 >, is used in Fig. 2(a).

A threshold literal is a four-valued-input binary-output function which is defined as

T (x, y) = Ty(x) ={

1 if x > y,0 otherwise (2)

where x ∈ {0, 1, · · · , R − 2, R − 1}, y ∈ {−1, 0, · · · , R −2, R − 1}. In the specification given in Fig. 2(b), fourthreshold literals, Ty1(x),Ty2(x),Ty3(x) and Ty4(x) areprogrammed as shown in Fig. 2(c) where a four-valuedstored input b is fixed at a logic value “2.” In this way,an arbitrary combinational logic circuit with a four-valued input and a binary output is designed by pro-gramming the threshold literals in Fig. 2(a).

Fig. 2 Pass-transistor network with four-valued inputs anda binary output.

2.2 Floating-Gate-MOS Pass-Transistor Network

A floating-gate MOS transistor is one of the key devicesto realize a logic-in-memory VLSI circuit, because itcan be used as a multiple-valued logic element as wellas a one-digit multiple-valued storage element.

Figure 3(a) shows a pass gate using a singlefloating-gate MOS transistor which merges a thresholdliteral into a pass-switch operation. The control-gatevoltage Vc and the threshold Voltage Vt in a floating-gate MOS transistor correspond to an external input xand a stored input y, respectively, whose relationshipsare given in R-valued logic as

Vc =Vdd

R − 1· x, (3)

Vt =Vdd

R − 1· (y + 0.5) (4)

where Vdd is a power supply voltage. In four-valued

1664IEICE TRANS. ELECTRON., VOL.E82–C, NO.9 SEPTEMBER 1999

Fig. 3 Floating-gate-MOS pass-transistor network.

Table 1 Relationship between logic values and voltage levels.

logic with Vdd = 5 V, Vc and Vt are given by Eqs. (3)and (4), respectively, as shown in Table 1. Using thisfloating-gate-MOS pass transistors, the combinationallogic circuit shown in Fig. 2(a) can be simply realizedas shown in Fig. 3(b).

3. Design of a Logic-in-Memory VLSI for theNearest Pattern Matching

As an efficient application of the multiple-valuedfloating-gate-MOS pass-transistor network, a highlyparallel and compact logic-in-memory VLSI to per-form the nearest pattern-matching operations betweena four-valued n-digit input word and a stored word isdesigned. The similarity between two words is calcu-lated by the Manhattan distance.

3.1 Hardware Algorithm

Figure 4 shows a block diagram of the logic-in-memoryVLSI for the nearest pattern matching. A four-valuedinput n-digit word A and the i-th stored word Bi(1 ≤i ≤ m) are expressed as

A =n∑

j=1

4n−j · aj , (5)

Bi =n∑

j=1

4n−j · bij (6)

Fig. 4 Logic-in-memory VLSI for the nearest patternmatching.

where aj and bij(1 ≤ j ≤ n) indicate the j-th digit ofA and Bi, respectively, and where aj , bij ∈ {0, 1, 2, 3}.The Manhattan distance Di between A and Bi is de-fined by the absolute value of the difference which isdescribed as

Di =| A − Bi | . (7)

In Eq. (7), there are two kinds of basic operations, sub-traction (A − Bi) and its absolute-value computation(ABS). Since the subtraction and its ABS for an inputA are performed in parallel by every word circuit, eachword circuit must be designed as compactly as possible.Hence, we choose a four-valued ripple-carry additionscheme to make the adder compact. Table 2 shows thetruth tables of a four-valued full adder, where the i-thsum is described by two-bit binary codes as (s2i, s2i−1),and where the i-th carry is described by a one-bit codeas ci.

Since the sums (s2i, s2i−1) are represented by thetwo’s complement expression, the output of ABS isdetermined by the carry cn from the most-significantdigit. Namely, if the difference (s2i, s2i−1) is negative,then cn becomes ‘1.’ Otherwise, cn = 0.

As a result, the Manhattan distance Di between Aand Bi shown in Eq. (7) is rewritten as

Di ={

(sn sn−1 · · · s2 s1) if cn = 0,(sn sn−1 · · · s2 s1) if cn = 1.

(8)

where si is the complement of si. The nearest pattern

HANYU and KAMEYAMA: MULTIPLE-VALUED LOGIC-IN-MEMORY VLSI1665

Table 2 Truth table of four-valued addition.

matching can be performed according to Eq. (8) in thei-th word, where the i-th output Oi from the word cir-cuit is described as

Oi =

1 if Di is the minimum of all theother Dk (k �= i) ,

0 otherwise.(9)

3.2 Circuit Realization

Figure 5(a) shows a circuit diagram of a four-valued fulladder based on floating-gate-MOS pass-transistor logic.The peripheral circuits to distribute four-valued inputvoltages in the logic-in-memory plane and to programone of five-valued threshold voltages in each floating-gate MOS transistor can be designed by using the al-most same peripheral ones in a multilevel NAND flashmemory [12]. The Block1 in Fig. 5 is the circuit fors2i−1 in case of ci−1, that is designed by the series-parallel connection of three floating-gate MOS transis-tors because three threshold literals are required in therealization of s2i−1. Similarly, the number of floating-gate MOS transistors in the other circuit blocks is alsodetermined by the number of the required thresholdliterals. As a result, a four-valued full adder can bedesigned by 34 transistors, in which four-valued stor-age functions are merged as well as an addition withfour-valued inputs and binary outputs. Figure 5(b)shows input and output waveforms of the proposedfour-valued full adder by using HSPICE simulation.The use of precharge-evaluate logic makes it possible toreduce the switching delay of the proposed full adderwith less area penalty. Moreover, all the outputs ofthe proposed pass-transistor network become compati-ble with standard binary CMOS gates because the bi-nary inverters are used as their output buffers.

Figure 6 shows a circuit and a layout of the ba-sic cell for the nearest pattern-matching operations. Itconsists of the proposed four-valued full adder with atwo-bit storage capability, two ABS circuits, a two-to-four encoder and a four-valued WTA circuit. The two-

(a) Circuit diagram

(b) HSPICE simulation

Fig. 5 Four-valued full adder.

bit outputs from a four-valued full adder are modifiedin the corresponding ABS circuits, respectively, wherethe absolute values of (s2i, s2i−1) are controlled bythe carry c8 from the most-significant digit as shownin Eq. (8). Since the WTA circuit is designed by thecurrent-mode logic [11], two-bit voltage-mode outputsfrom two ABS circuits are converted to a four-valuedcurrent-mode input in the WTA circuit by a two-to-four encoder. Figure 6(c) shows input and output wave-forms of a basic cell by using HSPICE simulation, wherethe equivalent circuit of a floating-gate MOS transistor

1666IEICE TRANS. ELECTRON., VOL.E82–C, NO.9 SEPTEMBER 1999

Fig. 6 Basic-cell structure of the logic-in-memory VLSI.

used in the HSPICE simulation is composed of a stan-dard nMOS transistor, a capacitor and a resistor asshown in Fig. 6(d). When a one-digit difference S is 3(the maximum value), the output of the WTA becomes0 in the simulation. In case of S = 2, the switchingdelay between an ABS and a WTA is maximum. Thereason is that another WTA input S′ on the same rowis set to 2 in the simulation. Since each component isdesigned simply in the basic cell, its critical path be-comes short enough, which results in a short switchingdelay in the basic cell.

Figure 7 shows a layout of the logic-in-memoryVLSI for the nearest pattern matching between twowords. The chip area is 11.2 × 16.0 mm2 under a stan-dard 0.5-µm flash EEPROM technology. This chipincludes 32,768 16-bit words whose stored data areprogrammable by changing the threshold voltage offloating-gate MOS transistors.

3.3 Evaluation

Since the basic components except the four-valued fulladder in a basic cell are simple enough, it is very im-portant to design a high-performance full adder. Todemonstrate the advantage of the proposed floating-gate-MOS pass-transistor network, we evaluate the per-formance of the proposed four-valued full adder with atwo-bit storage capability in comparison with that ofthree different two-bit adders. As shown in Fig. 8(a),a binary full adder with a one-bit storage capabil-ity is desinged by the combination of standard bi-nary CMOS gates. In addition to the combinationalcircuit for three-bit addition, six transistors are re-quired to store one bit using an Static RAM-like cell.Figure 8(b) shows another binary full adder, called‘Manchester Carry Adder’ using a pass-transistor net-work [13], where a one-bit storage element based on anSRAM-like cell is also required in the full adder. Thetotal number of transistors in the Manchester Carry

HANYU and KAMEYAMA: MULTIPLE-VALUED LOGIC-IN-MEMORY VLSI1667

Fig. 7 Overall structure of the logic-in-memory VLSI.

(a) Binary CMOS implementation

(b) Manchester carry adder

Fig. 8 Binary full adders.

Adder with a two-bit storage capability is less than halfin comparison with that of the binary CMOS imple-mentation shown in Fig. 8(a).

Table 3 summarizes the comparison of four-valuedfull adders under a 0.5-µm flash EEPROM technol-ogy. The precharge-evaluate logic design [14] is used to

Table 3 Comparison of four-valued full adders.

realize high-speed and low-power pass-transistor net-works such as the proposed four-valued full adder andthe Manchester Carry Adder. In the proposed four-valued full adder, a four-valued stored data bji is pre-liminarily programmed as the threshold voltages of thecorresponding floating-gate MOS transistors. Since afloating-gate MOS transistor is used as a storage el-ement for the stored data, no additional circuits forstorage are required in the proposed hardware, whichresults in reduced transistor counts. In contrast, whenstorage elements and logic functions are not merged inthe same circuits, the total transistor counts becomelarger.

Using the floating-gate-MOS pass-transistor net-work, the performance of the proposed logic-in-memoryVLSI is superior to those of any other ones in terms ofthe chip area and the power dissipation under the sameswitching speed. In fact, the chip area, the switchingdelay and the power dissipation of the proposed fulladder are reduced to about 33 percent, 67 percent and24 percent, respectively, in comparison with those ofthe corresponding binary CMOS implementation.

4. Conclusion

A new pass-transistor network using floating-gateMOS transistors has been proposed to design a high-performance combinational logic circuit with four-valued inputs and binary outputs. The design methodof the multiple-valued pass-transistor network is eas-ily utilized in a four-valued logic-in-memory VLSI. Itsperformance is much superior to that of an ordinarynon-logic-in-memory implementation in terms of areaand power dissipation under the same switching speed.The design concept to merge storage and switchingfunctions and to use floating-gate MOS transistors asa key device makes it possible to realize such a high-performance logic-in-memory VLSI architecture. Theproposed floating-gate MOS pass-transistor network issuitable for any combinational logic-circuit design withmultiple-valued external and stored inputs and binaryoutput. As a future prospect of the proposed multiple-valued logic-in-memory VLSI, it would be important to

1668IEICE TRANS. ELECTRON., VOL.E82–C, NO.9 SEPTEMBER 1999

design its peripheral circuits such as a charge-pumpingcircuit for a single supply voltage and to evaluate theseperformance.

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[5] T. Hanyu, K. Teranishi, and M. Kameyama, “Designand evaluation of a digit-parallel multiple-valued content-addressable memory” IEICE Trans. vol.J81-D-I, no.2,pp.151–156, Feb. 1998.

[6] T. Hanyu, K. Teranishi, and M. Kameyama, “Multiple-valued floating-gate-MOS pass logic and its application tologic-in-memory VLSI,” IEEE International Symposium onMultiple-Valued Logic, pp.270–275, May 1998.

[7] D. Radhakrishnan, S.R. Whitaker, and G.K. Maki, “For-mal design procedures for pass transistor switching circuits”IEEE J. Solid-State Circuits, vol.SC-20, no.2,pp.531–536,April 1985.

[8] A. Parameswar, H. Hara, and T. Sakurai, “A high speed,low power, swing restored pass-transistor logic basedmultiply and accumulate circuit for multimedia applica-tions,” Proc. IEEE 1994 Custom Integrated Circuits Conf.,pp.278–281, May 1994.

[9] T. Higuchi and M. Kameyama, Multiple-Valued DigitalProcessing System, Shokodo Co. Ltd., Tokyo, 1989.

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[11] J. Lazzaro, S. Ryckebusch, M.A. Mahowald, and C.A.Mead, “Winner-take-all network of O(N) complexity,” inAdvances in Neural Information Processing Systems 1 ed.D. Touretzky, Morgan Kaufmann, pp.703–711, San Mateo,CA, 1989.

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Takahiro Hanyu received the B.E.,M.E. and D.E. degrees in Electronic En-gineering from Tohoku University, Sen-dai, Japan, in 1984, 1986 and 1989, re-spectively. He is currently an Asso-ciate Professor in the Graduate Schoolof Information Sciences, Tohoku Univer-sity. His general research interests includemultiple-valued logic and its applicationto intelligent integrated systems. He re-ceived the Outstanding Paper Awards at

the 1985 and 1987 IEEE International Symposiums on Multiple-Valued Logic (with M. Kameyama et al.) and the Niwa MemorialAward in 1988. Dr. Hanyu is a member of the IEEE.

Michitaka Kameyama received theB.E., M.E. and D.E. degrees in Elec-tronic Engineering from Tohoku Univer-sity, Sendai, Japan, in 1973, 1975, and1978, respectively. He is currently a Pro-fessor in the Graduate School of Infor-mation Sciences, Tohoku University. Hisgeneral research interests include intel-ligent integrated systems for real-worldapplication and robotics, VLSIprocessorsfor highly-safe intelligent systems, and

multiple-valued VLSI systems. Dr. Kameyama received the Out-standing Paper Awards at the 1984, 1985, 1987, and 1989 IEEEInternational Symposiums on Multiple-Valued Logic, the Tech-nically Excellent Award from the Society of Instrument andControl Engineers of Japan in 1986, the Outstanding Transac-tions Paper Award from the IEICE in 1989, and the TechnicallyExcellent Award from the Robotics Society of Japan in 1990.Dr. Kameyama is a Fellow of the IEEE.