Page 1EL/CCUT T.-C. Huang Oct. 2002 TCH CCUT Introduction to IC Design Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech.

Page 1EL/CCUT T.-C. Huang Oct. 2002

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Introduction to IC DesignIntroduction to IC Design

Tsung-Chu Huang( 黃宗柱 )

Department of Electronic Eng.Chong Chou Institute of Tech.

Email: [email protected]

2003/9/29


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2003/9/29Switch Model and Complex Gate

Relay Logic MOS Switch – Why CMOS? Eular Path Complex Gate Homework #1


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Relay (Switching) Logic

1. 基本 Relay (Switch) Logic 只能表達 AND 及 OR 功能

2. 註：一組邏輯能組合出 {And, Or, Not} 稱Complete( 完整 ) ，例如 {NAND} 或 {NOR}

3.例： F=A(B+C)+D C

B

D

A


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Basic Model of a MOSFET

0

0.5

1

1.5

2 2.5

3

IDSS5

S9S13S1

7S21S2

5S29

0

20

40

60

80

100

120

140

160

Ids

VdsVgs

MOSFET Model


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Simple Switch Modelof an n-MOSFET

Vth


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Switch Intention

S

D

G B

S

D

G

0

0

D

S

G

V(1)

V(1)-Vth

D

S

G B

D

S

G

1

1 S

D

G

0

Vth


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CMOS( 互補金氧半 ) Logic

P 型網路

N 型網路

FX

1. P 型網路為 F(X) 的 Relay logic

2. N 型網路為 F(X) 的 Relay logicAND 與 OR 互換即可


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Stick Diagram1. 常用佈局表示法及簡化佈局法

1. 格子 (Grid) 狀文字 (Font) 表示法2. EDIF 為一種 ( 層次，對角座標 ) 的表示法3. Stick diagram: 草圖用，將不重要寬度省略

2. 例：

2/0.35

1/0.35


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例如： F=(A+B)(C+D)

因為 F=(A+B)(C+D)

N 型網路為： A B

C D

P 型網路為：

因為 F= A B + C D A

B

C

D

A B

C D

A

B

C

D


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尤拉路徑 (Euler Path)

1. 十八世紀拓樸學被用來簡化 CMOS 邏輯閘佈局

2. N 型路徑為 N 型 Relay-logic 網路3. P 型路徑為 P 型 Relay-logic 網路4.拓樸學證明各輸入開關 X 與 X 交叉通過！

BA

F

S

FD


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BA

尤拉路徑 (Euler Path) 佈局法

先畫出一倍寬度的 N+IMP

再畫出兩倍寬度的 P+IMP

VSS

VDD

BA

F

S

FD

S A F B S

D A B F


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FVdd

例如： F=(A+B)(C+D)

A B

C D

N

F

Vss

F A N C Vss D N B F

X A Vdd C D F B XX

A C D B

F

選擇路徑時，輸入要有相同的順序重遇點或切斷點均須命名！

標準邏輯元件， Stancard Cell通常等高，兩上下兩邊作

通道繞線 (Channel Routing)

A C B D F

Vss

Vdd Vdd

Vss

A C B D F


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Cell-Based Channel Routing

NANDNANDNOTAOINOTXORNORNAND

NANDNANDNOTAOI NOTXORNORNAND

NANDNAND NOTAOI NOTXORNORNAND


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Primitive Gates1. Primitive: A- -tomic (Cannot be cut off)

2. Properties of a CMOS Primitives:

• Either pulled up or pulled down;

• Current from or to the single output

• IDDQ=0 for Ideal CMOS

3. Usual Symbols:

• directly assembled without wire.

• {AND, OR} Combo ended with an Inverter


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Complex PrimitiveTrivial Example


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Usual Example and Naming

OAI231


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Switch Intention

S

D

G

0

0

D

S

G

1

1


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Pass Transistor as Switch

S D

G

DS

G


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Pass Transistor as Switch

1. Good p/n switch for 1/0 but bad for 0/1

2. CMOS Transmission gate – another compensated structure

3. Pass Transistor Logic (PTL)

1. VDD >> stages * Vth

2. Pulled-up or down


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Transmission Gate

BA

C

C

C

C

BA


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Tri-State

0

1

IN

High ImpedianceFloating (connection)

Hi-Z‘z’


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Tri-State Logic

AND 0 Z 1

0 0 0 0

Z 0 Z Z

1 0 Z 1

OR 0 Z 1

0 0 Z 1

Z Z Z 1

1 1 1 1


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2-to-1 Multiplexer

0

1

A

B

C

AC+BC


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TG-based Multiplexer

C

C

A

C

C

B


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TG-based Multiplexer

Bidirectional

No tri-state in ideal timing

Bus Contention possibly !


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Memory – Latches and Registers Prior to ’90s, they’re used to be confused. Latch: Level Sensitive Register: Edge Triggled 50’s Flipflop (Very slow frequency):

Later Flipflop:

Latch

LatchLatch


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Static Gate Based Latch

Example: Resettable D Latch

D

D

CLK

Q

D

D

CLK

QRESET

(a) (b) (c) (d)

D

D

Q

Q

R

CLK

D

D

Q

Q

R

CLK

QQ222 221

RESET


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Switch-Based Static Latch and Flipflop

D

CLK

Q

SkewSkew


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Home #1

1. Draw all 6-input AOI gates in structured style

2. Draw all possible structured stick diagrams of a primitive OAI32 using Eular-Paths

3. Thinking or Reading: 4-T XOR gate design; Write your afterthoughts in hundreds words.

Due: Oct. 27, 2003


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Preparation for Next Lecture

1. Prepare at least one SPICE-like tool (e.g., download the ORCAD/Design Lab 8.0 freeware)

2. Try to install and excise some simple example

Page 1EL/CCUT T.-C. Huang Oct. 2002 TCH CCUT Introduction to IC Design Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech.

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