Package Construction Analysis - TechInsights · PDF filePACKAGE CONSTRUCTION ANALYSIS SAMPLE REPORT REPORT ID#: 1006-00000-O-5P1-10 ii ii Table of Contents 1.0 Introduction

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PACKAGE CONSTRUCTION ANALYSIS SAMPLE REPORT THIS COPY SUPPLIED EXCLUSIVELY FOR THE USE OF:

TECHINSIGHTS

October 2006

IMPORTANT NOTICE REGARDING THE USE OF THIS REPORT: This report is protected by copyright and may not be copied or reproduced in any form without express written permission from TechInsights. It is the policy of TechInsights to provide its customers with extra copies of reports at a nominal cost. This report is sold subject to the condition that it shall not, by way of trade or otherwise, be re-sold, lent, hired out or otherwise circulated outside of the purchasing organization without the prior consent of TechInsights. TechInsights always endeavors to provide accurate and reliable information to its customers. However, it is not possible to guarantee absolute accuracy of all information contained herein and TechInsights can assume no liability for inadvertent errors in this report. This report was prepared for our Clients’ private study, analysis or research and for no other purpose. The information contained in this report may describe technical innovations, which are the subject of patents held by third parties. The disclosure by TechInsights of any such information is in no form whatsoever an inducement to infringe any patent. TechInsights assumes no liability for patent infringement arising from the use of the information contained in this report. Report ID#: 1006-00000-O-5P1-10 01/12/08 © 2009, UBM LLC

PACKAGE CONSTRUCTION ANALYSIS SAMPLE REPORT REPORT ID#: 1006-00000-O-5P1-10

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Table of Contents

1.0 Introduction ....................................................................................................................................1

1.1 Die Overview........................................................................................................................2

2.0 External Package Overview ...........................................................................................................4

2.1 External Overview................................................................................................................4

2.2 Radiography Overview.......................................................................................................11

3.0 Package Structure and Assembly .................................................................................................13

3.1 Substrate .............................................................................................................................13

3.2 Die Mounting......................................................................................................................26

3.3 Heat Spreader......................................................................................................................39

4.0 Critical Dimensions......................................................................................................................43

5.0 Major Findings .............................................................................................................................45


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List of Photographs

Photograph 1.1.1: Die photograph.....................................................................................................2

Photograph 1.1.2: Die markings........................................................................................................3

Photograph 2.1.1: Optical view of the top surface of the package....................................................4

Photograph 2.1.2: Optical view of the bottom surface of the package..............................................4

Photograph 2.1.3: Profile of the package edge..................................................................................5

Photograph 2.1.4: Identifier of PCB substrate...................................................................................6

Photograph 2.1.5: Discrete passives mounted on the base of the package substrate. .......................7

Photograph 2.1.6: Terminal attachments of the passive components. ..............................................8

Photograph 2.1.7: External connection lands are plated with gold. ................................................10

Photograph 2.2.1: Y view X-ray through package. .........................................................................11

Photograph 2.2.2: Features annotated onto Y view X-ray. .............................................................12

Photograph 3.1.1: Overall view of substrate in cross-section. ........................................................13

Photograph 3.1.2: Substrate identification. .....................................................................................14

Photograph 3.1.3: Die mounted onto the top surface of the PCB substrate. ...................................15

Photograph 3.1.4: 10 metallization levels on substrate. ..................................................................16

Photograph 3.1.5: Metal levels 1 through 4 interconnected with microvias. ..................................17

Photograph 3.1.6: Nickel plated onto attachment area of PCB metal. ............................................18

Photograph 3.1.7: Optical view of metals in attachment site. .........................................................19

Photograph 3.1.8: Attachment sites patterned by PCB solder mask. ..............................................20

Photograph 3.1.9: PCB metal levels 6 through 10. .........................................................................21

Photograph 3.1.10: Metal levels interconnected with microvias. .....................................................22

Photograph 3.1.11: External connection sites patterned on M10 and plated with nickel and gold...22

Photograph 3.1.12: Copper etched and nickel added in dual-plating process in passive attachment site. .....................................................................................................................23

Photograph 3.1.13: Passive attachment site. .....................................................................................24

Photograph 3.1.14: Plated metal layers on M10 and on attached capacitor terminal. ......................25

Photograph 3.2.1: Die attachment. ..................................................................................................26

Photograph 3.2.2: Optical view of copper pillar bumps in cross-section........................................29


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Photograph 3.2.3: SEM view of copper pillar bump in cross-section.............................................30

Photograph 3.2.4: Minimum width and pitch of CPBs in cross-section. ........................................30

Photograph 3.2.5: SEM view of the pillar attachment to the die metallization...............................31

Photograph 3.2.6: Edge of the 'neck' of the CPB showing the passivation and polyimidie layers. 32

Photograph 3.2.7: SEM view of UBM. ...........................................................................................32

Photograph 3.2.8: Optical view of tin plating on CPB....................................................................33

Photograph 3.2.9: Edge of a typical CPB showing the solder profile following the re-flow attachment process. ............................................................................................35

Photograph 3.2.10: General view of the die edge showing the underfill meniscus. .........................37

Photograph 3.2.11: Higher magnification image of the underfill material that contains silica filler particles. .............................................................................................................38

Photograph 3.3.1: Cross-section through mounted heat spreader. ..................................................39

Photograph 3.3.2: Thermal adhesive attachment of flange to PCB substrate. ................................40

Photograph 3.3.3: Higher magnification image of thermal adhesive..............................................40

Photograph 3.3.4: Plating layer on top surface of the copper heat spreader. ..................................41

Photograph 3.3.5: Plating layer on under surface of spreader.........................................................42

List of Figures

Figure 2.1.1: EDXS spectrum of the solder employed to attach discrete components. ...........9

Figure 3.1.1.1: EDXS of filler particle material in PCB solder mask. .......................................20

Figure 3.2.1: EDXS spectrum of the die adhesive material. ...................................................27

Figure 3.2.2: EDXS spectrum of the UBM material. ..............................................................28

Figure 3.2.3: EDXS spectrum of the copper pillar bump plating............................................34

Figure 3.2.4: EDXS spectrum of the copper pillar bump solder. ............................................36


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List of Tables

Table 4.0.1: Critical vertical dimensions. ..............................................................................43

Table 4.0.2: Critical horizontal dimensions. ..........................................................................44


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1.0 Introduction

The Dual-Core Intel® Xeon® microprocessor is Intel’s newest dual-core processor (DP) for dual processor servers and work stations. It delivers a new level of energy- efficient performance from the innovative Intel ® Core ™ microarchitecture, optimized for low-power, dual-core, 64 bit computing. This report analyzes the structural features of the 933 pin, land grid array (FC-LGA) package in which the processor is assembled in flip chip orientation. Analysis was performed using optical microscopy, Field Emission Scanning Electron Microscopy (FESEM), and Energy Dispersive X-ray Spectrometry (EDXS). Section 2.0 presents an overview of the external aspects of the package. The internal structures and materials are presented in Section 3.0 of the report, including the copper pillar bump (CPB) technology used to mount/connect the die to the package substrate. A summary of the critical horizontal and vertical dimensions is presented in table form in Section 4. Section 5 is a summary of the features found in the analysis of the package and assembly of the device.


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www.ubmtechinsights.com 1.1 Die Overview The previous dual-core Pentium D processor 920, code named Presler contains two separate dies in a LGA package. The current Dual-Core Intel® Xeon® 3.0 GHz contains a single die, is based on the state of the art, energy efficient Intel ® Core ™ microachitecture. The die measures 13.4 mm x 10.4 mm = 142 mm2. The die thickness is approximately 804 µm. The die markings include: MEROM © ¤ Intel 2005 Photograph 1.1.1 shows the die photograph of Dual-Core Intel® Xeon® processor.

Photograph 1.1.1: Die photograph.


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Photograph 1.1.2: Die markings.


4


2.0 External Package Overview

2.1 External Overview The Dual-Core Intel® Xeon® processor is packaged in a 933 Flip-chip land grid array (FC-LGA) package that interfaces with the motherboard via a LGS 933 socket. Optical views of the top and bottom of the package are shown in Photographs 2.1.1 and 2.1.2, respectively. Photograph 2.1.3 presents an optical image of the edge of the package in profile. The identification applied to the surface of the attached heat spreader indicates a date code of ’05 (2005) and lists an assembly and packaging site in Costa Rica. The full identification includes: 3.00GHZ/4M/1333 INTEL ® XEON® 5160 SL9RZ COSTA RICA

і ¤ © ‘ 05

3625A237 (e4)

Photograph 2.1.1: Optical view of the top

surface of the package.

Photograph 2.1.2: Optical view of the bottom

surface of the package.


5


Photograph 2.1.3: Profile of the package edge.


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The footprint of the package is the measure of the substrate that has horizontal dimensions of 37.8 mm x 37.8mm. The mounting flange formed around the periphery of an integrated heat spreader (HIS) that covers the die, is mounted onto and attached to the top surface of the package substrate with thermal adhesive. The heat spreader dimensions are smaller than the substrate, measuring 34.8 mm by 34.8 mm. See Photograph 2.1.1. A 2-D matrix number is applied to the package substrate beside Intel’s unique unit identifier ATPO serial number shown in Photograph 2.1.4. 35620306 A0304

Photograph 2.1.4: Identifier of PCB substrate.


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Multiple discrete decoupling capacitors and five ceramic chip resistors are mounted in the central region of the bottom of the package substrate. The component terminals are attached to landings on the substrate metallization with tin-rich solder. The material content was identified using EDXS probing, with the spectrum presented as Figure 2.1.1. The use of tin-rich solder signifies this component as compliant to RoHS requirements.

Photograph 2.1.5: Discrete passives mounted on the base of the package substrate.


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Photograph 2.1.6: Terminal attachments of the passive components.


9


Figure 2.1.1: EDXS spectrum of the solder employed to attach discrete components.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Energy (keV)

Coun

ts

Sn

Sn

Sn

Sn

Sn


10


External connection lands are patterned on the bottom surface of the package substrate, defined by the surface solder mask and plated with a layer of gold metallization. The diameter of each land is 0.62 and the pitch is 0.84 mm.

.

Photograph 2.1.7: External connection lands are plated with gold.


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2.2 Radiography Overview Photograph 2.2.1 is a radiograph of the device X-rayed in the Y view. The package features and components are annotated onto the image in Photograph 2.2.2. There is a single die mounted onto the substrate on the surface opposite the passive components.

Photograph 2.2.1: Y view X-ray through package.

Pin 1 Indicator


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Photograph 2.2.2: Features annotated onto Y view X-ray.


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3.0 Package Structure and Assembly

3.1 Substrate Photograph 3.1.1 is an optical image showing the package in cross-section. A single die is mounted onto the top surface of the PCB (Printed Circuit Board) substrate, and covered with a heat spreader, the flange of which is attached to the periphery of the PCB with adhesive. Discrete passive components are mounted onto the opposite surface of the PCB. Identification applied to the PCB substrate is shown in Photograph 3.1.2 and includes: D33605 01 S75

Photograph 3.1.1: Overall view of substrate in cross-section.


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Photograph 3.1.2: Substrate identification.


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The PCB substrate is 1.35 mm in thickness and constructed conventionally with a FR fibre-filled core and copper metallization levels. The resin-fibre core is 635 µm thick. The copper levels on either side of the core are 62 µm thick and are connected with Plated Through Hole (PTH) vias. The length of the PTH is 830 µm. With a diameter of 134 µm, the aspect ratio of the PTH (L/D) is 6.3/1. The PTH is filled with a carbon-based epoxy than contains irregularly shaped silica particles. Photographs 3.1.3 and 3.1.4 show the substrate in cross-section.

Photograph 3.1.3: Die mounted onto the top

surface of the PCB substrate.


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Photograph 3.1.4: 10 metallization levels on substrate.

M5 connected to M6 with PTH technology vias. There are 10 levels of copper metallization, 5 on either side of the central FR core. The metallization levels are arbitrarily designated 1 through 10 from the die surface to the external connection side of the substrate. The outer metal levels are interconnected using microvias. Metal levels 1, 2 and 3 on one side of the central core, are slightly over 16 µm in thickness as are Metal levels 8, 9 and 10 on the opposite side of the core. Metals 4 and 7 are approximately 27 µm thick. Photographs 3.1.5 and 3.1.9 are images showing the upper and lower level metal profiles, respectively.

M1M2

M3M4

M5

M7M8

M9M10

M6


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Each metal level is separated by an IMD (Inter-Metal Dielectric) level and a solder mask is applied to both the top and bottom of the PCB. Photograph 3.1.5 presents the upper levels of PCB metal in cross-section.

Photograph 3.1.5: Metal levels 1 through 4

interconnected with microvias.


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The solder mask over the metal 1 level, defines the landings for the copper pillar connections to the PCB. The surface of the copper is etched prior to the nickel plating that is deposited using a dual plating process. The final nickel thickness is 5.5 µm. Photographs 3.1.6 and 3.1.7 are optical images of the nickel plating on metal 1 lines. A seed layer of lead-tin (Pb-Sn) solder is applied to the nickel plating, using the solder mask for patterning. Nickel-tin intermetallics are formed at the interface. Photograph 3.1.8 shows the edge of the solder mask which is a carbon based resin containing barium sulphate and silica particles as filler. The EDXS (Energy Dispersive X-ray Spectrometry) spectrum identifying the filler particle materials, is presented as Figure 3.1.1.

Photograph 3.1.6: Nickel plated onto attachment area of PCB metal.


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Photograph 3.1.7: Optical view of metals in attachment site.


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Photograph 3.1.8: Attachment sites patterned by PCB solder mask.

Figure 3.1.1.1: EDXS of filler particle material in PCB solder mask.

1E+001E+012E+013E+014E+015E+016E+017E+018E+019E+011E+021E+021E+021E+021E+022E+022E+022E+022E+022E+022E+022E+022E+022E+022E+023E+023E+02

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Energy (keV)

Coun

ts

Ba

BaBa

Ba

S

Si

C

O(Pt)


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Photograph 3.1.9 is a SEM image of Metals 6 through 10 of the substrate in cross-section. The levels are separated with dielectric layers and are interconnected using microvias, similar to the structures of Metals 1 through 5. The external lands are patterned by the solder mask on the outer surface of Metal 10. The copper metal is etched slightly prior to adding nickel plating in a dual-plate process. The nickel layer formed is 5.8 µm in thickness. A thin layer of gold that is 4.0 µm thick, is deposited over the nickel. Similarly, Metal 10 is etched and plated in the landing sites for the externally attached discrete passives. Photographs 3.1.9 through 3.1.13 show the substrate metal layers 6 through 10.

Photograph 3.1.9: PCB metal levels 6 through 10.


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Photograph 3.1.10: Metal levels interconnected with microvias.

Photograph 3.1.11: External connection sites patterned on

M10 and plated with nickel and gold.


23


Photograph 3.1.12: Copper etched and nickel added in

dual-plating process in passive attachment site.


24


Photograph 3.1.13: Passive attachment site.


25


Photograph 3.1.14: Plated metal layers on M10 and

on attached capacitor terminal.


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3.2 Die Mounting The single die in the Dual-Core Intel® Xeon® processor is mounted in flip chip presentation, with the backside of the silicon substrate attached to the underside of the heat spreader with a generous wetting of indium-rich adhesive. The attach material is 168.6 µm in thickness. Photograph 3.2.1 shows a section of the adhesive at one edge of the die and the meniscus formed at the die edge. Figure 3.2.1 is an EDXS spectrum of the die attach adhesive, showing the indium rich material.

Photograph 3.2.1: Die attachment.


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Figure 3.2.1: EDXS spectrum of the die adhesive material.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Energy (keV)

Coun

ts

(Cu)

In

In

In

In In


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The die is mounted onto the top surface of the substrate PCB and connected to the PCB metallization layer using copper pillar bump technology. Copper pillar bumps are applied at the wafer level. The passivation layer and die coating over the passivation are patterned to expose the pad areas on the die. An under-bump metal (UBM) layer of titanium that is 11.0µm thick is deposited over the connection site as a metal liner and extends over the walls of the passivation and polyimide. Copper is then deposited onto the titanium, forming the ‘neck’ of the pillar. Figure 3.2.2 is an EDXS spectrum that identifies titanium in the UBM layer.

Figure 3.2.2: EDXS spectrum of the UBM material.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Energy (keV)

Coun

ts

(Pt)

(Cu)

(Cu)

(Cu)

Ti

Ti


29


A general view of the copper bumps attached to the top surface of the PCB and the die pads, is presented in Photograph 3.2.1. Closer views are shown in Photographs 3.2.2 and 3.2.3. Photograph 3.2.4 shows the CPB pitch as 320 µm and the width of a single CPB to be 102.5 µm.

Photograph 3.2.2: Optical view of copper pillar bumps in cross-section.


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Photograph 3.2.3: SEM view of copper pillar bump in cross-section.

Photograph 3.2.4: Minimum width and pitch of CPBs in cross-section.


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Photograph 3.2.5 presents in more detail, the neck of the copper pillar bump attached to a landing site patterned onto the die metallization. A closer view of one edge of the pillar neck in Photograph 3.2.6, shows that the copper neck is defined by the passivation layer on the die surface and the polyimide coating. Photograph 3.2.7 is a SEM image that is slightly tilted to show the extension of the UBM layer over the etched walls of the passivation. The EDXS spectrum of the UBM can be viewed in Figure 3.2.2, showing that the metal layer is primarily titanium.

Photograph 3.2.5: SEM view of the pillar attachment

to the die metallization.


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Photograph 3.2.6: Edge of the 'neck' of the CPB showing

the passivation and polyimidie layers.

Photograph 3.2.7: SEM view of UBM.


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The body of the copper pillar bump is most probably defined using a thick deposition of photoresist or partially cured polyimide that is subsequently removed once the pillar is formed. The copper bump is 50 µm in thickness, not including the neck of the pillar. The surface of the pillar is plated with tin (Sn), forming a layer approximately 3.5 µm in thickness over the copper body. Photograph 3.2.8 is an optical view of the edge of one copper pillar with the tin plating layer exposed. EDXS probing at the tin to solder interface, indicated the presence of gold, although no discrete layer of gold was visible. There was possibly a pre-existing coating of gold that became incorporated into the intermetallics at the interface during the reflow process.

Photograph 3.2.8: Optical view of tin plating on CPB.


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Figure 3.2.3: EDXS spectrum of the copper pillar bump plating.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Energy (keV)

Coun

ts

Cu

Cu

Cu

Sn

Sn

Sn

Sn Sn

Pb

Pb

Au


35


The outer surface of the tin plating is covered with lead-tin (Pb-Sn) solder. Solder is also deposited onto the nickel plating of the PCB substrate landing sites, and the flip-chip attachment is achieved using a solder reflow process once the die is mounted in place on the PCB metallization. Photograph 3.2.9 is a SEM view of the edge of a typical bump attachment. Photographs 3.2.2 and 3.2.5 show a thin solder wetting on the left surface of the copper pillar, while Photographs 3.2.3 and 3.2.4 show solder thinning to be prevalent on the right surface of the pillar, suggesting misalignment in the process. Figure 3.2.2 is an EDXS spectrum of the solder used in connecting the CPBs to the substrate, showing the presence of both lead (Pb) and tin (Sn).

Photograph 3.2.9: Edge of a typical CPB showing the

solder profile following the re-flow attachment process.


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Figure 3.2.4: EDXS spectrum of the copper pillar bump solder.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Energy (keV)

Coun

ts

Sn

Sn

Sn

Sn

Sn

Sn

Pb

Pb


37


With bump attachment complete, underfill material is infused between the die surface and substrate to reduce mechanical, thermal and moisture stress on the bumps. Photograph 3.2.10 is a SEM image showing the meniscus of underfill formed around the periphery of the die. Photograph 3.2.11 is a higher magnification view at the underfill to solder mask interface. The underfill material appears to be a conventional epoxy-based resin with spherical-shaped silica particle filler.

Photograph 3.2.10: General view of the die edge

showing the underfill meniscus.


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Photograph 3.2.11: Higher magnification image of the underfill

material that contains silica filler particles.


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3.3 Heat Spreader Photograph 3.3.1 is an optical view of the heat spreader in cross-section, mounted over the die. The periphery of the spreader is formed with a depressed flange that is attached to the surface of the substrate with a thermal adhesive. The thick central portion of the spreader is connected to the back surface of the silicon die with an indium-rich adhesive. Photograph 3.3.2 is a SEM view of the flange attachment on one edge of the spreader. The thermal adhesive contains carbon, silicon and oxygen and is directly attached to the solder mask of the PCB substrate.

Photograph 3.3.1: Cross-section through mounted heat spreader.


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Photograph 3.3.2: Thermal adhesive attachment

of flange to PCB substrate.

Photograph 3.3.3: Higher magnification image of thermal adhesive.


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The heat spreader is fabricated with copper base metal that is 1.86 mm thick in the central area, thinning to 0.88 mm in the flange area. The copper is plated on both surfaces with nickel. The plating on the top surface is 4.1 µm thick, while the under surface is slightly thinner at 3.6 µm Photographs 3.3.4 and 3.3.5 are optical views of the nickel plating on the top and bottom surfaces of the heat spreader respectively.

Photograph 3.3.4: Plating layer on top surface of the copper heat spreader.


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Photograph 3.3.5: Plating layer on under surface of spreader.


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4.0 Critical Dimensions

All measurements are (±5% ) unless otherwise indicated.

Feature Vertical Dimension

Heat Spreader External Thickness (Copper) 0.88 – 1.86 mm Heat Spreader Plating 3.6 – 4.1 µm nickel Substrate Overall Thickness 1.35 mm Solder Mask Thickness Top surface: 21 µm – 37.1 µm

Bottom surface: 21 µm – 38 µm Substrate Metallization Thickness M1: 16.2 µm

M2: 16.8 µm M3: 16.5 µm M4: 27.0 µm M5: 62.0 µm

M6: 62.0 µm M7: 27.2 µm M8: 16.8 µm M9: 16.8 µm M10: 16.8 µm

Metallization Plating Layers on Metal level 1 5.5 µm nickel Metallization Plating Layers on Metal level 10 5.8 µm nickel

4.0 µm gold FR4 Thickness (Fibre-Resin Core) 635 µm PTH Height 830 µm

Attachment Thickness 168.6 µm Die Thickness 804 µm

Die

Polyimide Coating Thickness 4.3 µm Eutectic solder between bump and landing ~ 30 µm Copper Bump Height 50 µm Copper Bump Plating 3.5 µm tin UBM Thickness 0.11 µm

Overall Package Thickness 4.0 mm (including heat spreader and PCB)

Table 4.0.1: Critical vertical dimensions.


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Feature Horizontal Dimension

Overall Package Size 37.8 mm x 37.8 mm (1428.8 mm2 ) Substrate Size 37.8 mm x 37.8 mm (1428.8 mm2 ) Substrate Metallization (Min. Width/Pitch observed)

M1: Unknown M2: 26 µm M3: Unknown M4: Unknown M5: 120 µm

M6: Unknown M7: Unknown M8: 26 µm M9: Unknown M10: 168 µm

PTH plating thickness 23 µm Heat Spreader (including flange) 34.8 mm x 34.8 mm External Contact Lands Diameter 0.62 mm External Contact Lands Pitch 0.84 mm Die Size 13.4 mm x 10.4 mm (142 mm2 ) Copper Pillar Width 102.5 µm Copper Pillar Pitch 320 µm

Table 4.0.2: Critical horizontal dimensions.


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5.0 Major Findings

The Dual-Core Intel® Xeon® processor is mounted in flip chip presentation and packaged in a land grid array (LGA) package with an attached heat spreader. The die is connected to the substrate metallization using copper pillar bump (CPB) technology. The major findings of the package structural analysis include:

• 933 land grid array (LGA) package; • Package contains a single die mounted in flip-chip presentation; • Die is fabricated with copper metallization on 804 µm thick silicon substrate; • The passivation layer on the die surface is silicon nitride; • Passivation layer is patterned to leave pad areas uncovered; • Polyimide coating covering the passivation is similarly patterned; • Die is electrically connected to the substrate metallization using copper pillar bump (CPB)

technology; • Edges of the etched passivation and polyimide are coated with the under bump metal (UBM)

layer added to the pad areas; • The UMB is titanium that is approximately 11 µm thick; • The neck of the copper pillar is formed on the UBM, defined by the passivation and polyimide

layers; • The body of the pillar section of copper is 50 µm thick and probably defined by a patterned

polyimide or cured photoresist that is subsequently removed; • The copper pillar bump is plated with 3.5 µm thick layer of tin that is probably overplated

with a thin layer of gold; • The minimum pitch of the CPB appears to be 320 µm; • The tin layer on the CPB is plated with lead (Pb) – tin (Sn) solder as is the landing on the

substrate metallization; • A solder reflow process forms the connection of the die to the substrate; • Underfill material which is a resin containing silica filler particles is infused between the

surfaces of the die and substrate to provide support and protection for the CPB structures; • The package substrate defined the footprint size of the package; • Package dimensions are 37.8 mm x 37.8 mm producing an area of 1428.8 mm2 ; • The package substrate is constructed with a fibre-filled resin core Printed Circuit Board (PCB) with

five (5) levels of copper metallization deposited on either side of the core; • The levels of metallization on either side of the core are copper interconnect with copper

microvias; • Metal levels 5 and 6 are connected through the core using Plated Through Hole (PTH)

technology; • Both surfaces of the PCB are coated with solder mask layers; • Solder mask on the die surface of the PCB is patterned to define landing sites for the CPBs; • Solder mask on the outer surface of the PCB is patterned to provide landing sites for the

passive components to be attached and external connection sites;


46


• All landing sites in the copper metallization are plated with nickel; • External attachment sites are also plated with a gold layer; • Passive components are attached to the PCB using tin-rich solder; • A copper heat spreader that is plated with nickel, is attached to the PCB with thermal

adhesive; • The backside of the die silicon is attached to the underside of the heat spreader with indium-

rich adhesive; • Passive components (ceramic chip capacitors and resistors) are mounted/connected to the PCB

metallization on the outer surface; • Terminals of the passive components are attached using lead-free solder.

Package Construction Analysis - TechInsights · PDF filePACKAGE CONSTRUCTION ANALYSIS SAMPLE REPORT REPORT ID#: 1006-00000-O-5P1-10 ii ii Table of Contents 1.0 Introduction

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