PAC1934 Four-Channel DC Power/Energy Monitor with ...ww1.microchip.com/downloads/en/DeviceDoc/20005850B.pdfFour Channel DC Power/Energy Monitor with Accumulator PAC1934 DS20005850B-page

PAC1934 Four Channel DC Power/Energy Monitor with Accumulator

Features

• High-Side Current Monitor

- 100 mV full scale range for current sense voltage,16b resolution default setting

- Selectable bidirectional current sense capa-bility, –100 mV to +100 mV range, 16-bit two’s complement (signed) data format

- External sense resistor sets full scale current range

- Very low input current simplifies routing

• Wide Bus Voltage Range for Voltage Monitor

- 0V to 32V input common-mode voltage

- 16-bit resolution for voltage measurements, 14b are used for power calculations

• Real Time Auto-Calibration of Offset and Gain Errors for Voltage and Current, No User Adjust-ment Required

• 1% Power Measurement Accuracy over a Wide Dynamic Range

• On-Chip Accumulation of 28-bit Power Results for Energy Measurement

- 48-bit power accumulator register for record-ing accumulated power data

- 24 bit Accumulator Count

- User programmable sampling rates of 8, 64, 256 and 1024 samples per second

- 17 minutes of power data accumulation mini-mum at 1024 S/s

- >36 hours of power data accumulation mini-mum at 8 S/s

• 2.7V to 5.5V Supply Operation

- Separate VDD I/O pin for digital I/O

- 1.62-5.5V capable SMBus and digital I/O

- SMBus 3.0 and I2C Fast Mode Plus (1Mb/S)

• SMBus Address - 16 Options, set with Resistor

• No Input Filters Required

• ALERT Features that can be Enabled:

- ALERT on accumulator overflow

- ALERT on Conversion Complete

• 2.225 x 2.17 mm WLCSP Package

Applications

• Notebook and Tablet Computing

• Networking

• Automotive

• Cloud, Linux and Server Computing

• Industrial

• Linux Applications

Description

The PAC1934 device is a four-channel energy monitor,with bus voltage monitor and current sense amplifiers thatfeed high-resolution ADCs. Digital circuitry performs powercalculations and energy accumulation.

This enables energy monitoring with integration periodsfrom 1 ms up to 36 hours or longer. Bus voltage, senseresistor voltage and accumulated proportional power arestored in registers for retrieval by the system master orEmbedded Controller.

The sampling rate and energy integration period can becontrolled over SMBus or I2C. Active channel selection,one-shot measurements and other controls are also config-urable by SMBus or I2C.

The PAC1934 uses real time calibration to minimize offsetand gain errors. No input filters are required for this device.

Package TypesPAC1934 – Top View

2.225 x 2.17 mm WLCSP

For more details, see Table 3-1 and Section 7.0.

A

B

C

D

1 2 3 4

SENSE1+SENSE1-SENSE2+

SENSE2-

SENSE3+

SENSE3-

SENSE4+SENSE4-

GND

SM_DATA

SM_CLK

VDD

VDD I/O

ADDRSEL

PWRDN

SLOW/ALERT

2017 Microchip Technology Inc. DS20005850B-page 1

PAC1934

Device Block DiagramVDD GND

VDD I/O

ADDRSEL

SLOW/ALERT

Accumlator

Differentia l VSENS E

Amplifier

VBUS Buffer/Divider

SM_CLK

SM_DATA

PWRDN

I 2C/S

MB

us

ADC/MUX Clocking & Control

VBUS Registers

VSENS E Registers

VPOWE R Registers

Accumulator Registers

Control Registers

Calculation and

Calibration

16-bitADC

16-bitADC

Resistor Decoder

SENSE 1+

SENSE 1-

SENSE 2+

SENSE 2-

SENSE 3+

SENSE 3-

SENSE 4+

SENSE 4-

VBUS1

VBUS2

HighVoltage

MUX

VBUS4

Sense1+

Sense2+

Sense1-

Sense2-

Sense3+Sense3-

Sense4+Sense4-

VBUS3

DS20005850B-page 2 2017 Microchip Technology Inc.

PAC1934

1.0 ELECTRICAL CHARACTERISTICS

1.1 Electrical Specifications

Absolute Maximum Ratings(†)

VDD pin...........................................................................................................................................................–0.3 to 6.0V

Voltage on SENSE- and SENSE+ pins...........................................................................................................–0.3 to 40V

Voltage on any other pin to GND ........................................................................................................GND –0.3 to +6.0V

Voltage between Sense pins (|(SENSE+ – SENSE–)|).........................................................................................500 mV

Input current to any pin except VDD ....................................................................................................................±100 mA

Output short-circuit current.............................................................................................................................. Continuous

Junction to Ambient (J-A) ...................................................................................................................................+78°C/W

Operating Ambient Temperature Range .................................................................................................... –40 to +150°C

Storage Temperature Range...................................................................................................................... –55 to +150°C

ESD Rating – all pins – HBM...................................................................................................................................4000V

ESD Rating – all pins – CDM ..................................................................................................................................2000V

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.This is a stress rating only and functional operation of the device at those or any other conditions above those indicatedin the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended peri-ods may affect device reliability.

ESD Protection Diagram

This diagram represents the ESD protection circuitryon the PAC1934. These pins are allowed to be at 32Vif VDD is at zero. The back to back diodes between theSense+ and Sense– pins have 1 kΩ resistors in serieswith them.

SM_DATA SM_CLK ADDRSEL VDD I/O VDD GNDCLAMP

CIRCUIT

SENSE1-

SENSE1+

(Floating ESD rail)

(~40v breakdown)

SENSE2-

SENSE2+

SENSE3-

SENSE3+

SENSE4-

SENSE4+

PWRDNSLOW/ALERT


PAC1934

TABLE 1-1: DC CHARACTERISTICS

Electrical Characteristics: Unless otherwise specified, maximum values are at TA = –40°C to +85°C, VDD = 2.7V to 5.5V, VDD I/O= 1.62V to 5.5V, VBUS = 0V to 32V; typical values are at TA = +25°C VDD = VDD I/O = 3.3V, VBUS = 32V, VSENSE = (SENSE+ – SENSE–) = 0V

Characteristic Symbol Min. Typ. Max. Unit Conditions

Power Supply

VDD Range VDD 2.7 — 5.5 V

VDD I/O Range VDD I/O 1.62 — 5.5 V

VDD Pin Active Current

IDD — 585 675 µA All 4 measurement channels enabled. 1024 Samples/s

VDD Pin Active Current

IDD SLOW — 16 — µA 4 channels enabled, 8 Samples/s

Minimum VDD Rise Rate

VDD_RISE_MIN — 0.05 — V/ms 0 to 5V in 100 ms

Maximum VDD Rise Rate

VDD_RISE — 1000 — V/ms 0 to 5V in 5 µs

VDD Sleep Current IDD_SLEEP — 5 — µA Sleep State

VDD Power-Down Current

IDD_PWRDN — 0.1 — µA Power-Down State

VDD I/O Current IDD I/O — — 2 µA All States

Analog Input Characteristics

VBUS Voltage Range VBUS –0.2V — 32 V Common mode range for SENSE+ and SENSE– pins, referenced to ground (negative range not tested in production)

VSENSE Differential Input Voltage Range

VSENSE_DIF –100 — 100 mV

SENSE+, SENSE– Pin Input Current

ISENSE +, ISENSE- –7 0 7 µA VSENSE+ = VSENSE– = 32V(Input current is the combined cur-rent for the two pins)

SENSE+, SENSE– Pin Input current

ISENSE +, ISENSE- –1 0 1 µA VSENSE = 6V, VSENSE– = 5.9V

VSENSE Measurement Accuracy

VSENSE Gain Accuracy

VSENSE_

GAIN_ERR

— ±0.2±1

±0.9 %%

At +25°Ctypical, –40 to +85°C

VSENSE Offset Accuracy, referenced to input

VBUS_

OFFSET_ERR

— ±0.02±0.2

±0.1 mVmV

At +25C°typical, –40 to +85°C

VSENSE – Unidirectional Currents

VSENSEADC Resolution

VSENSE_RES — — 16 Bits Straight Binary for unidirectional currents

VSENSE Full Scale Range

VSENSE_FSR 0 — 100 mV Unidirectional currents

VSENSE LSB Step Size

VSENSE_LSB — 1.5 — µV Unidirectional currents

VSENSE – Bidirectional Currents

VSENSE ADC Resolution

VSENSE_RES — — 16 bits 16-bit two’s complement (signed)

VSENSE Full Scale Range

VSENSE_FSR –100 — 100 mV Bidirectional currents


PAC1934

VSENSE LSB Step Size

VSENSE_LSB — 3 — µV Bidirectional currents

VBUS Measurement Accuracy

VBUS Gain Accuracy VBUS_GAIN_ERR — ±0.02±0.2

±0.5 %%


VBUS Offset Accu-racy, referenced to input

VBUS_

OFFSET_ERR

— ±1±2

— LSBLSB


VBUS – Unipolar Voltages

VBUS ADC Resolution

VBUS_RES — — 16 bits Straight Binary for unidirectional currents

VBUS UnipolarFull-Scale Range

VBUS_FSR 0 — 32 V Unipolar voltage

VBUS LSB Step Size VBUS_LSB — 488 — µV FSR = 32V, 16-bit resolution

VBUS – Bipolar Voltages

VBUS ADC Resolution VBUS_RES — — 16 bits 16-bit two's complement (signed) numbers are reported for VBUS measurement result

VBUS BipolarFull-Scale Range

VBUS_FSR –32 — 32 V Mathematical scaling. Physics limits the negative input voltage to –0.2V

VBUS LSB Step Size VBUS_LSB — 976 — µV Bipolar voltages

TABLE 1-1: DC CHARACTERISTICS (CONTINUED)




PAC1934

Power Accumulator Accuracy

Accumulator Error ACC_Err — 0.2 — % VSENSE = 97 mV

Accumulator Error ACC_Err — 0.2 — % VSENSE = 10 mV

Accumulator Error ACC_Err — 1 — % VSENSE = 1 mV

Accumulator Error ACC_Err — 3 — % VSENSE = 100 µV

Accumulator Error ACC_Err — 5 — % VSENSE = 50 µV

Active Mode Timing

Pull-Up Voltage Range

VPULLUP 1.62 — 5.5 V Pull-up voltage for I2C/SMBus pins and digital I/O pins. Set by VDD I/O.

Time to First Communications

tINT_T — 14.25 — ms

Transition From Sleep State to Start of Conversion Cycle

tSLEEP_TO_ACTIVE — 3 — ms

Digital I/O Pins (SM_CLK, SM_DATA, SLOW/ALERT, PWRDN)

Input High Voltage VIH VDD I/O x 0.7

— — V

Input Low Voltage VIL — — VDD I/O x 0.3

V

Output Low Voltage VOL — — 0.4 V Sinking 8 mA for the ALERT pin and 20 mA for the SMCLK pin

Leakage Current ILEAK –1 — +1 µA

TABLE 1-1: DC CHARACTERISTICS (CONTINUED)




PAC1934

FIGURE 1-1: SMBus Timing.

TABLE 1-2: SMBUS MODULE SPECIFICATIONS

Electrical Characteristics: Unless otherwise specified, maximum values are at TA = –40°C to +85°C, VDD = 2.7V to 5.5V, VBUS = 0V to 32V; Typical values are at TA = +25°C, VDD = 3.3V, VBUS = 32V, VSENSE = (SENSE+ – SENSE–) = 0V, VDD I/O = 1.62V to 5.5V

Characteristic Sym. Min. Typ. Max. Units Conditions

SMBus Interface

Input Capacitance CIN — 4 10 pF Not tested in production

SMBus Timing

Clock Frequency fSMB .010 — 1 MHz No minimum if Time-Out is not enabled.

Spike Suppression tSP 0 — 50 ns

Bus Free Time Stop to Start

tBUF 0.5 — — µs Per SMBus 3.0

Hold Time after Repeated Start Condition

tHD:STA 0.26 — — µs Per SMBus 3.0

Repeated Start Condition Setup Time

tSU:STA 0.26 — — µs Per SMBus 3.0

Setup Time: Stop tSU:STO 0.26 — — µs Per SMBus 3.0

Setup Time: Start tSU:STA 0.26 — — µs

Data Hold Time tHD:DAT 0 — — µs

Data Setup Time tSU:DAT 50 — — ns Per SMBus 3.0 (Note 1)

Clock Low Period tLOW 0.5 — — µs Per SMBus 3.0

Clock High Period tHIGH 0.26 — 50 µs

Clock/Data Fall Time tFALL — — 120 ns Not tested in production

Clock/Data Rise Time tRISE — — 120 ns Not tested in production

Capacitive Load CLOAD — — 550 pF Per bus line,CLOAD not tested in production

SLOW Pin Pulse Width SLOWpw — 100 — µs Pulses narrower than 100 µS may not be detected

Note 1: A device must internally provide a hold time of at least 300 ns for the SM_DATA signal (with respect to theVIH(min) of the SM_CLK signal) to bridge the undefined region of the falling edge of SM_CLK.

SMDATA

SMCLK

TLOW

TRISE

THIGH

TFALL

TBUF

THD:STA

P S S - Start Condition P - Stop Condition

THD:DAT TSU:DA

TTSU:STA

THD:STA

P

TSU:STO

S


PAC1934

NOTES:


PAC1934

2.0 TYPICAL OPERATING CURVES

Note: Unless otherwise indicated, maximum values are at TA = –40°C to +85°C, VDD = 2.7V to 5.5V, VBUS = 0V to 32V;typical values are at TA = +25°C, VDD = 3.3V, VBUS = 3.3V, VSENSE = (SENSE+ – SENSE–) = 0V, VDD I/O = 1.62 to 5.5V.

FIGURE 2-1: VSENSE Error vs. VSENSE Input Voltage.

FIGURE 2-2: VSENSE Error vs. VSENSE Input Voltage Bidirectional Mode.

FIGURE 2-3: VSENSE Error vs. VSENSE Input Voltage vs. Temperature.

FIGURE 2-4: VSENSE Error vs. VSENSE Input Voltage and Temperature.

FIGURE 2-5: VSENSE Error vs. VSENSE Input Voltage Bidirectional Mode (Zoom View).

FIGURE 2-6: VSENSE Error vs. VSENSE and Common Mode.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.

10uV 100uV 1mV 10mV 100mV-10

5

0

5

10

Sense Input Voltage

Err

or

(pe

rce

nt)

3.3vDC 25oC

-80 -60 -40 -20 0 20 40 60 80

-0.025%

0.0125%

0

0.0125%

0.025%

Sense Input Voltage (mV)

Err

or

(%F

ull

Sc

ale

)

CM3.3v 3.3vDC 25oC

0 20mV 40mV 60mV 80mV 100mV

-0.1%

-0.15%

-0.05%

0

0.05%

Sense Input Voltage

Err

or

(%F

ull

Sc

ale

)

Ch1 3.3vDC -40oC

Ch1 3.3vDC 0oC

Ch1 3.3vDC 25oC

Ch1 3.3vDC 85oC

Ch1 3.3vDC 125oC

1uV 10uV 0.1mV 1mV 10mV 100mV

-15

-10

-5

0

5

10

15

20

25

Sense Input Voltage

Err

or

(pe

rce

nt)

3.3vDC -40oC

3.3vDC 0oC

3.3vDC 25oC

3.3vDC 85oC

3.3vDC 125oC

-1mV -0.5mV 0 0.5mV 1mV-0.025%

0.025%

0.0125%

-0.0125%

0

Sense Input Voltage

Err

or

(%F

ull

Sc

ale

)

CM3.3v 3.3vDC 25oC

0 20mV 40mV 60mV 80mV 100mV

0.025%

0

-0.025%

0.05%

-0.05%

Sense Input Voltage

Err

or

(%F

ull

Sc

ale

)

CM1v 3.3vDC 25oC

CM3v 3.3vDC 25oC

CM5v 3.3vDC 25oC

CM16v 3.3vDC 25oC

CM32v 3.3vDC 25oC


PAC1934

FIGURE 2-7: VBUS Error vs. VBUS Input Voltage.

FIGURE 2-8: VBUS Error vs. VBUS Input Voltage (Zoom View).

FIGURE 2-9: VBUS Error vs. VBUS Input Voltage.

FIGURE 2-10: VBUS Error vs. VBUS Input Voltage vs. Temperature.

FIGURE 2-11: VBUS Error vs. VBUS Input Voltage vs. Temperature (Zoom View).

FIGURE 2-12: VBUS Error vs. VBUS Input Voltage vs. Temperature (Bipolar Voltage Mode).

1mV 10mV 0.1V 1V 10V

0

5

10

15

20

25

Input Voltage

Err

or

(pe

rce

nt)

3.3vDC 25oC

10mV 100mV 1V 10V-2%

-1%

0

1%

2%

Input Voltage

Err

or

(pe

rce

nt)

3.3vDC 25oC

0 5 10 15 20 25 30

-0.05%

0

0.05%

-0.1%

Input Voltage

Err

or

(%F

ull

Sc

ale

)

3.3vDC 25oC

1mV 10mV 0.1V 1V 10V0

5

10

15

20

25

Input Voltage

Err

or

(pe

rce

nt)

3.3vDC -40oC

3.3vDC 0oC

3.3vDC 25oC

3.3vDC 85oC

3.3vDC 125oC

10mV 100mV 1V 10V 32V-2%

-1%

0

1%

2%

Input Voltage

Err

or

(pe

rce

nt)

3.3vDC -40oC

3.3vDC 0oC

3.3vDC 25oC

3.3vDC 85oC

3.3vDC 125oC

-0.5v 0v 0.5v 1v

0.1%

0

-0.2%

-0.4%

-0.6%

-0.8%

Input Voltage

Err

or

(%F

ull

Sc

ale

)

3.3vDC -40oC

3.3vDC 0oC

3.3vDC 25oC

3.3vDC 85oC

3.3vDC 125oC


PAC1934

FIGURE 2-13: VBUS Error vs. VBUS Input Voltage vs. Temperature.

FIGURE 2-14: Zero Input Histogram for VBUS (LSBs, 8X Average Results).

FIGURE 2-15: Zero Input Histogram for VSENSE (LSBs, 8X Average Results).

FIGURE 2-16: Input Offset for VBUS Measurements vs. Temperature.

FIGURE 2-17: Input Offset for VSENSE Measurements vs. Temperature.

FIGURE 2-18: I2C/SMBus Drive Current vs. VOL.

0v 5v 10v 15v 20v 25v 30v

-0.1%

-0.2%

0.2%

0

0.1%

Input Voltage

Err

or

(%F

ull

Sc

ale

)

3.3vDC -40oC

3.3vDC 0oC

3.3vDC 25oC

3.3vDC 85oC

3.3vDC 125oC

-40 0 25 55 85 125-1

-0.8

-0.6

-0.4

-0.2

0

Temperature (oC)

DC

Off

se

t (L

SB

's 1

5b

+s

ign

)

-40 0 25 55 85 125-1

-0.8

-0.6

-0.4

-0.2

0

Temperature (oC)

DC

Off

se

t (L

SB

's 1

5b

+s

ign

)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.70

10

20

30

40

50

60

70

SMBUS Output Voltage (VOL)

SM

BU

S D

riv

e C

urr

en

t (I

OL

) m

A

VIO=1.6v VDD=2.6vVIO=5.5v VDD=5.5v


PAC1934

FIGURE 2-19: IDD vs. Temperature and Supply at 1024 Samples/Second.

FIGURE 2-20: IDD in SLOW Mode vs. Temperature and VDD.

FIGURE 2-21: IDD for VDD I/O pin vs. Temperature and VDD.

FIGURE 2-22: IDD vs.Temperature, VDD, and Sample Rate.

FIGURE 2-23: IDD in SLEEP Mode vs. Temperature and VDD.

FIGURE 2-24: IDD in Power Down Mode vs. Temperature and VDD.

-40 0 25 55 85 125520

540

560

580

600

620

640

Temperature (oC)

1k

Sp

s m

od

e C

urr

en

t (u

A)

2.6v2.7v3.3v5.0v5.5v5.6v

-40 0 25 55 85 12510

20

30

40

50

60

Temperature (oC)

8S

ps

mo

de

Cu

rre

nt

(uA

)

2.6v2.7v3.3v5.0v5.5v5.6v

-40 0 25 55 85 125

0

0.05

0.1

0.15

Temperature (oC)

VIO

Cu

rre

nt

(uA

)

VDD 2.6v/VIO 1.7vVDD 5.6v/VIO 1.7vVDD 2.6v/VIO 5.6vVDD 5.6v/VIO 5.6v

-40 0 25 55 85 1250

100

200

300

400

500

600

700

Temperature (oC)

Ac

tiv

e C

urr

en

t (u

A)

2.6v2.7v3.3v5.0v5.5v5.6v

1kSps

256 Sps

16 Sps

8 Sps

-40 0 25 55 85 1250

5

10

15

20

25

30

Temperature (oC)

Sle

ep

mo

de

Cu

rre

nt

(uA

)

2.6v2.7v3.3v5.0v5.5v5.6v

-40 0 25 55 85 1250

2

4

6

8

10

12

Temperature (oC)

Po

we

rDo

wn

Cu

rre

nt

(uA

)

2.6v2.7v3.3v5.0v5.5v5.6v


PAC1934

FIGURE 2-25: VSENSE Input Current - Active Mode, 1024 Samples/Second.

FIGURE 2-26: VBUS Input Leakage Current vs. VDD and Temperature.

FIGURE 2-27: VBUS Input Current - Active Mode, 1024 Samples/Second.

FIGURE 2-28: VSENSE Input Leakage Current vs. VDD and Temperature.

-40 0 25 55 85 125-0.5

0

0.5

1

1.5

2

Temperature (oC)

Av

era

ge

Cu

rre

nt

1k

Sp

s (

uA

)

0v CM1v CM5v CM16v CM32v CM

-40 0 25 55 85 1250.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Temperature (oC)

Le

ak

ag

e C

urr

en

t (u

A)

0v1v5v16v32v

-40 0 25 55 85 1250

0.5

1

1.5

2

2.5

Temperature (oC)

Av

era

ge

Cu

rre

nt

1k

Sp

s (

uA

)

0v1v5v16v32v

-40 0 25 55 85 1250

0.005

0.01

0.015

0.02

0.025

0.03

Temperature (oC)

Le

ak

ag

e C

urr

en

t (u

A)

0v CM1v CM5v CM16v CM32v CM


PAC1934

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

3.1 SenseN+/SenseN– (N=1,2,3,4)

These two pins form the differential input for measuringvoltage across a sense resistor in the application. Thepositive input (SenseN+) also acts as the input pin forbus voltage.

3.2 Ground (GND)

System ground.

3.3 SMBus Data (SM_DATA)

This is the bi-directional SMBus data pin. This pin isopen drain, and requires a pull-up resistor to VDD I/O.

3.4 SMBus Clock (SM_CLK)

This is the SMBus clock input pin.

3.5 Positive Power Supply Voltage (VDD)

Power supply input pin for the device. 2.7-5.5V range,bypass with 100 nF ceramic capacitor to ground nearthe IC.

3.6 Digital Power Reference Voltage (VDD I/O)

Connect this pin to the power supply voltage for the dig-ital controller driving the SMBus pins and digital inputpins for the device, 1.62V-5.5V. Bypass with 100 nFceramic capacitor to ground near the IC. This pin doesnot supply power, instead it acts as the VIH reference.

3.7 Address Selection (ADDR_SEL)

Connect a resistor from this pin to ground to selectSMBus address.

3.8 Enable pin (PWRDN)

Power down input pin for the device, active low.

3.9 SLOW/ALERT

In default mode, if this pin is forced high, sampling rateis forced to 8 samples/second. When it is forced low,the sampling rate is 1024 samples/second unless a dif-ferent sample rate has been programmed.This pin maybe programmed to act as the ALERT pin, in ALERTmode the pin needs a pull-up resistor to VDD I/O.

TABLE 3-1: PIN DESCRIPTIONS

PAC1934WLCSP16

Symbol Pin Type Description

A3 SENSE1+ 32V analog in 0-32V range, Connect to supply side of sense resistor

A2 SENSE1– 32V analog in 0-32V range, Connect to load side of sense resistor

A1 SENSE2+ 32V analog in 0-32V range, Connect to supply side of sense resistor

B1 SENSE2– 32V analog in 0-32V range, Connect to load side of sense resistor

D1 SENSE3+ 32V analog in 0-32V range, Connect to supply side of sense resistor

C1 SENSE3– 32V analog in 0-32V range, Connect to load side of sense resistor

D3 SENSE4+ 32V analog in 0-32V range, Connect to supply side of sense resistor

D2 SENSE4– 32V analog in 0-32V range, Connect to load side of sense resistor

B4 GND Ground pin Ground for the IC

D4 SM_DATA SMBus data I/O Open drain requires pull-up resistor to VDD I/O

C4 SM_CLK SMBus clock Input Clock Input pin

A4 VDD Power for IC Positive power supply voltage

B2 VDD I/O Sets VIH reference for digital I/O

Digital power reference level for digital I/O

C2 ADDRSEL Analog I/O pin Address selection for the SMBus Slave address

B3 PWRDN Digital input pin Voltage range is set by VDD I/O pin. Active low puts the device in power-down state (all circuitry is powered down including SMBus).

C3 SLOW/ALERT Digital I/O pin Voltage range is set by VDD I/O pin. Default function is SLOW, may be programmed to function as ALERT pin (Open Collector when functioning as ALERT, requires pull-up resistor to VDD I/O).


PAC1934

4.0 GENERAL DESCRIPTION

The PAC1934 is a four-channel, bidirectional, high-sidecurrent-sensing device with precision voltagemeasurement capabilities, DSP for power calculationand a power accumulator. It measures the voltagedeveloped across an external sense resistor (VSENSE)to represent the high-side current of a battery orvoltage regulator. The PAC1934 also measures theSENSE+ pin voltages (VBUS). Both VBUS and VSENSEare converted to digital results by a 16-bit ADC, and the

digital results are multiplied to give VPOWER. TheVPOWER results are accumulated on-chip, whichenables energy measurement over the accumulationperiod.

The PAC1934 has an I2C/SMBus interface for digitalcontrol and reading results. It also has digital supplyreference VDD I/O that is to be connected to the samesupply as the digital master for the I2C/SMBUS,enabling digital I/O voltages as low as 1.62V.

A system diagram is shown in Figure 4-1.

FIGURE 4-1: PAC1934 System Diagram.

Note: VDD and VDD I/O may be connected together.

PAC1934 System Master

SM_DATA

SM_CLK

VSOURCE 0V – 32V

Sense Resistors

VDD

1.62V to 5.5V Digital Supply

GND

2.7V to 5.5V

SEN

SE1+

SEN

SE1-

SEN

SE2+

SEN

SE2-

SEN

SE3+

SEN

SE3-

SEN

SE4+

SEN

SE4-

VSOURCE 0V – 32V

VSOURCE 0V – 32V

VSOURCE 0V – 32V

Load

Load

Load

Load

SLOW

PWRDN

ADDRSEL

VDD I/O


PAC1934

FIGURE 4-2: PAC1934 Functional Block Diagram.

FIGURE 4-3: PCB Pattern for Sense Resistor.

Figure 4-3 shows the recommended PCB pattern forsense resistor with wide metal for the high-current path.The drawing shows metal, solder paste openings andresistor outline. VSOURCE connects to the +terminal of thehigh-current path, and the load connects to the –terminalof the high-current path. Sense+ and Sense– have a Kel-vin connection to the current sense resistor to ensure thatno metal with high current is included in the VSENSE mea-surement path. Sense+ and Sense– are shown as a dif-ferential pair, route them as a differential pair to the Senseinputs at the chip.

VDD GND

VDD I/O

ADDRSEL

SLOW/ALERT

Accumlator

Differentia l VSENS E

Amplifier

VBUS Buffer/Divider

SM_CLK

SM_DATA

PWRDN

I 2C/S

MB

us

ADC/MUX Clocking & Control

VBUS Registers

VSENS E Registers

VPOWE R Registers

Accumulator Registers

Control Registers

Calculation and

Calibration

16-bitADC

16-bitADC

Resistor Decoder

SENSE 1+

SENSE 1-

SENSE 2+

SENSE 2-

SENSE 3+

SENSE 3-

SENSE 4+

SENSE 4-

VBUS1

VBUS2

HighVoltage

MUX

VBUS4

Sense1+

Sense2+

Sense1-

Sense2-

Sense3+Sense3-

Sense4+Sense4-

VBUS3


PAC1934

4.1 Detailed Description

A high-voltage multiplexer connects the input pins tothe VBUS and VSENSE amplifiers. The amplifier outputsare sampled simultaneously for each channel, con-verted by 16 bit ADCs and processed for gain and off-set error correction. After each conversion, VBUS andVSENSE are multiplied together to give VPOWER.

An internal oscillator and digital control signals controlthe two ADCs and the mux. The mux sequentially con-nects each channel’s amplifiers to the ADC inputs.

The PAC1934 measures the source-side voltage,VBUS, and the voltage VSENSE across an external cur-rent sense resistor, RSENSE.

4.1.1 INITIAL OPERATION AND ACTIVE STATE

After POR and a start-up sequence, the device is inthe ACTIVE state and begins sampling the inputssequentially. Voltage and current are sampled for allactive channels and power is calculated and accumu-lated. All active channels are sampled at 1024 sam-ples/second by default. Sample rates of 256, 64 or 8samples/second may be programmed over I2C orSMBus. If the SLOW pin is asserted the sample rate is8 samples per second. For sampling rates lower than1024 samples/second, the device is in Sleep mode fora portion of the conversion cycle, which results inlower power dissipation. If fewer than four channelsare active, power is also reduced.

To read accumulator data and reset the accumulators,the REFRESH command is used. To read the voltage,current, power and accumulator data without resettingthe accumulators, the REFRESH_V command isused. Changes to the control register (01h) are acti-vated by sending either REFRESH or REFRESH_V.When a new value is written to the Control Register(01h), the new values take effect at the end of the nextround-robin sampling cycle following the nextREFRESH or REFRESH_V command.

4.1.2 REFRESH COMMAND

The master sends the REFRESH command afterchanging the Control Register and/or before readingaccumulator data from the device. The master controlsthe accumulation period in this manner.

The readable registers for the VBUS, VSENSE, Power,accumulator outputs and accumulator count areupdated by the REFRESH command and the valueswill be static until the next REFRESH command.These readable registers will be stable within 1 mSfrom sending the REFRESH command, and may beread by the master at any time up until the nextREFRESH command is sent. The internal accumulatorvalues and accumulator count will be reset by theREFRESH command, but the sampling of the inputs,

data conversion and power integration is not inter-rupted and will continue as determined by the settingsin the control register.

Changes written to the control and configuration regis-ters take effect 1 mS after a REFRESH command issent. Any new commands written within this 1 mS win-dow will be ignored and NACKed to indicate that theyare ignored.

The values for VBUS and VSENSE measurement resultsand Power calculation results respond to theREFRESH command in the same fashion as the accu-mulators and accumulator count. The readable regis-ters will be stable within 1 mS from sending theREFRESH command and may be read by the masterat any time. The internal values continue to beupdated according to the sampling plan determined bythe settings in the CONTROL register. The results thatare sent to the readable registers for VBUS, VSENSEand Power are the values from the most recent com-plete conversion cycle. See Register 6-1 REFRESHCommand (Address 00h).

4.1.3 REFRESH_G COMMAND

The REFRESH_G is identical in every respect to theREFRESH command, but it is used with the I2C Gen-eral Call address (0000 000). This allows the systemto issue a REFRESH command to all of the PAC1934devices in the system with a single command. Thenthe data from this REFRESH_G command may beread device by device to capture a snapshot of thesystem power and energy for all devices. SeeRegister 6-12 REFRESH_G COMMAND (Address1Eh). Note that the REFRESH_G command can alsobe used with a valid Slave Address but in this caseonly the device with this Slave Address will receive thecommand. In other words it has the same propertiesas the REFRESH command with the possibility ofbeing compatible with the I2C General Call address.

4.1.4 REFRESH_V COMMAND

If the user wants to read VSENSE and VBUS results, themost recent Power calculation, and/or the accumulatorvalues and count without resetting the accumulators,the REFRESH_V command may be sent. Sending theREFRESH_V command and waiting 1 mS ensuresthat the VSENSE, VBUS, Power, accumulator and accu-mulator count values will be stable when read by themaster. The sampling of the inputs, data conversionand power integration are not interrupted and will con-tinue as determined by the settings in the CONTROLregister. The data in these readable registers willremain stable until the next REFRESH orREFRESH_V command.The internal accumulator val-ues and accumulator count are unaffected by theREFRESH_V command.

Note that the REFRESH_V command may also beused to activate changes to the CONTROL register,just like the REFRESH command, except with the


PAC1934

REFRESH_V command changes to the control regis-ter will be enacted without resetting the accumulatorsor accumulator count. See Register 6-13REFRESH_V COMMAND (Address 1Fh).

4.1.5 SLEEP STATE

The SLEEP state is a lower power state than theACTIVE state. While in this state, the device will drawa supply current of ISLEEP from the VDD pin. Thedevice automatically goes to this state between con-version cycles when sampling rates lower than 1,024samples/second are selected, or if fewer than fourchannels are active. All digital states and data areretained in the SLEEP state. The device can also beput in the SLEEP state by setting the SLEEP bit fol-lowed by a REFRESH or REFRESH_V command, andsampling will resume when the SLEEP bit is clearedfollowed by a REFRESH of REFRESH_V command.The device does not go into SLEEP state based onany other condition such as static conditions on theSMBus pins. If SMBus Timeout is enabled, it is sup-ported in SLEEP mode or ACTIVE mode.

4.1.6 POWER-DOWN STATE

The Power-Down state is entered by pulling thePWRDN pin low. In this state, all circuits on the chipincluding the SMBus pins are inactive, and the deviceis in a state of minimum power dissipation.

In the Power-Down state, no data is retained in thechip (neither register configuration nor measurementdata). When the PWRDN pin is pulled high, integra-tion, measurement and accumulation will begin usingthe default register settings, as described in paragraph3.1.1 above. The first measurement data may berequested by a REFRESH or REFRESH_V command20 ms after the PWRDN pin is pulled high.

4.1.7 PROGRAMMING THE SAMPLE RATE AND THE SLOW PIN

The default sampling rate after power-up is 1024 sam-ples/second. Sampling rates of 256, 64 or 8 sam-ples/second may be programmed in the CTRLREGISTER (Address 01h) (Register 6-2). Any time anew sample rate is programmed, it does not take effectuntil a REFRESH, RERESH_G, or REFRESH_V com-mand is received. When any of these REFRESH com-mands are received, any round-robin sampling cycle inprogress will complete before the new sampling ratetakes effect.

If one of these lower sample rates is used, power dissi-pation is reduced. The round-robin sampling and con-version cycle is exactly the same, but the device goesinto the sleep state between conversion cycles. SeeSection 2.0 “Typical Operating Curves”.

If the SLOW pin is pulled high, the device will sampleat eight samples/second. No matter what the pro-grammed sample rate, this new SLOW sample rate

will take effect on the next conversion cycle (if around-robin conversion cycle is in process when theSLOW pin goes high, that conversion cycle will com-plete before the SLOW sample rate takes effect.)

If the device is programmed for Single Shot mode, andthe SLOW pin is asserted, the first sampling will beginwithin 125 ms after the SLOW pin is asserted.

If the device is in the SLEEP state, asserting theSLOW pin will not cause sampling to start.

Whenever the SLOW pin changes state, a limitedREFRESH or REFRESH_V command may be exe-cuted by the chip hardware (default is REFRESH).Like any other REFRESH command, this resets theaccumulators and accumulator count for a REFRESHcommand, and updates the readable registers foreither REFRESH or REFRESH_V. These are limitedREFRESH commands because no programmedchanges to the control or status registers take effect(control and status registers means registers 01h,1Ch, 1Dh, and 20h-26h). The readable registers arestable with the new values within 1 ms of the SLOWpin transition.

The SLOW register enables selection of REFRESH orREFRESH_V on the SLOW pin transitions, whichallows this function to be disabled for either edge, andalso tracks both the state of the SLOW pin and transi-tions on the SLOW pin. See Register 6-14, SLOW(Address 20h).

This is the default functionality of the SLOW pin, but itmay be reconfigured to function as an ALERT pin (seeparagraph Section 4.4 “ALERT Functionality”). Ifthe SLOW pin is configured to serve as an ALERT pin,the slower sampling rate of eight samples/second isonly available by programming the CONTROL register01h.

4.2 Conversion Cycles

A conversion cycle for the device consists of analog todigital conversion being complete for all channels(including the real-time calibration that is part of eachconversion cycle). Immediately following the data con-version, the power results are calculated for that chan-nel and the power value is added to the accumulator.Averaged values for VSENSE and VBUS are alsoupdated internally as part of each conversion cycle.

Data conversion and processing is performed for eachactive channel in sequential fashion until all activechannels have been converted, completing the con-version cycle for the device. The sequential samplingof each channel, along with the calculation time andany sleep time needed to set the overall sampling rate,is referred to as a round-robin sampling period.


PAC1934

4.3 Conversion Cycle Controls

4.3.1 REDUCING THE NUMBER OF CHANNELS TO BE SAMPLED

Program Register 6-10 CHANNEL_DIS and SMBus(Address 1Ch) to reduce the number of channels thatare active. The sample rate is unaffected, but powerdissipation is reduced if some channels are disabled.Any or all channels may be disabled; if all channelsare disabled, the device goes into sleep mode.

4.3.2 SINGLE SHOT MODE

The Control register also allows the device to operatein Single Shot mode. In Single Shot mode, all activechannels will sample and convert once, followed byresults being calculated. The accumulator and accu-mulator count operate the same as for continuous con-version mode, accumulating each single shot powercalculation and incrementing the accumulator count.The conversion cycle will start when the REFRESHcommand (or REFRESH_V or REFRESH_G) is sent.

After the single shot measurements and calculationsare complete, the device will go into SLEEP mode. AREFRESH, REFRESH_G or REFRESH_V commandmay be sent to read the data. The user needs to wait3 ms after the REFRESH command before command-ing another Single Shot conversion by means of send-ing one of the REFRESH commands. This is becausea 1 ms delay is required between Refresh commands,and coming out of Sleep requires 2 ms.

4.4 ALERT Functionality

The ALERT functionality can serve two purposes: tonotify the system that a conversion cycle for all activechannels is complete, or to notify the system that theaccumulator or accumulator count has overflowed.

4.4.1 USING THE ALERT FUNCTION

To use the ALERT function, configure the SLOW pin tofunction as ALERT using the Register 6-2. For thisconfiguration, the ALERT pin must have a pull-up toVDD I/O (it will function as an open drain output). If apull-up resistor is attached to the pin for ALERT func-tionality, the device will power up in SLOW mode. Anyof the four sample rates can be programmed using theCTRL Register 01h.

The ALERT function for Accumulator Overflow canalso be used without reconfiguring the SLOW pin, bymonitoring the OVF bit in the CTRL REGISTER(Address 01h) Register 6-2.

4.4.2 ALERT AFTER COMPLETE CONVERSION

The Register 6-2 has a bit ALERT_CC that can beused to enable the ALERT_CC function. If this bit isset, the ALERT pin will go low for 5 μS after each com-plete conversion cycle is complete.

4.4.3 ALERT ON ACCUMULATOR OVERFLOW

If the ALERT function is enabled, and any of the accu-mulators or the accumulator count overflows, theALERT pin may be used to notify the system. Toenable this trigger for the ALERT pin, bit 1 in the CTRLREGISTER (Address 01h) Register 6-2 must be set.Note that the OVF bit in the CTRL REGISTER(Address 01h) Register 6-2, will be set when theseoverflows occur.

4.4.4 CLEARING ALERT AND OVF

When the ALERT function has been tripped by accu-mulator or accumulator count overflow, it will remainasserted until a REFRESH command is received.REFRESH_G will also clear the OVF bit and theALERT function, but REFRESH_V will not.


PAC1934

4.5 Voltage Measurement

The VBUS voltage for each channel is measured by theSENSE+ pin for each channel. A high-voltage multi-plexer is connected to each SENSE+ pin, and the mul-tiplexer sequentially connects each SENSE+ input toand ADC for conversion. The result is stored in a 16-bitVBUS results register and the 14 MSBs are multiplied bythe VSENSE number for the VPOWER results value. TheVPOWER results are accumulated in the accumulator.

Full-Scale Voltage (FSV) is 32V by default. The devicemay be programmed for bipolar VBUS measurements.in this bipolar mode, the mathematical range for nega-tive VBUS numbers is –32V, the actual range is limitedto about –200mV due to physical factors. This bipolarcapability for VBUS enables accurate offset measure-ment and correction. For bipolar operation, the 16-bitVBUS result is a twos complement (signed) number.

The measured voltage at SENSE+ can be calculatedusing Equation 4-1.

EQUATION 4-1: BUS VOLTAGE

4.6 Current Measurement

The PAC1934 includes high-side current sensing cir-cuits. These circuits measure the voltage (VSENSE)induced across a fixed external current sense resistor(RSENSE) and store the voltage as a 16-bit number inthe VSENSE Results registers.

The PAC1934 current sensing operates with aFull-Scale Range (FSR) of 100 mV in unidirectionalmode (default).

When sensing unidirectional currents (the defaultmode), the ADC results are presented in straight binaryformat. For bidirectional current sensing, the ADCresults are in two’s complement (signed) format. Forbipolar current measurements, the range is ±100 mV,but use FSR = 100 mV in the equations that follow. Forbest accuracy on current values near zero, it is recom-mended to use the bidirectional current mode and 8xaverage current results.

4.7 Selecting RSENSE Values

RSENSE can easily be calculated if you know the maxi-mum current you want to sense, as shown inEquation 4-2.

Consider that you may need to select a value for IMaxthat includes current peaks well beyond your nominalcurrent.

EQUATION 4-2: CALCULATING RSENSE

Full-Scale Current (FSC) can be calculated fromEquation 4-3.

EQUATION 4-3: FULL-SCALE CURRENT

The actual current through RSENSE can then be calcu-lated using Equation 4-4.

EQUATION 4-4: SENSE CURRENT

VSource 32V VBUS

Denominator-----------------------------------=

Where:

VSOURCE = The measured voltage on the SENSE+ pin

VBUS = The value read from the VBUS Results Registers

Denominator = 216 for unipolar measurements

= 215 for bipolar measurements

Rsense FSRImax-------------=

Where:

FSR = Full Scale VSENSE voltage input

RSENSE = External RSENSE resistor value

IMax = Maximum current to measure

FSC 100 mVRSENSE----------------------=

Where:

FSC = Full-scale current

RSENSE = External sense resistor value

ISENSE

FSC VSENSE

Denominator-----------------------------------=

Where:

ISENSE = Actual bus current

FSC = Full-scale current value (from Equation 4-3)

VSENSE = The value read from the VSENSE Results Registers

Denominator = 216 for unipolar measurements

= 215 for bipolar measurements


PAC1934

4.8 ADC Measurements, Offset, and 8x Averaging

The PAC1934 is primarily desired for energy measure-ments where many power readings are accumulated.This is inherently an averaging process. Individual volt-age and current measurements can also benefit fromaveraging to reduce noise and offset. Averaged valuesare internally calculated for VBUS and VSENSE, with arolling average of the most recent eight values presentin the VBUSn_AVG (Register 6-7) andVSENSEn_AVG (Register 6-6) registers. The averageis updated internally after every conversion cycle. Thereadable registers are updated with REFRESH,REFRESH_V, or REFRESH_G commands like all theother readable results registers. These averagedresults should be used for the most accurate, lowestnoise and lowest offset measurements.

The ADC channels use a special offset canceling tech-nique. If the user observes the unaveraged results fornear-zero values of VBUS and VSENSE, they mayobserve a cyclical pattern of offset variation. The usermay think this is noise, but in fact it is due to internal cir-cuitry switching through different permutations of offsetcancellation circuitry. This small variation in unaver-aged offset is canceled in the 8x averaged result. It isalso canceled in the Power Accumulator results. Theoverall effect is offset that is consistently very close tozero LSB over supply and temperature variations.

The offset canceling technique is illustrated inFigure 4-4. It is very difficult to accurately observe, as itis a challenge to read the data from every conversioncycle. The effect of capturing data points at a rate thatdoes not correspond exactly to the internal samplingrate of the PAC1934 can make these permutationsappear less periodic and deterministic than they areinside the chip. The data conversion uses one of thepermute positions 1-4 for each input on each conver-sion, cycling through all four permutations in four con-versions. When averaged the Permute Enabled resultshown below is realized, evenly distributed aroundzero.

FIGURE 4-4: Illustration of the Four Permute Combinations that the ADC Cycles through and the Resulting Low Average Offset. Each Bin Represents One Code.

Results from both the VBUS and VSENSE ADCs are 17btwo's complement (signed) internally. There is an addi-tional bit of resolution that is not accessible from theresults register. The NEG_PWR (Address 1Dh) registerdetermines whether the conversion results arereported in the readable registers as unipolar or bipolarnumbers. Using bipolar numbers can give more accu-rate results for very small numbers that may actually benegative for some readings, in addition to measuringbidirectional currents (charging/discharging) and volt-ages that can dip below ground.

Averaged values are also calculated for VBUS andVSENSE. A rolling average of the most recent eight val-ues is present in the VBUSn_AVG (Register 6-7) andVSENSEn_AVG (Register 6-6) registers. These regis-ters require eight conversion cycles after POR beforethey represent an accurate value, they are updatedafter every conversion cycle. The readable registersare updated with REFRESH, REFRESH_V orREFRESH_G commands like all the other readableresults registers.


PAC1934

4.9 Power and Energy

The Full-Scale Range for Power depends on the exter-nal sense resistor used, as shown in Equation 4-5.

EQUATION 4-5: POWER FSR CALCULATION

The device implements Power measurements by mul-tiplying VBUS and the VSENSE to give a result VPOWER.VPOWER values are used to calculate ProportionalPower as shown in Equation 4-6. The ProportionalPower is the fractional portion of Power FSR mea-sured in one sample. Bipolar mode is where VBUS isbipolar mode, VBUS is bidirectional mode, or bothVBUS and VSENSE are bipolar/bidirectional.

EQUATION 4-6: PROPORTIONAL POWER CALCULATION

To calculate the actual power from the ProportionalPower, multiply by the Power FSR as shown inEquation 4-7. This Actual Power number is the powermeasured in one sample.

EQUATION 4-7: POWER CALCULATION

These VPOWER results are digitally accumulated onchip, and stored in the VACCUM registers.

The energy calculation equations 4-8 and 4-9 use adifferent denominator term depending on unipolar orbipolar mode. Bipolar mode for energy applies whenbipolar/bidirectional mode is used for VBUS and/orVSENSE. Equation 4-8 shows how to realize this usingthe Accumulator results, Accumulator count and theaccumulation period, T. In this equation, T must beknown from a system clock time stamp or other accu-rate indicator of the total accumulation period.

EQUATION 4-8: ENERGY CALCULATION

EQUATION 4-9: ENERGY CALCULATION

Equation 4-9 shows how to calculate energy using theaccumulated power and the sampling rate, fs.

PowerFSR 100 mV RSENSE 32V=

Where:

RSENSE = External RSENSE resistor value

100 mV = Full-Scale VSENSE voltage input

32V = Full-Scale VBUS voltage input

3.2V2

RSENSE=

PPROPVpower

Denominator-----------------------------------=

Where:

Denominator ==

228 (unipolar mode)227 (bipolar mode)

Pactual PowerFSR PPROP=

EnergyV accum

Denominator----------------------------------- PwrFSR T

AccCount--------------------------=

Where:

Denominator = 228 (unipolar mode)

= 227 (bipolar mode)

EnergyV accum

Denominator----------------------------------- PwrFSR

fs--------------------------=

Where:

Denominator = 228 (unipolar mode)

= 227 (bipolar mode)


PAC1934

4.9.1 ADDITIONAL ACCUMULATOR INFORMATION

The math for the Power calculation and accumulationinside the chip is always done in two's complementmath, no matter what the user sets the output registersto show. VBUS and VSENSE are 17-bit two's comple-ment (signed) numbers internally. VPOWER is the prod-uct of VSENSE multiplied by the 14 MSBs of VBUS, andthis is a 31 bit two's complement result (signed) inter-nally. In some cases this results in a Power result thatis not identical to the product of the VBUS results regis-ter multiplied by the VSENSE register. However, thePower result from the Power results register is moreaccurate than the product of the VBUS register multi-plied by the VSENSE register in these cases, asexplained below.

If VSENSE and VBUS are both programmed to beunsigned (unipolar) in register NEG_PWR (Address1Dh), 16b without sign are exported to VBUS andVSENSE results registers.

If VBUS is programmed to be signed (bipolar) inRegister 6-11 NEG_PWR (Address 1Dh), the corre-sponding data is truncated to 16-bit two's complement(signed) for the readable results register.

If VSENSE is programmed to be signed (bipolar) in reg-ister NEG_PWR (Address 1Dh), the correspondingresults register value is truncated to 16-bit two's com-plement (signed), but the power calculation uses 17-bittwo's complement (signed). Therefore, a mismatch ispossible between an externally calculated power value(VBUS times VSENSE) and the actual power value calcu-lated internally to the chip. The internally calculated(and accumulated) value is more accurate than theexternally calculated value in every case.

The continuous power integration periods (also called theenergy accumulation period) can range from ~1ms tomany hours, depending on the number of samples persecond selected via SMBus. The number of samples islimited by the size of the Accumulator Count Register to16,777,216 (224). This count corresponds to about 273minutes at 1024 samples/second, or 582 hours at eightsamples/second. This Accumulator Count can overflow,and it will not reset when it overflows.

When the accumulation registers reach their maximumvalue, this is called accumulator overflow. The accumu-lator outputs remain at their maximum value; they donot roll over. The user can calculate the worst-casetime to roll over and read them at or before that time oruse the built in ALERT functions to detect rollover andread them at that time.

Worst-case accumulator overflow time can be calcu-lated assuming that every measurement that is accu-mulated is a full-scale number. Since the powernumbers are 28 bits, and the accumulator is 48 bits, 220

samples can be accumulated before overflow if theyare all full-scale values. For most applications, they willnot all be full-scale numbers; this is especially true if

VBUS is not 32V. If VBUS is a lower number, the maxi-mum number of full-scale samples that can be accumu-lated is scaled by 32V/VBUS. This limitation can limit theaccumulation period before overflow to 17 minutes at1024 samples/second, or 36 hours at eight sam-ples/second, if most values are near full-scale. TheAccumulator Count limit described above will still limitthe total number of samples to 224.


PAC1934

5.0 SMBUS AND I2C COMMUNICATIONS PROTOCOL

The PAC1934 device communicates over a two-wirebus with a controller using SMBus or I2C serial commu-nication protocol. A detailed timing diagram is shown inFigure 1-1.

Stretching of the SMCLK signal is supported; however,the PAC1934 will not stretch the clock signal.

5.1 I2C/SMBus Addressing and Control Bits

5.1.1 SMBUS ADDRESS AND RD / WR BIT

The SMBus Address Byte consists of the 7-bit slaveaddress followed by a 1-bit RD / WR indicator. If thisRD / WR bit is a logic ‘0’, the SMBus master is writingdata to the slave device. If this RD / WR bit is a logic‘1’, the SMBus master is reading data from the slavedevice.

The PAC1934 I2C/SMBus address is determined by asingle pull-down resistor connected between groundand the ADDRSEL pin as shown in Table 5-1. The chiptranslates the resistor value into an address onpower-up, and the value is latched until anotherpower-up event takes place. The address cannot bechanged on the fly.

5.1.2 SMBUS START BIT

The SMBus Start bit is defined as a transition of theSMBus data line from a logic ‘1’ state to a logic ‘0’ statewhile the SMBus Clock line is in a logic ‘1’ state.

5.1.3 SMBUS ACK AND NACK BITS

The SMBus slave will ACK (acknowledge) all databytes that it receives. This is done by the slave devicepulling the SMBus data line low after the eighth bit ofeach byte that is transmitted.

5.1.4 SMBUS STOP BIT

The SMBus Stop bit is defined as a transition of theSMBus data line from a logic ‘0’ state to a logic ‘1’ statewhile the SMBus clock line is in a logic ‘1’ state. Whenthe PAC1934 detects an SMBus Stop bit, and it hasbeen communicating with the SMBus protocol, it willreset its slave interface and prepare to receive furthercommunications.

5.1.5 SMBUS DATA BYTES

All SMBus data bytes are sent most significant bit firstand composed of 8 bits of information.

TABLE 5-1: ADDRESS SELECT RESISTOR

RESISTOR (1%) SMBUS ADDRESS

0 (Tie to GND) 0010_000(r/w)

499 0010_001(r/w)

806 0010_010(r/w)

1,270 0010_011(r/w)

2,050 0010_100(r/w)

3,240 0010_101(r/w)

5,230 0010_110(r/w)

8,450 0010_111(r/w)

13,300 0011_000(r/w)

21,500 0011_001(r/w)

34,000 0011_010(r/w)

54,900 0011_011(r/w)

88,700 0011_100(r/w)

140,000 0011_101(r/w)

226,000 0011_110(r/w)

Tie to VDD 0011_111(r/w)


PAC1934

5.2 SMBus Time-Out

The PAC1934 can support the SMBus Time-Out func-tionality. This functionality is disabled by default, andcan be enabled by writing to the TIMEOUT bit (seeRegister 6-10: CHANNEL_DIS and SMBus (Address1Ch).

If Time-Out is enabled and the clock is held at logic ‘0’for tTIMEOUT = 25-43 ms, the device will time-out andreset the SMBus interface. Communication is restoredwith a start condition.

5.3 SMBus and I2C Compatibility

The PAC1934 is compatible with SMBus 3.0 1 MHzclass and I2C Fast-mode Plus. The major differencesbetween SMBus and I2C devices are highlighted here.For more information, refer to the SMBus 3.0 and I2Cspecifications.

1. If Time-Out function is enabled, the minimumfrequency for SMBus communications is10 kHz. If Time-Out function is disabled (defaultcondition), then there is no minimum frequencyfor SMBus communications.

2. If SMBus Time-Out is enabled in Register 6-10:CHANNEL_DIS and SMBus (Address 1Ch),theSMBus slave protocol will reset if the clock isheld at a logic ‘0’ for tTIMEOUT. I

2C does not havea time-out, this is the default condition.

3. I2C devices do not support the Alert ResponseAddress functionality (which is optional forSMBus).The PAC1934 does not support theAlert Response Address functionality; instead,the ALERT is a GPIO pin that may be monitoredby the master or Embedded Controller.

4. I2C devices support Block Read and Block Writedifferently. I2C protocol allows for unlimited num-ber of bytes to be sent in either direction. TheSMBus protocol for Block Read and Block Writerequires that an additional data byte indicatingnumber of bytes to read/write is transmitted.PAC1934 devices support the I2C protocol forBlock Read by default (no byte count informa-tion is sent). If the Byte Count bit is set (seeRegister 6-10: CHANNEL_DIS and SMBus(Address 1Ch), it will be sent as the first databyte in response to the Block Read command,per SMBus protocol.

5.4 I2C/SMBus Protocols

The PAC1934 supports Write Byte, Read Byte, BlockRead, Send Byte and Receive Byte as valid protocols.

It will not respond to the Alert Response Address pro-tocol. It will respond to the I2C General Call Address.

All of the protocol charts listed below use the conven-tion in Table 5-2.

5.5 Auto-Incrementing Pointer

The PAC1934 has an auto-incrementing address pointer.The pointer has two loops for auto-incrementing, a READloop and a WRITE loop.

The READ loop includes all of the readable registers —all of the configuration and control registers, the resultsregisters, and the Product ID, Manufacturer ID andRevision ID registers.

The WRITE loop includes only the writable control andconfiguration registers.

Neither loop includes the REFRESH commands.

The READ loop will skip inactive channels, if somechannels have been disabled. This automatic channelskipping feature can be disabled by setting the NOSKIP bit in Register 6-10: CHANNEL_DIS and SMBus(Address 1Ch).

If the user elects to read disabled channels, they willreturn FFh and the register address will by NACKed.

See Figure 5-1 below for a graphic representation.

TABLE 5-2: PROTOCOL FORMAT

Data Sent to Device Data Sent to the Master

# of bits sent # of bits sent


PAC1934

FIGURE 5-1: READ and WRITE Auto Incrementing Loops.

Figure 5-1 shows how the auto-incrementing READ loop works with SKIP option on and off, for reading. It also showshow the WRITE loop works with the REFRESH, REFRESH_V, and REFRESH_G commands.

App Read Loop App Write LoopDon’t care if Channels

ON or OFF

REFRESH

CTRL

ACC_COUNT

VPOWER1_ACC

VPOWER2_ACC

VPOWER3_ACC

VPOWER4_ACC

VBUS1

VBUS2

VBUS3

VBUS4

VSENSE1

VSENSE2

VSENSE3

VSENSE4

VBUS1_AVG

VBUS2_AVG

VBUS3_AVG

VBUS4_AVG

VSENSE1_AVG

VSENSE2_AVG

VSENSE3_AVG

VSENSE4_AVG

VPOWER1

VPOWER2

VPOWER3

VPOWER4

CHANNEL_DIS

NEG_PWR

REFRESH_G

REFRESH_V

SLOW

CTRL_ACT

CHANNEL_DIS_ACT

NEG_PWR_ACT

CTRL_LAT

CHANNEL_DIS_LAT

NEG_PWR_LAT

REFRESH

CTRL

ACC_COUNT

VPOWER1_ACC

VPOWER2_ACC

VPOWER3_ACC

VPOWER4_ACC

VBUS1

VBUS2

VBUS3

VBUS4

VSENSE1

VSENSE2

VSENSE3

VSENSE4

VBUS1_AVG

VBUS2_AVG

VBUS3_AVG

VBUS4_AVG

VSENSE1_AVG

VSENSE2_AVG

VSENSE3_AVG

VSENSE4_AVG

VPOWER1

VPOWER2

VPOWER3

VPOWER4

CHANNEL_DIS

NEG_PWR

REFRESH_G

REFRESH_V

SLOW

CTRL_ACT

CHANNEL_DIS_ACT

NEG_PWR_ACT

CTRL_LAT

CHANNEL_DIS_LAT

NEG_PWR_LAT

PID

MID

REV

PID

MID

REV

Channels ON or (Channels OFF and

Skip OFF)

REFRESH

CTRL

ACC_COUNT

VPOWER1_ACC

VPOWER2_ACC

VPOWER3_ACC

VPOWER4_ACC

VBUS1

VBUS2

VBUS3

VBUS4

VSENSE1

VSENSE2

VSENSE3

VSENSE4

VBUS1_AVG

VBUS2_AVG

VBUS3_AVG

VBUS4_AVG

VSENSE1_AVG

VSENSE2_AVG

VSENSE3_AVG

VSENSE4_AVG

VPOWER1

VPOWER2

VPOWER3

VPOWER4

CHANNEL_DIS

NEG_PWR

REFRESH_G

REFRESH_V

SLOW

CTRL_ACT

CHANNEL_DIS_ACT

NEG_PWR_ACT

CTRL_LAT

CHANNEL_DIS_LAT

NEG_PWR_LAT

PID

MID

REV

Channels 1 & 4 OFF and Skip ON

Channels OFF andSkip ON

REFRESH

CTRL

ACC_COUNT

VPOWER1_ACC

VPOWER2_ACC

VPOWER3_ACC

VPOWER4_ACC

VBUS1

VBUS2

VBUS3

VBUS4

VSENSE1

VSENSE2

VSENSE3

VSENSE4

VBUS1_AVG

VBUS2_AVG

VBUS3_AVG

VBUS4_AVG

VSENSE1_AVG

VSENSE2_AVG

VSENSE3_AVG

VSENSE4_AVG

VPOWER1

VPOWER2

VPOWER3

VPOWER4

CHANNEL_DIS

NEG_PWR

REFRESH_G

REFRESH_V

SLOW

CTRL_ACT

CHANNEL_DIS_ACT

NEG_PWR_ACT

CTRL_LAT

CHANNEL_DIS_LAT

NEG_PWR_LAT

PID

MID

REV

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0xFD

0xFE

0xFF

W

R/W

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R/W

R/W

W

W

R/W

R

R

R

R

R

R

R

R

R

1 byte

1 byte

3 bytes

6 bytes

6 bytes

6 bytes

6 bytes

2 bytes

2 bytes

2 bytes

2 bytes

2 bytes

2 bytes

2 bytes

2 bytes

2 bytes

2 bytes

2 bytes

2 bytes

2 bytes

2 bytes

2 bytes

2 bytes

4 bytes

4 bytes

4 bytes

4 bytes

1 byte

1 byte

1 byte

1 byte

1 byte

1 byte

1 byte

1 byte

1 byte

1 byte

1 byte

1 byte

1 byte

1 byte


PAC1934

5.6 I2C/SMBus Commands

5.6.1 REFRESH AND REFRESH_V

REFRESH and REFRESH_V commands are sentusing the Send byte command, the Slave Address andthe desired command (00h for REFRESH or 1Fh forREFRESH_V.See Table 5-3.

5.6.2 GENERAL CALL ADDRESS RESPONSE

When the master sends the General Call address, thePAC1934 will be able to execute the REFRESH com-mand by means of a second version of the REFRESHcommand called REFRESH_G (see REFRESH_GCOMMAND (Address 1Eh) Register 6-12.).

Just as the REFRESH command is sent using a SendByte command with the slave address, and theREFRESH command (00h), the REFRESH_G com-mand is sent using Send Byte with the General Calladdress (0000 000) and the REFRESH_G command(1Eh).

Table 5-4 shows the response to the General Call com-mand for REFRESH_G.

5.6.3 WRITE BYTE

The Write Byte is used to write one byte of data to theregisters, as shown in Table 5-5.

5.6.4 READ BYTE

The Read Byte protocol is used to read one byte of datafrom the registers, as shown in Table 5-6.

If an invalid register address is specified, the slave willACK its address but NACK the register address.

The master will NACK (not acknowledge) the datareceived from the slave by holding the SMBus data linehigh after the eighth data bit has been sent.

TABLE 5-3: REFRESH AND REFRESH_V COMMANDS

START Slave Address WR ACKREFRESH orREFRESH_V

CommandACK STOP

1 0 YYYY_YYY 0 0 00h or 1Fh 0 0 1

TABLE 5-4: GENERAL CALL RESPONSE

STARTGeneral Call

AddressWR ACK

REFRESH_GCommand

ACK STOP

1 0 0000_000 0 0 1Eh 0 0 1

TABLE 5-5: WRITE BYTE PROTOCOL

STARTSlave

AddressWR ACK

RegisterAddress

ACKRegister

DataACK STOP

1 0 YYYY_YYY 0 0 XXh 0 XXh 0 0 1

TABLE 5-6: READ BYTE PROTOCOL

STARTSlave

AddressWR ACK

RegisterAddress

ACK START Slave Address RD ACK Register Data NACK STOP

1 0 YYYY_YYY 0 0 XXh 0 1 0 YYYY_YYY 1 0 XXh 1 0 1


PAC1934

5.6.5 SEND BYTE

The Send Byte protocol is used to set the internaladdress register pointer to the correct address location.No data is transferred during the Send Byte protocol,as shown in Table 5-7.

5.6.6 RECEIVE BYTE

The Receive Byte protocol is used to read data from aregister when the internal register address pointer isknown to be at the right location (e.g., set via SendByte). This is shown in Table 5-8.

When an ACK is received after the REGISTER DATA,then the address pointer automatically increments.

When a NACK is received after the REGISTER DATA,then the address pointer stays at the same position.

If the master wishes to continue clocking and read thenext register, the master will ACK after the registerdata, instead of sending NACK followed by STOP.

If some channels are deactivated, their data registerswill be skipped by the auto-incrementing pointer. Alter-natively, you may set bit 0 in Register 6-10 CHAN-NEL_DIS and SMBus (Address 1Ch) and the pointerwill not skip the addresses associated with the inactivechannels. The measurement data for these inactivechannels will read FFh.

5.6.7 BLOCK READ – I2C VERSION

Block Read is used to read multiple data bytes from aregister that contains more than one byte of data, orfrom a group of contiguous registers, as shown inTable 5-9. The PAC1934 supports I2C Block Read bydefault, but the SMBus format can also be supported(see Table 5-10).

If an invalid register address is specified, the slave willACK its address but NACK the register address.

The master will NACK (not acknowledge) the datareceived from the slave by holding the SMBus data linehigh after the 8th data bit has been sent.

TABLE 5-7: SEND BYTE PROTOCOL

START Slave Address WR ACK Register Address ACK STOP

1 0 YYYY_YYY 0 0 XXh 0 0 1

TABLE 5-8: RECEIVE BYTE PROTOCOL

START Slave Address RD ACK Register Data NACK STOP

1 0 YYYY_YYY 1 0 XXh 1 0 1

TABLE 5-9: BLOCK READ PROTOCOL I2C VERSION (DEFAULT)

START Slave Address WR ACKRegisterAddress

ACK START Slave Address RD ACKRegister

Data

1 0 YYYY_YYY 0 0 XXh 0 1 0 YYYY_YYY 1 0 XXh

ACK Register Data ACKRegister

DataACK

Register Data

ACKRegister

DataNACK STOP

0 XXh 0 XXh 0 XXh 0 XXh 1 0 1


PAC1934

5.6.8 BLOCK READ – SMBUS VERSION

PAC1934 can also support the SMBus version of BlockRead. If the Byte Count bit is set, Block Read will resultin the device sending the Byte Count data before thefirst data byte. This protocol is shown in Table 5-10.Also see Section 4.3 “Conversion Cycle Controls”above and Register 6-10 CHANNEL_DIS and SMBus(Address 1Ch).

TABLE 5-10: BLOCK READ PROTOCOL SMBUS VERSION (MUST SET BYTE COUNT BIT)

START Slave Address WR ACKRegister Address

ACK START Slave Address RD ACK Byte Count

1 0 YYYY_YYY 0 0 XXh 0 1 0 YYYY_YYY 1 0 XXh = N

ACK Register Data ACKRegister

DataACK

Register Data

ACKRegister

DataNACK STOP

0 XXh 0 XXh 0 XXh 0 XXh 1 0 1


PAC1934

6.0 REGISTERS IN HEXADECIMAL ORDER

The registers shown in Table 6-1 are accessiblethrough the SMBus. In the individual register tables thatfollow, an entry of ‘—’ indicates that the bit is not usedand will always read ‘0’.

Data represented by the data registers are guaranteedto be synchronized and stable 1 ms after any of theREFRESH commands are sent. Immediately after theREFRESH commands are sent, the data bytes will bechanging dynamically until 1 ms has elapsed. Whennew data is written to a control register, and the masterreads it back, this new data will be read back even if noREFRESH command has been sent to cause the newdata to take effect.

Note: The letter N or n is used to represent1,2,3,4 in the register and bit namesbelow, in sections that describe registersthat are grouped for all four channels.

TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER

Register Number

Description Type BytesPOR Value

Register 6-1REFRESH Command (Address 00h)

Send Byte for REFRESH command SEND 0 00h

Register 6-2CTRL REGISTER (Address 01h)

Configuration controls and status R/W 1 00h

Register 6-3ACC_COUNT Register (Address 02h)

Accumulator count for all channels Block Read

3 000000h

Register 6-4VPOWERN Accumulator Registers: VPOW-

ER1_ACC(03h), VPOWER2_ACC (04h), VPOWER3_ACC (05h), VPOWER4_ACC

(06h)

Accumulator output for channel 1 Block Read

6 Note 1


6 Note 1


6 Note 1


6 Note 1

Register 6-5VBUSN Result Registers VBUS1 (07h),

VBUS2 (08h), VBUS3 (09h),VBUS4 (0Ah )

VBUS measurement for channel 1 Block Read

2 0000h


2 0000h


2 0000h


2 0000h

Note 1: The VPOWERN Accumulator Registers, 03h -06h, have a POR value that is all zeros: 6 bytes 000000000000h.


PAC1934

Register 6-6VSENSEn Result Registers: VSENSE1

(0Bh), VSENSE2 (0Ch), VSENSE3 (0Dh), VSENSE4 (0Eh)

VSENSE measurement for channel 1 Block Read

2 0000h


2 0000h


2 0000h


2 0000h

Register 6-7VBUSN_AVG Result Registers

VBUS1_AVG (0Fh), VBUS2_AVG (10h), VBUS3_AVG (11h), VBUS4_AVG (12h)

Rolling average of 8 most recent VBUS1 measurements

Block Read

2 0000h


Block Read

2 0000h


Block Read

2 0000h


Block Read

2 0000h

Register 6-8VSENSEn AVG Result Register

VSENSE1_AVG (13h), VSENSE2_AVG (14h), VSENSE3_AVG(15h),

VSENSE4_AVG (16h)

Rolling average of 8 most recent VSENSE1 measurements

Block Read

2 0000h


Block Read

2 0000h


Block Read

2 0000h


Block Read

2 0000h

Register 6-9VPOWERN Result Register: VPOWER1

(17h), VPOWER2 (18h), VPOWER3 (19h), VPOWER4 (1Ah)

VSENSE x VBUS for Channel 1 Block Read

4 00000000h


4 00000000h


4 00000000h


4 00000000h

Register 6-10CHANNEL_DIS and SMBus (Address 1Ch)

Disable selected channels, activate SMBus functionality,

pointer increment

R/W 1 00h

Register 6-11NEG_PWR (Address 1Dh)

Configuration control for enabling bidirectional current and

bipolar voltage measurements

R/W 1 00h

Register 6-12REFRESH_G COMMAND (Address 1Eh)

REFRESH response to General Call Address

SEND 0 N/A

Register 6-13REFRESH_V COMMAND (Address 1Fh)

Refreshes VBUS and VSENSE data only,

no accumulator reset

SEND 0 N/A

Register 6-14SLOW (Address 20h)

Status and control for SLOW pin functions

R/W 1 15h

Register 6-15CTRL_ACT Register (Address 21h)

Currently active value of 01h (Control)

R 1 00h

TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED)

Register Number




PAC1934

Register 6-16Channel DIS_ACT (Address 22h)

Currently active value of 1Ch (CHANNEL_DIS and SMBus)

R 1 00h

Register 6-17NEG_PWR_ACT (Address 23h)

Currently active value of1Dh(NEG_PWR)

R 1 00h

Register 6-18CTRL_LAT Register (Address 24h)

Latched image of 21h (CTRL_ACT) R 1 00h

Register 6-19Channel DIS_LAT (Address 25h)

Latched image of 22h (Channel DIS_ACT)

R 1 00h

Register 6-20NEG_PWR _LAT (Address 26h)

Latched image of23h (NEG_PWR_ACT)

R 1 00h

Register 6-21Product ID Register (Address FDh)

Stores the Product ID R 1 5Bh

Register 6-22Manufacturer ID Register (Address FEh)

Stores the Manufacturer ID R 1 5Dh

Register 6-23Revision ID Register (Address FFh)

Stores the revision R 1 03h

TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED)

Register Number




PAC1934

6.1 Detailed Register Information

REGISTER 6-1: REFRESH COMMAND (ADDRESS 00H)

SEND SEND SEND SEND SEND SEND SEND SEND

No Data in this command, Send Byte only

bit 7 bit 0

Legend:

R = Readable bit W = Writeable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7:0 This command is a SEND Byte, does not contain any data. When it is sent to the device, the REFRESHcommand is executed. The accumulator data, accumulator count, VBUS, and VSENSE measurementsare all refreshed and the accumulators are reset. The master can read the accumulator data and accu-mulator count anytime 1ms after the REFRESH command is sent, and anytime after than up until thenext REFRESH command is sent. (The master can read VBUS and VSENSE data in the same timeperiod. The accumulator results, accumulator count, VBUS and VSENSE data can be refreshed with theREFRESH_V command without resetting the accumulators, see Register 5-7).

REGISTER 6-2: CTRL REGISTER (ADDRESS 01H)

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R-0

Sample_Rate<1:0> SLEEP SING ALERT_PIN ALERT_CC OVF ALERT OVF

bit 7 bit 0

Legend:



bit 7:1 Write to these bits to change settings from default value

bit 7:6 Sample_Rate<1:0> - determines sample rate in Normal mode (that is, if SLOW pin is not asserted)00b = 1024 samples/s01b = 256 samples/s10b = 64 samples/s11b = 8 samples/s

bit 5 SLEEP: setting this bit to 1, followed by the REFRESH or REFRESH_V command, puts the device inSLEEP mode. All programmed, readable, and measured digital data is stable in this mode. Clear-ing the SLEEP bit and sending a REFRESH or REFRESH_V command causes the devicebecome active and start converting in the mode specified by the CONTROL registers (unless theSLOW pin is asserted, in which case it will start converting at an 8 Hz rate). The SLEEP bit hashigher priority than the SING bit or the SLOW pin, if the SLEEP bit is set the device goes intoSLEEP mode not matter how the SING bit or the SLOW pin are set.

0 = Active mode1 = SLEEP mode, no data conversion

bit 4 SING: setting this bit to 1 puts the device in Single-shot mode. After writing this bit and sending aREFRESH command, the device resets the accumulators and performs one conversion cycle forany and all active channels, then returns to sleep mode. Another REFRESH command, withoutchanging this bit, will perform another single-shot command. When the bit is cleared, sending aREFRESH command resets the accumulators and causes the device to start converting in thesequential scan mode for active channels. A REFRESH_V command may be used instead ofREFRESH to move in and out of Single Shot mode without resetting the accumulators and accu-mulator count.

0 = Sequential scan mode1 = Single-shot mode


PAC1934

bit 3 ALERT_PIN: Setting this bit to 1 causes the SLOW pin to function as an ALERT pin (active low output pin). If this bit is set to 1, the ALERT pin can be triggered by conversion complete if bit 2 is set.If this bit is set to 1, and the Overflow ALERT enable bit is set to 1, the ALERT pin will be triggered by accumulator or accumulator count overflow. see bit 1 and bit 0 descriptions directly below)Note that bit 3 only determines the functionality of this pin, SLOW or ALERT, it does not influence the ALERT functionality. If there is a pull-up resistor connected to the pin for ALERT functionality, the device will initially power-up in SLOW mode. Once bit 3 is set to enable ALERT functionality, the con-version rate will change to either the default or programmed value.0 = Disable the ALERT pin function1 = Enable the ALERT pin function

bit 2 ALERT_CC: Setting this bit to 1 causes the ALERT pin to be asserted for 5 μS at the end of each con-version cycle.0 = No ALERT on Conversion Cycle Complete1 = ALERT function asserted for 5uS on each completion of the conversion cycle

Note: If this bit and the OVF ALERT bit are set, OVF ALERT dominates. EOC alerts will not beseen on the ALERT pin if OVF ALERT =1.

bit 1 OVF ALERT: Overflow ALERT enable. If this bit is set and any of the accumulators or the accumulator counter overflow, the ALERT function will be triggered. This will be reflected in bit 0 of this register, and if bit 3 is set to a 1, the ALERT pin will be triggered (sent low). The ALERT function is cleared by REFRESH or REFRESH_G.0 = no ALERT if accumulator or accumulator counter overflow has occurred.1 = ALERT pin triggered if accumulator or accumulator counter has overflowed

Note: If this bit and the ALERT_CC bit are set, OVF ALERT dominates. EOC alerts will not beseen on the ALERT pin if OVF ALERT =1.

bit 0 OVF: Overflow indication status bit, this bit will be set to 1 if any of the accumulators or the accumula-tor counter overflows.This bit is by cleared REFRESH or REFRESH_G. These commands also clear the ALERT function.0 = no accumulator or accumulator counter overflow has occurred.1 = accumulator or accumulator counter has overflowed

REGISTER 6-2: CTRL REGISTER (ADDRESS 01H) (CONTINUED)

REGISTER 6-3: ACC_COUNT REGISTER (ADDRESS 02h)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

ACC_COUNT<23:16>

bit 23 bit 16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

ACC_COUNT<15:8>

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

ACC_COUNT<7:0>

bit 7 bit0 bit0

Legend:



bit 23:0 ACC_COUNT[23:0]: This register contains the count for each time a power result has been summed in the accumulator


PAC1934

REGISTER 6-4: VPOWERN ACCUMULATOR REGISTERS: VPOWER1_ACC(03h), VPOWER2_ACC (04h), VPOWER3_ACC (05h), VPOWER4_ACC (06h)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VPOWERn<47:40>

bit 47 bit 40

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VPOWERn<39:32>

bit 39 bit 32

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VPOWERn<31:24>

bit 31 bit 24

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VPOWERn<23:16>

bit 23 bit 16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VPOWERn<15:8>

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VPOWERn<7:0>

bit 7 bit 0

Legend:



bit 47:0 VPOWERn_ACC<47:0>: These registers contain the accumulated sum of VPOWER samples, where n = 1 to 4, depending on device. These are 48 bit unsigned numbers unless either VBUS or VSENSE are configured to have a bipolar range. In that case they will be 48-bit two's complement (signed) numbers.Note that power is always calculated and accumulated using signed numbers for VBUS and VSENSE, but if both VBUS and VSENSE are in the default unipolar mode, power is reported as an unsigned num-ber. This can lead to very small discrepancies between a manual comparison of the product of VBUS and VSENSE and the results that the chip calculates and accumulates for VPOWER. The digital math in the chip uses more bits than the reported results for VBUS and VSENSE, so the results registers for VPOWER and Accumulated Power will in some cases have a more accurate number than calculations using the results registers for VSENSE and VBUS will provide.

REGISTER 6-5: VBUSN RESULT REGISTERS VBUS1 (07h), VBUS2 (08h), VBUS3 (09h),VBUS4 (0Ah)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VBUSn<15:8>

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VBUSn<7:0>

bit 7 bit 0


PAC1934

Legend:



bit 15:0 VBUSn<15:0>: These registers contain the most recent digitized value of a VBUS sample, where n = 1 to 4, depending on device. These are 16 bit unsigned numbers unless VBUS is configured to have a bipolar range. In that case they will be 16-bit two's complement (signed) numbers.

REGISTER 6-5: VBUSN RESULT REGISTERS VBUS1 (07h), VBUS2 (08h), VBUS3 (09h),VBUS4 (0Ah) (CONTINUED)

REGISTER 6-6: VSENSEn RESULT REGISTERS: VSENSE1 (0Bh), VSENSE2 (0Ch), VSENSE3 (0Dh), VSENSE4 (0Eh)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VSENSEn<15:8>

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VSENSEn<7:0>

bit 7 bit 0

Legend:



bit 15:0 VSENSEn<15:0>: These registers contain the most recent digitized value of VSENSE samples, where n = 1 to 4, depending on device.These are 16 bit unsigned numbers unless VSENSE is configured to have a bipolar range. In that case they will be 16-bit two's complement (signed) numbers.

REGISTER 6-7: VBUSN_AVG RESULT REGISTERS VBUS1_AVG (0FH), VBUS2_AVG (10H), VBUS3_AVG (11H), VBUS4_AVG (12H)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VBUSn_AVG<15:8>

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VBUSn_AVG<7:0>

bit 7 bit 0

Legend:



bit 15:0 VBUSn_AVG<15:0>: These registers contain a rolling average of the 8 most recent VBUS measure-ments. They have the same format as the values in the VBUS registers.


PAC1934

REGISTER 6-8: VSENSEn AVG RESULT REGISTER VSENSE1_AVG (13H), VSENSE2_AVG (14H), VSENSE3_AVG(15H), VSENSE4_AVG (16H)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VSENSEn_AVG<15:8>

bit 15 bit 8

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VSENSEn_AVG<7:0>

bit 7 bit 0

Legend:



bit 15:0 VSENSEn_AVG<15:0>: These registers contain a rolling average of the 8 most recent VSENSE results

They have the same format as the values in the VSENSE registers,.

REGISTER 6-9: VPOWERN RESULT REGISTER: VPOWER1 (17H), VPOWER2 (18H), VPOWER3 (19H), VPOWER4 (1AH)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VPOWERn<27:20>

bit 31 bit 24

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VPOWERn<19:12>

bit 23 bit 16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VPOWERn<11:4>

bit 15 bit 8

R-0 R-0 R-0 R-0 U U U U

VPOWERn<3:0> — — — —

bit 7 bit 0

Legend:



bit 31:4 VPOWERn<27:0>: These registers contain the product of VBUS (14 MSBs) and VSENSE which rep-resents Proportional Power for each channel.These are 28 bit unsigned numbers unless either VBUS or VSENSE are configured to have a bipolar range. In that case they will be 28-bit two's complement (signed) numbers.These are the numbers that are accumulated in the accumulators. Note that power is always calculated using signed numbers for VBUS and VSENSE, but if both VBUS and VSENSE are in the default unipolar mode, power is reported as an unsigned number. This can lead to very small discrepancies between a manual comparison of the product of VBUS and VSENSE and the results that the chip calculates for VPOWER.The digital math in the chip uses more bits than the reported results for VBUS and VSENSE, so the results registers for VPOWER and Accumulated Power will in some cases have a more accurate number than calculations using the results registers for VSENSE and VBUS will provide.

bit 3:0 Not used at this time, always reads 0


PAC1934

REGISTER 6-10: CHANNEL_DIS AND SMBUS (ADDRESS 1CH)

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 U

CH1_OFF CH2_OFF CH3_OFF CH4_OFF TIMEOUT BYTE COUNT NO SKIP —

bit 7 bit 0

Legend:



bit 7:4 CHn_OFF<7:4> - Allows one or more channels to be inactive during the conversion cycle. These set-tings apply for normal continuous round-robin conversion cycles or Single-Shot mode, if Single-Shot mode is selected. Note that if a channel is set to inactive, the auto incrementing address pointer will skip addresses associated with that channel unless the Pointer Skipping bit 1 in this register is set.

Changes to bits 7:4 do not take effect until a REFRESH, REFRESH_V, or REFRESH_G command are sent.

Changes to bits 3:1 take place as soon as a new value is written, they are not gated by a REFRESH command like most other control bits.

bit 7 0 = CH1 ON. Channel 1 active during conversion cycle

1 = CH1 OFF. Channel 1 inactive during conversion cycle







bit 3 Timeout enable bit. The SMBus timeout is disabled by default, and is enabled by setting this bit.

0 = No SMBus timeout feature

1 = SMBus timeout feature is available.

bit 2 This bit causes Byte Count data to be included in the response to the SMBus Block Read command for each register read. This functionality is disabled by default, and Block Read corresponds to I2C Proto-col.

0 = No Byte Count in response to a Block Read command

1 = Data in response to a Block Read command includes the Byte Count data

bit 1 NO SKIP - This bit controls the auto-incrementing of the address pointer for channels that are inactive.

0 = The auto-incrementing pointer will skip over addresses used by/for channels that are inactive.

1 = The auto-incrementing pointer will not skip over addresses used by/for channels that are inactive. With this setting, these channels that are disabled will read 0xFF if read.

bit 0 Unimplemented bits always read 0


PAC1934

REGISTER 6-11: NEG_PWR (ADDRESS 1DH)

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

CH1_BIDI CH2_BIDI CH3_BIDI CH4 BIDI CH1_BIDV CH2_BIDV CH3_BIDV CH4_BIDV

bit 7 bit 0

Legend:



bit 7:4 These control bits allow the user to enable bidirectional current measurements for any channel, which will result in the VSENSE voltage measurement data being in 16-bit two's complement (signed) format. If the channel is enabled for negative current measurements, the full scale range for VSENSE is –100 mV to +100 mV.

If these bits are enabled for any channel, that channel’s power numbers are also capable of reporting bidirectional numbers in two’s complement format.

bit 3:0 These control bits allow the user to enable bidirectional/bipolar voltage measurements for any channel, which will result in the VBUS voltage measurement data being in 16 bit two’s complement format.

If the channel is enabled for negative voltage measurements, the full scale range for VBUS is +32V to –32V.Note that this range is the digital FSR, the VBUS input will not give accurate measurements if taken more than 200 mV below ground.

If these bits are enabled for any channel, that channel’s power numbers are also capable of reporting bidirectional numbers in two’s complement format.

bit 7 0 = Channel 1 VSENSE ADC converts 0 to +100 mV range with 16-bit straight binary output1 = Channel 1 VSENSE ADC converts –100 mV to +100 mV range with 16-bit two’s complement output

bit 6 0 = Channel 2 VSENSE ADC converts 0 to +100 mV range with 16 bit straight binary output1 = Channel 2 VSENSE ADC converts –100 mV to +100 mV range with 16 bit two’s complement output


bit 4 0 = Channel 4 VSENSE ADC converts 0 to +100 mV range with 16-bit straight binary output1 = Channel 4 VSENSE ADC converts –100 mV to +100 mV range with 16 bit two’s complement output

bit 3 0 = Channel 1 VBUS ADC converts 0 to +32V range with 16-bit straight binary output1 = Channel 1 VBUS ADC converts –32V to +32 range with 16-bit two’s complement output

bit 2 0 = Channel 2 VBUS ADC converts 0 to +32V range with 16-bit straight binary output1 = Channel 2 VBUS ADC converts –32V to +32V range with 16-bit two’s complement output


bit 0 0 = Channel 4 VBUS ADC converts 0 to +32V range with 16-bit straight binary output1 = Channel 4 VBUS ADC converts –32V to +32V range with 16-d1sw2fxbit two’s complement output


PAC1934

REGISTER 6-12: REFRESH_G COMMAND (ADDRESS 1EH)



bit 7 bit 0

Legend:



bit 7:0 This command is a SEND Byte, does not contain any data. It is exactly like the REFRESH commandbut is intended for use with the General Call command.

When it is sent to the device, the REFRESH command is executed and the readable accumulator data,readable accumulator count, VBUS, and VSENSE measurements are all refreshed and the internalaccumulators values or accumulator count are reset, exactly like the REFRESH command. Themaster can read the updated data 1 ms after the REFRESH_G command is sent, and anytimeafter than up until the next REFRESH, REFRESH_G, or REFRESH_V command is sent.

REGISTER 6-13: REFRESH_V COMMAND (ADDRESS 1FH)



bit 7 bit 0

Legend:



bit 7:0 This command is a SEND Byte, does not contain any data. When it is sent to the device, the REFRESH_V command is executed. It is similar to the REFRESH command except the accumulators and accumulator count are not reset. The readable accumulator data, readable accumulator count, VBUS, and VSENSE measurements are all refreshed without affecting the internal accumulators values or accumulator count. The master can read the updated data 1 ms after the REFRESH_V command is sent, and anytime after than up until the next REFRESH, REFRESH_G, or REFRESH_V command is sent.


PAC1934

REGISTER 6-14: SLOW (ADDRESS 20H)

R-0 R-0 R-0 RW-1 RW-0 RW-1 RW-0 RW-1

SLOW SLOW-LH SLOW_HL R_RISE R_V_RISE R_FALL R_V_FALL POR

bit 7 bit 0

Legend:



This register tracks the state of the SLOW pin, tracks transitions on the SLOW pin, and controls the type of limitedREFRESH command (if any) that occurs on a SLOW pin transitions. This allows software to monitor the state of theSLOW pin and its transitions over I2C even though the SLOW pin is asynchronous to the I2C pins and may have adifferent controller.

Note that if a REFRESH and REFRESH_V are both enabled for a certain SLOW pin transition, REFRESH will be exe-cuted (REFRESH wins over REFRESH_V).

On a transition of the SLOW pin, a limited REFRESH function is executed. These limited REFRESH and REFRESH_Vfunctions update all of the readable results registers. For the limited REFRESH function only, it also reset the accu-mulators and accumulator count. These are called limited REFRESH and limited REFRESH_V functions becausethere is no activation of any pending changes to the control registers.

If the SLOW pin is configured to act as an ALERT pin, all of these bits are always 0. The bits are not cleared whenread, see the details on each bit for clearing information.

SLOW Control and Status Bits

bit 7 =0bit 7 = 1

The SLOW pin is pulled low externallyThe SLOW pin is pulled high externally

bit 6 = 0

bit 6 = 1

The SLOW pin has not transitioned low to high since the last REFRESH commandThe SLOW pin has transitioned low to high since the last REFRESH commandThe bit is reset to 0 by a REFRESH or REFRESH_G command

bit 5 = 0

bit 5 = 1

The SLOW pin has not transitioned high to low since the last REFRESH commandThe SLOW pin has transitioned high to low since the last REFRESH commandThe bit is reset to 0 by a REFRESH or REFRESH_G command

bit 4 = 0 bit 4 = 1

Disables a limited REFRESH function to take place on the rising edge of the SLOW pin Enables a limited REFRESH function to take place on the rising edge of the SLOW pin The bit is not reset automatically, it must be written to be changed.

bit 3 = 0bit 3 = 1

Disables a limited REFRESH_V function to take place on the rising edge of the SLOW pinEnables a limited REFRESH_V function to take place on the rising edge of the SLOW pinThe bit is not reset automatically, it must be written to be changed.

bit 2 =0bit 2 = 1

Disables a limited REFRESH function to take place on the falling edge of the SLOW pinEnables a limited REFRESH function to take place on the falling edge of the SLOW pinThe bit is not reset automatically, it must be written to be changed.

bit 1 = 0bit 1 = 1

Disables a limited REFRESH_V function to take place on the falling edge of the SLOW pin Enables a limited REFRESH_V function to take place on the falling edge of the SLOW pin The bit is not reset automatically, it must be written to be changed.

POR Status BitThe POR bit is a POR flag, for the purpose of enabling the system designer can clear it after POR, and then monitor it to detect if the device was powered cycled or somehow reset since the POR. If the reset is detected in this manner, any non-default programming can be reprogrammed.

bit 0 = 0bit 0 = 1

this bit has been cleared over I2C since the last POR occurred.this bit has the POR default value of 1, and has not been cleared since the last reset occurredThis bit is only reset by POR


PAC1934

REGISTER 6-15: CTRL_ACT REGISTER (ADDRESS 21H)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0


bit 7 bit 0

Legend:



This register contains an image of the Control register, 01h. The bits in this register reflect the current active value ofthese settings, whereas the values in register 01h may have been programmed but not activated by one of theREFRESH commands. This register allows software to determine the actual active setting.

This register is valid when the Results registers are valid, 1 ms after a REFRESH/_V/_G command (in most cases).However, if you program a conversion rate change followed by REFRESH, the new conversion rate will not becomeeffective until the current conversion cycle is complete. This can cause a delay in come cases before the conversioncycle (and the CTRL_ACT register) are updated. This delay can be variable, depending on where we are in the con-version cycle when the REFRESH command is sent.

bit 7:6 Sample_Rate<1:0> - shows the value that is currently active since the most recent REFRESH functionwas received for programmed sample rate in Normal mode (that is, if SLOW pin is not asserted)

00b = 1024 samples/s01b = 256 samples/s10b = 64 samples/s11b = 8 samples/s

bit 5 SLEEP: This bit shows the value that is currently active since the most recent REFRESH function wasreceived for the SLEEP bit.

0 = Active mode1 = SLEEP mode, no data conversion

bit 4 SING: this bit shows the value that is currently active since the most recent REFRESH function wasreceived for the single shot select bit, SING.


bit 3 This bit shows the value that is currently active since the most recent REFRESH function was received for the ALERT_PIN bit.

0 = Disable the ALERT pin function1 = Enable the ALERT pin function

bit 2 This bit shows the value that is currently active since the most recent REFRESH function was received for the ALERT_CC bit.

0 = No ALERT on Conversion Cycle Complete

1 = ALERT function asserted for 5uS on each completion of the conversion cycle

bit 1 This bit shows the value that is currently active since the most recent REFRESH function was receivedfor the OVF ALERT bit.

0 = No ALERT if accumulator or accumulator counter overflow has occurred.1 = ALERT pin triggered if accumulator or accumulator counter has overflowed

bit 0 This bit shows the value that is currently active since the most recent REFRESH function was receivedfor the OVF bit.

0 = No accumulator or accumulator counter overflow has occurred.1 = Accumulator or accumulator counter has overflowed


PAC1934

REGISTER 6-16: CHANNEL DIS_ACT (ADDRESS 22H)

R-0 R-0 R-0 R-0 U U U U

CH1_OFF CH2_OFF CH3_OFF CH4_OFF — — — —

bit 7 bit 0

Legend:



This register contains an image of the Channel Disable bits in register 1Ch.The bits in this register reflect the valuethat was activated by the most recent REFRESH function, and is currently active. Whereas the values in register 1Chmay have been programmed but not activated by one of the REFRESH commands, register 22h allows software todetermine the actual active setting. This register is valid when the Results registers are valid, 1 ms after aREFRESH/_V/_G command.

bit <7:4> CHn_OFF<7:4> – Shows the value that is currently active for these bits









bit 3:0 Not used, always reads zero

REGISTER 6-17: NEG_PWR_ACT (ADDRESS 23H)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0


bit 7 bit 0

Legend:



This register contains an image of the NEG_PWR register, 1Dh.The bits in this register reflect the current active valueof these settings, whereas the values in register 1Dh may have been programmed but not activated by one of theREFRESH commands. This register allows software to determine the actual active setting. This register is valid whenthe Results registers are valid, 1 ms after a REFRESH/_V/_G command.

bit 7:0 These bits show the current active value of these bits








PAC1934



REGISTER 6-18: CTRL_LAT REGISTER (ADDRESS 24H)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0


bit 7 bit 0

Legend:



This register contains an image of the Register 6-15 CTRL_ACT Register (Address 21h). The bits in this register reflectthe value of these settings that was active before the most recent REFRESH command (including REFRESH_V and/orREFRESH_G). The values in register 01h may have been programmed but not activated by one of the REFRESHcommands, and the values in 21h are currently active. This register allows software to determine the actual active set-ting that was active prior to the most recent REFRESH command and therefore corresponds to the dataset that is heldin the readable registers. This register is valid when the Results registers are valid, 1 ms after a REFRESH/_V/_Gcommand.

bit 7:6 Sample_Rate<1:0> – shows the value of these settings that was latched prior to the most recentREFRESH command (including REFRESH_V and/or REFRESH_G)

00b = 1024 samples/s01b = 256 samples/s10b = 64 samples/s11b = 8 samples/s

bit 5 SLEEP: This bit shows the value of these settings that was latched prior to the most recent REFRESHcommand (including REFRESH_V and/or REFRESH_G).

0 = Active mode

1 = SLEEP mode, no data conversion

bit 4 SING: this bit shows the value of these settings that was latched prior to the most recent REFRESHcommand (including REFRESH_V and/or REFRESH_G).


bit 3 the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G).

0 = Disable the ALERT pin function1 = Enable the ALERT pin function

bit 2 This bit shows the value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G) for the ALERT_CC bit.

0 = No ALERT on Conversion Cycle Complete

1 = ALERT function asserted for 5uS on each completion of the conversion cycle.

bit 1 This bit shows the value of these settings that was latched prior to the most recent REFRESH command(including REFRESH_V and/or REFRESH_G) for the ALERT_CC bit.

0 = No ALERT if accumulator or accumulator counter overflow has occurred.

1 = ALERT pin triggered if accumulator or accumulator counter has overflowed.

bit 0 This bit shows the value of these settings that was latched prior to the most recent REFRESH command(including REFRESH_V and/or REFRESH_G) for the OVF bit.

0 = No accumulator or accumulator counter overflow has occurred.1 = accumulator or accumulator counter has overflowed

REGISTER 6-17: NEG_PWR_ACT (ADDRESS 23H) (CONTINUED)


PAC1934

REGISTER 6-19: CHANNEL DIS_LAT (ADDRESS 25H)

R-0 R-0 R-0 R-0 U U U U

CH1_OFF CH2_OFF CH3_OFF CH4_OFF — — — —

bit 7 bit 0

Legend:



This register contains an image of the Register 6-16 Channel DIS_ACT (Address 22h).The bits in this register reflectthe value of these settings that was active before the most recent REFRESH command (including REFRESH_V and/orREFRESH_G). The values in register 1Ch may have been programmed but not activated by one of the REFRESHcommands, and the values in 22h are currently active. This register allows software to determine the actual active set-ting that was active prior to the most recent REFRESH command and therefore corresponds to the dataset that is heldin the readable registers. This register is valid when the Results registers are valid, 1 ms after a REFRESH/_V/_Gcommand.

bit <7:4> The value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G)









bit 3:0 Not used, always read 0

REGISTER 6-20: NEG_PWR _LAT (ADDRESS 26H)

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0


bit 7 bit 0

Legend:



This register contains an image of the Register 6-17 NEG_PWR_ACT (Address 23h).The bits in this register reflectthe value of these settings that was active before the most recent REFRESH command (including REFRESH_V and/orREFRESH_G). The values in register 1Dh may have been programmed but not activated by one of the REFRESHcommands, and the values in 23h are currently active. This register allows software to determine the actual active set-ting that was active prior to the most recent REFRESH command and therefore corresponds to the dataset that is heldin the readable registers. This register is valid when the Results registers are valid, 1 ms after a REFRESH/_V/_Gcommand.

bit 7:0 The value of these settings that was latched prior to the most recent REFRESH command (including REFRESH_V and/or REFRESH_G)

bit 7 0 = Channel 1 VSENSE ADC converts 0 to +100mV range with 16-bit straight binary output1 = Channel 1 VSENSE ADC converts –100mV to +100mV range with 16 bit two’s complement output

bit 6 0 = Channel 2 VSENSE ADC converts 0 to +100mV range with 16-bit straight binary output1 = Channel 2 VSENSE ADC converts –100mV to +100mV range with 16-bit two’s complement output



PAC1934






REGISTER 6-21: PRODUCT ID REGISTER (ADDRESS FDh)

R-0 R-1 R-0 R-1 R-1 R-0 R-1 R-1

PID<7:0>

bit 7 bit 0

Legend:



bit 7:0 PID<7:0>: This register contains the Product ID for the PAC1934. This register is writable only when it is unlocked for test mode, always readable.

0101_1011 for PAC1934 (Default shown in table directly above)

REGISTER 6-22: MANUFACTURER ID REGISTER (ADDRESS FEh)

R-0 R-1 R-0 R-1 R-1 R-1 R-0 R-1

MID<7:0>

bit 7 bit 0

Legend:



bit 7:0 MID<7:0>: The Manufacturer ID register identifies Microchip as the manufacturer of the PAC1934This value is 5Dh.

REGISTER 6-20: NEG_PWR _LAT (ADDRESS 26H) (CONTINUED)


PAC1934

REGISTER 6-23: REVISION ID REGISTER (ADDRESS FFh)

R-0 R-0 R-0 R-0 R-0 R-0 R-1 R-1

RID<7:0>

bit 7 bit 0

Legend:



bit 7:0 RID<7:0>: The Revision register identifies the die revision

This register reads 03h.


PAC1934

7.0 PACKAGE DESCRIPTION

7.1 Package Marking Information

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week ‘01’)NNN Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of availablecharacters for customer-specific information.

3e

3e

WLCSP-16 Example

934725


PAC1934


PAC1934

Notes:


PAC1934


PAC1934

NOTES:



PAC1934

APPENDIX A: REVISION HISTORY

Revision B (November 2017)

The following is the list of modifications:

1. Updated Section 4.5 “Voltage Measurement”,Section 4.6 “Current Measurement”,Section 4.7 “Selecting RSENSE Values” andSection 4.9 “Power and Energy”.

2. Updated Register 6-10.

3. Fixed minor typographical errors.

Revision A (September 2017)

• Initial Release for Advance Data Sheet.

PAC1934


PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X -X /XXX

Tape and TemperatureDevice

Device: PAC1934: DC Power/Energy Monitor with Accumulator

Tape and Reel: T = Tape and Reel

TemperatureRange:

I = -40C to +85C (Industrial)

Package: 6CX = 16-Ball Wafer Level Chip Scale Package, 2.225 mm x 2.17 mm (WLCSP)

J6CX = This part number is being phased out and it is identi-cal to the 6CX package.

Reel RangePackage

Example:

a) PAC1934T-I/6CX: 16-lead 2.225 mm x 2.17 mmWLCSP, shipped in a 5,000piece Tape and Reel

Note 1: Tape and Reel identifier only appears in the catalog part number description. This identi-fier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights unless otherwise stated.

2017 Microchip Technology Inc.

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

QUALITYMANAGEMENTSYSTEMCERTIFIEDBYDNV

== ISO/TS16949==

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2017, Microchip Technology Incorporated, All Rights Reserved.

ISBN: 978-1-5224-2393-5

DS20005850B-page 55


AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200 Fax: 480-792-7277Technical Support: http://www.microchip.com/supportWeb Address: www.microchip.com

AtlantaDuluth, GA Tel: 678-957-9614 Fax: 678-957-1455

Austin, TXTel: 512-257-3370

BostonWestborough, MA Tel: 774-760-0087 Fax: 774-760-0088

ChicagoItasca, IL Tel: 630-285-0071 Fax: 630-285-0075

DallasAddison, TX Tel: 972-818-7423 Fax: 972-818-2924

DetroitNovi, MI Tel: 248-848-4000

Houston, TX Tel: 281-894-5983

IndianapolisNoblesville, IN Tel: 317-773-8323Fax: 317-773-5453Tel: 317-536-2380

Los AngelesMission Viejo, CA Tel: 949-462-9523Fax: 949-462-9608Tel: 951-273-7800

Raleigh, NC Tel: 919-844-7510

New York, NY Tel: 631-435-6000

San Jose, CA Tel: 408-735-9110Tel: 408-436-4270

Canada - TorontoTel: 905-695-1980 Fax: 905-695-2078

ASIA/PACIFICAustralia - SydneyTel: 61-2-9868-6733

China - BeijingTel: 86-10-8569-7000

China - ChengduTel: 86-28-8665-5511

China - ChongqingTel: 86-23-8980-9588

China - DongguanTel: 86-769-8702-9880

China - GuangzhouTel: 86-20-8755-8029

China - HangzhouTel: 86-571-8792-8115

China - Hong Kong SARTel: 852-2943-5100

China - NanjingTel: 86-25-8473-2460

China - QingdaoTel: 86-532-8502-7355

China - ShanghaiTel: 86-21-3326-8000

China - ShenyangTel: 86-24-2334-2829

China - ShenzhenTel: 86-755-8864-2200

China - SuzhouTel: 86-186-6233-1526

China - WuhanTel: 86-27-5980-5300

China - XianTel: 86-29-8833-7252

China - XiamenTel: 86-592-2388138

China - ZhuhaiTel: 86-756-3210040

ASIA/PACIFICIndia - BangaloreTel: 91-80-3090-4444

India - New DelhiTel: 91-11-4160-8631

India - PuneTel: 91-20-4121-0141

Japan - OsakaTel: 81-6-6152-7160

Japan - TokyoTel: 81-3-6880- 3770

Korea - DaeguTel: 82-53-744-4301

Korea - SeoulTel: 82-2-554-7200

Malaysia - Kuala LumpurTel: 60-3-7651-7906

Malaysia - PenangTel: 60-4-227-8870

Philippines - ManilaTel: 63-2-634-9065

SingaporeTel: 65-6334-8870

Taiwan - Hsin ChuTel: 886-3-577-8366

Taiwan - KaohsiungTel: 886-7-213-7830

Taiwan - TaipeiTel: 886-2-2508-8600

Thailand - BangkokTel: 66-2-694-1351

Vietnam - Ho Chi MinhTel: 84-28-5448-2100

EUROPEAustria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393

Denmark - CopenhagenTel: 45-4450-2828 Fax: 45-4485-2829

Finland - EspooTel: 358-9-4520-820

France - ParisTel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany - GarchingTel: 49-8931-9700

Germany - HaanTel: 49-2129-3766400

Germany - HeilbronnTel: 49-7131-67-3636

Germany - KarlsruheTel: 49-721-625370

Germany - MunichTel: 49-89-627-144-0 Fax: 49-89-627-144-44

Germany - RosenheimTel: 49-8031-354-560

Israel - Ra’anana Tel: 972-9-744-7705

Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781

Italy - PadovaTel: 39-049-7625286

Netherlands - DrunenTel: 31-416-690399 Fax: 31-416-690340

Norway - TrondheimTel: 47-7289-7561

Poland - WarsawTel: 48-22-3325737

Romania - BucharestTel: 40-21-407-87-50

Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91

Sweden - GothenbergTel: 46-31-704-60-40

Sweden - StockholmTel: 46-8-5090-4654

UK - WokinghamTel: 44-118-921-5800Fax: 44-118-921-5820

Worldwide Sales and Service

10/25/17

http://support.microchip.com

http://www.microchip.com

PAC1934 Four-Channel DC Power/Energy Monitor with ...ww1.microchip.com/downloads/en/DeviceDoc/20005850B.pdfFour Channel DC Power/Energy Monitor with Accumulator PAC1934 DS20005850B-page

Documents