P07202: Motor Module – Robotic Platform 100kg Robert Saltarelli: Project Manager Erich Hauenstein: Mechanical Member Dustin Collins: Mechanical Member Jasen Lomnick: Mechanical Member Saul Rosa: Electrical Member Derrick Lee: Electrical Member Muhammad Moazam: Electrical Member Vincent Capra: Electrical Member Sponsor: Gleason Foundation
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P07202 100kg Motor Moduleedge.rit.edu/content/P07202/public/Deliverables/sdII/P... · Machining Very mechanically intense design Hours of machining each day since the beginning of
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P07202: Motor Module –
Robotic Platform 100kg
Robert Saltarelli: Project Manager
Erich Hauenstein: Mechanical Member
Dustin Collins: Mechanical Member
Jasen Lomnick: Mechanical Member
Saul Rosa: Electrical Member
Derrick Lee: Electrical Member
Muhammad Moazam: Electrical Member
Vincent Capra: Electrical Member
Sponsor: Gleason Foundation
P07202: Functionality
P07202: Mechanical Design
Machining
Very mechanically intense design
Hours of machining each day since
the beginning of January
Over 36 parts on each driven motor
module
Over 30 of these parts were
machined or modified
Machining• Machine shop staff was very
helpful through out the entire process.
• Advanced machining techniques were introduced and explained by Rob Kraynik, Dave Hathaway and Steve Kosciol.
Rob performed
welding for several of
the subassemblies
Machining
• The Brinkman CNC
machining lab was
needed on 3 parts.
• The need for
precision led to the
use of CNC
• Ease of mass
production
Lessons Learned
• Price is usually a good measure of quality
• Modification of COTS parts may save
money, but does add time to
manufacturing
• Manufacturers models do not always
match the actual product.
• Easy to add to a CAD model ≠ Easy to
Machine!! (i.e. precise round plates)
Mechanical Design Modifications
• Extension of vertical driveshaft and addition of a supporting bearing to handle radial load exerted by spur gear
• Change from retaining rings to spacers, threaded axles, and washers
• Simplification of Yoke Sides
• Simplification of Motor Cage
• Change to smaller belt
• Additional washers to support available hardware
Verifying COTS Motor Performance
•Obtained dynamometer from Dave Krispinsky
•Fabricated coupling and mounting for motor to attach
to dyno
•Applied several
loading conditions to
motor and took
readings from
dynamometer
•Motor speed was
found using timing gun
provided by Dr.
Kempski
P07202: The H-Bridge
• First revision prototype on etch board PCB
• Cleaned copper is written over with sharpie marker.
Then the holes for through-hole devices are tapped
and drilled out
• After the necessary leads are soldered on the components can be placed and
the revision of the board is ready for testing.
• Made use of simulated input signals and tested under loading conditions.
• After several revisions for the steering and drive motors, aftermarket H-Bridges
were purchased due to budget constraints.
• The design schematics, simulations, and PCB
Layout files were well documented for possible
future use and mass production.
Power Board
Originally design but
not implemented.
Included 6X 5V 1A
lines, Battery
Monitoring, Battery
Indication, and
Status Relay to
P07302.
(Rev A Power Board Layout)
+5V_5
0
+5V_6
0
J6
HEADER 2X2
34
12
+5V_3
D5
LTST-C170KGKT
0
+5V_6
0
0
0% LED
0
VREF
CAD MAINTAINED CHANGES INCORPORATED BY THE DESIGN PROCESS
+5V
BATT0
U8
US5881LUA
1
23Vdd
OutGnd
+5V
F1
HEADER 2X2
34
12
0
U6
US5881LUA
1
23Vdd
OutGnd
0
+5V_2
+5V_2
R11
7.15k
100% LED
NOTE 1.1
+5V
R2
5k
0
0
+5V_5
VBATT
D7
LTST-C170KGKT
75% LED
0
0
NOTE 1.1
0
BATT50
R22
100D13
LTST-C170KGKT
VBATT
D14
LTST-C170KGKT
+5V_3
BATT25
R27
100
25% LED
NOTE 1.1
0
J2
HEADER 2X2
34
12
J1
HEADER 2
12
+5V_6
+5V
VBATT
R14
7.15k
0
R10
5.9k
0
+5V_6
NOTE 1.1
VREF
BATT50
0
D12
LTST-C170KGKT
00
U10
US5881LUA
1
23Vdd
OutGnd
0
R6
100
VBATT0
R20
100
BATT100
+5V_3
NOTE 1.1
0 R28
100
R7
8.06k
U13
REF192
1
2
3
4 5
6
7
8NC
Vin
SLEEP
Gnd NC1
Out
NC2
NC3
C2310u
VREF
J4
HEADER 2X2
34
12
0
+5V
D6
LTST-C170KGKT
VREF
NOTE 1.1
+5V_1
C260.1u
U3
LM193DR
1
2
3
4 5
6
7
8Out1
In1-
In1+
Gnd In2+
In2-
Out2
Vcc
R19
100
R21
100
0
0
+5V
BATT50_100
+5V
J7
HEADER 2X2
34
12
J3
HEADER 2X2
34
12
R24
100
VREF
100u
C18
0
VBATT
NOYE 4.0
0
0
+5V_1
U9
US5881LUA
1
23Vdd
OutGnd
+5V_4
D10
LTST-C170KGKT
VBATT
D2
LTST-C170KGKT
N/A A
SCHEMATIC, BOARD, CONTROL, POWER
B
1 1Friday , January 26, 2007
Title
Size Document Number Rev
Date: Sheet of
+5V_4
U1
LM193DR
1
2
3
4 5
6
7
8Out1
In1-
In1+
Gnd In2+
In2-
Out2
Vcc
0
C240.1u
1uC25
R1
8.5k
NOYE 4.0
+5V_1
0
0
D15
LTST-C170KGKT
+5V_5
100u
C19
NOYE 4.0
0
VBATT
BATT100
J8
HEADER 2
12
BATT75
VREF
R26
100
+5V_4
0
R85.36k
NOTE:
1.0 - J1: Battery Inlet
1.1 - Powe to individual Modules
2.0 - 5.0 (V) Voltage reference generator
3.0 - Voltage Regulation from 12V to 5.0V
4.0 - Load Indicator for Motor Module Side
* For Layout: Vout Trace from Regulator
has to go below of the
Hall effect Chip.
J9
HEADER 3
123
+5V_3
0
0
+5V
+5V
+5V
U2
LM193DR
1
2
3
4 5
6
7
8Out1
In1-
In1+
Gnd In2+
In2-
Out2
Vcc
U16
N74F298D
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16I1b
I1a
I0a
I0b
I1c
I1d
I0d
GND 10c
S
CP'
Qd
Qc
Qb
Qa
VCC
0
R23
100
NOYE 4.0
0
U7
US5881LUA
1
23Vdd
OutGnd
D9
LTST-C170KGKT
VREF
R25
100
0
+5V_2
+5V_1
+5V_5
U11
US5881LUA
1
23Vdd
OutGnd
NOYE 4.0
VBATT
VREF
+5V_2
0
R9
7.8k
0
+5V
VBATT
BATT50_100
J5
HEADER 2X2
34
12
100u
C17
0
NOTE 1.0
NOYE 4.0
+5V_4
VBATT
BATT75
R12
6.34k
BATT75
+5V
0
VREFR13
6.34k
50% LED
D8
LTST-C170KGKT
Motor Control Board
• Xilinx FPGA processor
• JTAG Programming
• CAN Communications
• Interfacing to H-Bridge
• Encoder Interpretation
• Built in Multi Stage
Regulation
• Custom PCB design
• Board Temperature
Sensing
0
INPUT_D
B_DRIVE
JTAG_TMS
STEER_B
B_DRIVE_FPGA
B_DRIVE_FPGA
CAN_RX0BF
FPGA_DONE
+1_2V
FPGA_INIT_B
R5
4.7k
TEMP_CS
STEAR_B
CAN_TX0RTS_FPGA
CAN_INT_FPGA
JTAG_TDI
+3_3V
CAN_TX2RTS
TEMP_SC
M1
0
INPUT_C
A_STEAR
INDEX_STEAR
CAN_SO
TEMP_CS
LED2
LED1
CAN_SCK
CAN_SO_FPGA
M0
INDEX_STEAR
0
INDEX_STEAR_FPGA
CAN_RX1BF_FPGA
TEMP_SI
+5V to +3.3V Interface Buffering
NOTE 1.0
B_STEAR
CAN_SI_FPGA
+3_3V
FPGA_CCLK
+3_3V
+2_5V
U10
3HM57-B-100.000R-C1.5
12
34
NCGND
SSC_OUTVCC
LED4
CAN_CS
CAN_CS_FPGA
0
+5V
CAN_RX0BF_FPGA
STEAR_A
CAN_TX1RTS
INDEX_DRIVE_FPGA
A_DRIVE_FPGA
NOTE:
1.0 - TOP(1) +3.3 to +5V (Right to Left)
BOTTOM(2) +5V to +3.3V (Left to Right)
CAN_TX2RTS_FPGA
LED4
STEER_C
INPUT_A
0
JTAG_TDI
CAN_TX1RTS
LED3
INPUT_D
U1
XC3S100E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144PROG_B
IO_L01P_3
IO_L01N_3
IO_L02P_3
IO_L02N_3/VREF_3
IP
IO_L03P_3
IO_L03N_3
VC
CIN
T0
IP1
GN
D0
IP/VREF_3
VC
CO
_30
IO_L04P_3/LHCLK0
IO_L04N_3/LHCLK1
IO_L05P_3/LHCLK2
IO_L05N_3/LHCLK3
IP2
GN
D1
IO_L06P_3/LHCLK4
IO_L06N_3/LHCLK5
IO_L07P_3/LHCLK6
IO_L07N_3/LHCLK7
IP3
IO_L08P_3
IO_L08N_3
GN
D2
VC
CO
_31
IP4
VC
CA
UX
0
IO/VREF_3
IO_L09P_3
IO_L09N_3
IO_L10P_3
IO_L10N_3
IP5
GN
D3
IP6
IO_L01P_2/CSO_B
IO_L01N_2/INT_B
IP7
VC
CO
_20
IO_L02P_2/DOUT/BUSY
IO_L02N_2/MOSI/CSI_B
VC
CIN
T1
GN
D4
IP_L03P_2
IP_L03N_2/VREF_2
VC
CO
_21
IO_L04P_2/D7/GCLK12
IO_L04N_2/D6/GCLK13
IO/D5
IO_L05P_2/D4/GCLK14
IO_L05N_2/D3/GCLK15
GN
D5
IP_L06P_2/RDWR_B/GCLK0
IP_L06N_2/M2/GCLK1
IO_L07P_2/D2/GCLK2
IO_L07N_2/D1/GCLK3
IO/M1
GN
D6
IO_L08P_2/M0
IO_L08N_2/DIN/D0
VC
CO
_22
VC
CA
UX
1
IO/VREF_2
IO_L09P_2/VS2/A19
IO_L09N_2/VS1/A18
IP8
IO_L10P_2/VS0/A17
IO_L10N_2/CCLK
DONE
GN
D7
IO_L01P_1/A16
IO_L01N_1/A15
IO_L02P_1/A14
IO_L02N_1/A13
IP9
VC
CO
_10
VC
CIN
T2
IO_L03P_1/A12
IO_L03N_1/A11
IO/VREF_1
IP10
IO_L04P_1/A10/RHCLK0
IO_L04N_1/A9/RHCLK1
IO_L05P_1/A8/RHCLK2
IO_L05N_1/A7/RHCLK3
IP11
GN
D8
IO_L06P_1/A6/RHCLK4
IO_L06N_1/A5/RHCLK5
IO_L07P_1/A4/RHCLK6
IO_L07N_1/A3/RHCLK7
IP/VREF_1
IO_L08P_1/A2
IO_L08N_1/A1
IO/A0
GN
D9
VC
C0_11
IP12
VC
CA
UX
2
IO_L09P_1/HDC
IO_L09N_1/LDC0
IO_L10P_1/LDC1
IO_L10N_1/LDC2
IP13
TMS
TDO
TCK
IP14
IO_L01P_0
IO_L01N_0
IP15
VC
CIN
T3
IP_L02P_0
IO_L02N_0
GN
D10
IP_L03P_0
IP_L03N_0
VC
CO
_00
IO_L04P_0/GCLK5
IO_L04N_0/GCLK5
IO/VREF_0
IO_L05P_0/GCLK6
IO_L05N_0/GCLK7
GN
D11
IP_L06P_0/GCLK8
IP_L06N_0/GCLK9
IO_L07P_0/GCLK10
IO_L07N_0/GCLK11
IO
GN
D13
IO_L08P_0
IO_L08N_0/VREF_0
IP16
VC
CA
UX
3
VC
CO
_01
IO_L09P_0
IO_L09N_0
IP17
IO_L10P_0
IO_L10N_0/HSWAP
TDI
+1_2V
STEAR_A
U3
XCF01SVO20C
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20D0
NC0
CLK
TDI
TMS
TCK
CF
OE/RESET
NC1
CE GND
NC2
CEO
NC3
NC4
NC5
TDO
VCCINT
VCCO
VCCJ
TEMP_SI
CAN_SO_FPGA
FPGA_PROG_B
A_DRIVE
TEMP_SI
CAN_TX2RTS
0
CAN_CS
M1
+5V
FPGA_JTAG_TDI
N/A A
FPGA + LOGIC LEVEL CONV, MOTOR CONTROL BOARD, P07202
C
1 2Thursday , February 15, 2007
Title
Size Document Number Rev
Date: Sheet of
JTAG_TDO
JTAG_TDI
INPUT_C
+3_3V
CAN_TX1RTS_FPGA
+1_2V
CAN_SCK
INPUT_B
A_DRIVE_FPGA
INPUT_D
+2_5V
CAN_INT
CAD MAINTAINED CHANGES INCORPORATED BY THE DESIGN PROCESS
JTAG_TDO
0
B_STEAR_FPGA
CAN_TX0RTS
CAN_CLKOUT
LED1
JTAG_TCK
A_STEAR_FPGA
DIN
STEAR_D
LED2
JTAG_TMS
CAN_INT
100MHz OSCILLATOR
TEMP_SC
CAN_SCK
CAN_SCK_FPGA
B_STEAR
INPUT_C
0
INDEX_STEAR
M2
JTAG_TCK
CAN_TX0RTS
TEMP_SC
JTAG_TMS
0
R6
330
CAN_INT_FPGA
LED2
CAN_TX2RTS
INDEX_DRIVE_FPGA
CAN_TX1RTS_FPGA
INPUT_A
FPGA_INIT_B
CAN_CLKOUT
LED3
A_STEAR
CAN_TX0RTS_FPGA
+3_3V
CAN_SO
INPUT_A
M1
INDEX_DRIVE
+3_3V
STEAR_D
CLOCK
INDEX_DRIVE
+3_3V
CAN_TX1RTS
STEER_D
CAN_CS
+5V
+3_3V
INPUT_B
0
CAN_TX0RTS
CAN_SI_FPGA
B_DRIVE
B_STEAR
JTAG_TDO
+2_5V
TP9
TEST POINT
1
M0
JTAG_TCK
JTAG_TCK
0
CAN_SO
CAN_INT
M2
CAN_SI
FPGA_CCLK
+5V
CAN_TX2RTS_FPGA
CAN_SI
+3_3V
B_STEAR_FPGA
+3_3V
CAN_RX1BF
A_DRIVE
LED1
CAN_RX0BF
FPGA_JTAG_TDI
M2
0
CAN_RX1BF_FPGA
CAN_RX0BF
CAN_RX0BF_FPGA
INDEX_DRIVE
M0
R4
4.7k
INPUT_B
FPGA_DONE
+2_5V
FPGA_PROG_B
0
B_DRIVE
CAN_SCK_FPGA
CAN_RX1BF
A_STEAR
A_STEAR_FPGA
INDEX_STEAR_FPGA
STEER_A
U2
SN74ALVC164245
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
481DIR
1B1
1B2
GND0
1B3
1B4
VCCB0
1B5
1B6
GND1
1B7
1B8
2B1
2B2
GND2
2B3
2B4
VCCB1
2B5
2B6
GND3
2B7
2B8
2DIR 2OE
2A8
2A7
GND4
2A6
2A5
VCCA0
2A4
2A3
GND5
2A2
2A1
1A8
1A7
GND6
1A6
1A5
VCCA1
1A4
1A3
GND7
1A2
1A1
1OE
CAN_RX1BF
TEMP_CS
CAN_SI
0
LED3
+1_2V
+2_5V
JTAG_TMS
STEAR_C
STEAR_B
LED4
CAN_CS_FPGA
J3
PIN HEADER
2468
1012141618
1357911131517
A_DRIVE
CLOCK
DIN
STEAR_CSTEAR_C
INDEX_STEAR
B_DRIVE
CAN_SO
CAN_RX1BF
+5V
TP1
TEST POINT
1
CAN Tranciever
STEAR_A
INDEX_STEAR
C18
0.1uF
D1
LL4448
+3_3VA_STEAR
+2_5V
TANT 22uF
C30
C7
0.1uF
U9
TPS76912DBVT
1
3
4
5
2
IN
EN'
NC/FB
OUT
GN
D
STEAR_B
TP7
TEST POINT
1
C35
1u
LED3
D3
SS12
C8
0.1uF
CAD MAINTAINED CHANGES INCORPORATED BY THE DESIGN PROCESS
0
A_DRIVE
JTAG_TDO
M2
R9
65
0
M1
CAN_SO
C13
0.1uF
0
Drive Encoder
+3_3V
CAN_RX1BF
R7
65
C12.2u
D9
LTST-C170KGKT
0
0
CAN_TX0RTS
+3_3V
+5V
LED2
STEAR_B
INPUT_D
R12
4.7k
TP2
TEST POINT
1
INPUT_D
JTAG_TCK
+2_5V
C6
0.1uF
TANT 22uF
C31
B_STEAR
JTAG_TMS
CAN_CLKOUT
INPUT_D
TEMP_CS
TANT 22uF
C39
+5V
C29
0.1uF
TP10
TEST POINT
1
0
CAN_SI
R13
10k
STEAR_D
LED2
B_STEAR
M2
C40
1n
D6
LTST-C170KGKT
0
C5
0.1uF
0
STEAR_C
A_STEAR
+5V
TP5
TEST POINT
1
+1.2V
M0
A_DRIVE
JTAG_TDO
TP14
TEST POINT
1
0
STEAR_A
TP8
TEST POINT
1
TANT 10u
C4
+5V
A_STEAR
CAN_TX1RTS
CAN_CLKOUT
+5V
R8
65
D2
LL4448
CAN_SCK
STEAR_A
CAN_CS
N/A A
CAN + CONNECTIONS, MOTOR CONTROL BOARD, P07202
C
2 2Thursday , February 15, 2007
Title
Size Document Number Rev
Date: Sheet of
+2_5V
TEMP_SI
LED4
STEAR_C
C26
0.1uF
C2 0.01u
H3
11
JTAG_TDI
0
+5V
D4
LTST-C170KGKT
TANT 22uF
C12
H2
11
INDEX_DRIVE
B_STEAR
0
U7
TPS73HD325PWPR
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28NC
NC2
1GND
1EN'
1IN
1IN2
NC3
NC4
2GND
2EN'
2IN
2IN2
NC5
NC6 NC7
NC8
2OUT2
2OUT
2SENSE
NC9
NC10
2RESET'
1OUT2
1OUT
1FB/SENSE
NC11
NC12
1RESET'
C36
22pF
U5
MCP2515
1
2
3
4
5
6
7
8
9 10
11
12
13
14
15
16
17
18TXCAN
RXCAN
CLKOUT/SOF
TX0RTS
TX1RTS
TX2RTS
OSC2
OSC1
VSS RX0BF
RX1BF
INT
SCK
SI
SO
CS
RESET
VDD
+1.2V Regulator
0
0
C27
0.1uF
TP6
TEST POINT
1
LED4
R15
3.16k
R11
4.7k
CAN_TX2RTS
CAN_INT
+3.3V
VBATT
U6
LM70CIMM-5
1
2
3
4 5
6
7
8SI/O
SC
NC
GND V+
NC2
CS
NC1
J6
HEADER 3
123
INDEX_STEAR
+1_2V
M1
JTAG_TMS
C28
0.1uF
+3_3V
J7
HEADER 3
123
+5V
CAN_SCK
+5V
CAN_RX0BF
0
CAN_SO
TANT 22uF
C32
0
INPUT_C
4.7u
C20
TP4
TEST POINT
1
0
J4
PIN HEADER
123456
NOTE:
1.0 - Center near FPGA
TEMP_SC
+5V
0
0
JTAG_TCK
+5V STEAR_D
D10
SK12-TP
R17
100
CAN_CS
+2_5V
+5V
INDEX_DRIVE
U4
MCP2551
1
2
3
4 5
6
7
8TXD
VSS
VDD
RXD VREF
CANL
CANH
RS
Stearing Encoder
MO
+2_5V
JTAG_TDI
C16
0.1uF
J10
39-30-1040
34
12
CAN_SI
CAN_RX0BF
TEMP_CS
C17
0.1uF
CAN_RX1BF
JTAG_TDO
INDEX_DRIVE
D5
LTST-C170KGKT
330uC34
R1
65
C15
0.1uF
CAN_TX1RTS
TP3
TEST POINT
1
P1
DB9-48202-6043
594837261
C10
0.1uF
0
JTAG_TDI
+2_5V
+5V Power LED
0
CAN_CLKOUT
STEAR_B
CAN_TX2RTS
INPUT_A
H1
11
0
CAN_INT
CAN_CS
TP12
TEST POINT
1
J8
IPS1-110-01-S-D-POL
135791113151719
2468
101214161820
L1
22uH1 2
TEMP_SI
C3
0.1uF
0
LED4
INPUT_A
LED2
B_DRIVE
CAN_INT
D8
B520C-13-F
AC
R3
120 1%
+3_3V
LED1
JTAG
0
CAN_TX0RTS
+3_3V
+5V
R1913.5k
M1
CLK1
NX2520SA-24.0MHz
CAN_TX0RTS
0
JTAG_TCK
INPUT_B
C14
0.1uF
U8
TPS5420
1
23
45
6
78
Boot
NCNC
VSenseENA
GND
VinPH
LED3
33uC24
Board Temprature Sensor
NOTE 1.0
0
+5V
A_DRIVE
1u
C22
D7
LTST-C170KGKT
LED1
M0
33u
C23
0
+5V
LED1
C25
0.1uF
0
INPUT_B
R247k
C9
0.1uF
TP11
TEST POINT
1
J1
0705550039
12345
+1_2V
CAN_TX1RTS
TEMP_SC
B_DRIVE
INPUT_B
TP13
TEST POINT
1
+3.3V and +2.5V Regulator
INPUT_C
R10
4.7k
JTAG_TMS
+1_2V
VBATT
INPUT_C1uC19
P2
DB9-48202-6043
594837261
R18
10k
CAN_SCK
CAN_RX0BF
J5
HEADER 3
123
INPUT_ATEMP_SC
0
LED3
C11
0.1uF
0
CAN_SI
CAN Interpreter
0C3722pF
J9
0705550039
12345
TEMP_SI
+5V
1u
C21
TEMP_CS
STEAR_D
CAN_TX2RTS
TANT 10u
C33
0
0
M2
P07202: Control and
Communications
•Precise control over system allows for optimal
efficiency designs
•High speed
•Power savings
•Fully parallel driven and steering control
systems achieves true simultaneous operation
•CAN protocol is fully addressable and
optimizes transmissions
•Significant potential for future functionality
•Incorporation of PIC soft core
•Generic I/O headers for interfacing with
additional circuitry (e.g. watchdog)
•Easy to add additional devices over CAN
P07202: Error Protection and
Failsafe Operation• CAN protocol provides robust protection against noise.
•Errors of up to 5 consecutives bits can be identified and corrected
•Differential signal is more immune to noise
•Shielded, twisted pair cabling used to mitigate risk of interference
•State encoding ensures that any errors are safely caught operation is returned to idle
mode
•Robust power up routines ensures integrity of system after booting
•Sophisticated I/O synchronization protects components from errors or potential
damage
•Encoder inputs are properly measured
•H-bridge lines never activated simultaneously
P07202: Digital Encoders
Drive EncoderSteer encoder
• The US Digital optical encoders were
ordered to measure the speed of the modules
using the measured RPM from the drive
motor shafts.
• A different model US Digital optical encoder
was used to measure the steering angle. An
indexing function helped to read and convert
the steering motor shaft’s RPM to an angular
position.
Pin-outs
Optical Ring
P07202: Testing• 3 Phases
– Initial• Baseline measurements
• Signals, Voltage levels
– Semi-Integration• Partial integration with Mechanical components
• To show components operate efficiently together
– Full Integration (Prototype)• Final measurements and stresses tested
• Reconfirmation of desired specifications
• Overall design assessed
P07202: Safety
• Several different fail-safe algorithms are coded
into the FPGA for a variety of disturbances:– No wheel contact with ground
– Liquid disturbances
– Collisions
– Communication connection loss
• Safety fuses are connected to the battery input
to avoid burning out the motors and breaches of
maximum speed.
• Current sensors are employed to ensure proper
functionality of critical signal lines.
Electrical Budget• Driver production cost (electrical)
– $267.11
• PCB– $17.13
• Chips
– $22.29
• H-bridges (COTS)
– $128.45
• Encoders– $98.32
• Cost of entire project– $1206.18
• Prototype cost– $334
Mechanical Budget• Driver prototype cost
– $651.14
• Driver production cost– $598.49
• Idler prototype/production cost– $121.82
• Cost of entire project– $2440.70
• Difference from original cost projection– $140.70