P. Narayanan, G. W. Burr, R. S. Shenoy, K. Virwani, and B ...researcher.watson.ibm.com/researcher/files/us-gwburr/CompareADs... · Circuit-Level Benchmarking of Access Devices for

Circuit-Level Benchmarking of Access Devices forResistive Nonvolatile Memory Arrays

P. Narayanan, G. W. Burr, R. S. Shenoy, K. Virwani, and B. KurdiIBM Research – Almaden, 650 Harry Road, San Jose, CA 95120, Tel: (408) 927–2920, E-mail: [email protected]

AbstractAccess Devices (1AD) for crossbar resistive (1R) memories

are compared via circuit-level analysis. We show that in additionto intrinsic properties, AD suitability for 1AD+1R memories isstrongly dependent upon (a) nonvolatile memory (NVM) and (b)circuit parameters. We find that (1) building large arrays (≥1Mb)with ≥10uA NVM current would require MIEC ADs and moder-ate NVM switching voltage (≤1.2V). (2) For all ADs high NVMvoltages (>2V) are supported only at sub-5uA currents. AD im-provements to expand this design space are discussed.Keywords: 1AD1R, Selector, Access Device, Nonvolatile memory

IntroductionDesirable AD properties for 3D resistive crossbar memories

(1AD+1R - Fig. 1) include BEOL compatibility, bipolar opera-tion for RRAM/MRAM and large ON/OFF ratios to support highON- current density through selected cells with ultra-low leakagein unselect and partial select cells. Beyond these basic proper-ties, determining whether an AD is suitable for an NVM requirescircuit-level analyses that capture complex interactions betweenAD, NVM and circuit parameters. We explore capabilities andlimitations of ADs in this design space by quantifying key figuresof merit such as total power consumption, maximum achievablearray size, and ranges of NVM voltages, currents supported.

Selected CellPartially (WL) Selected Cells

VW

es)

Selected CellPartially (WL) Selected Cells

s (W

ordl

ine

VR

cted

Cel

ls

elec

t Ro

ws

VR

(BL)

Sel

ec

(N-1

) U

nse

VR

Part

ially

VB(M-1) Unselect Columns (Bitlines)

(

VC VC VC

Fig. 1 Crossbar memory array with selected, partially (WL) selected, partially(BL) selected and unselected 1AD+1R cells.

Simulation FrameworkWe use a generic NVM model (Fig.2) that transitions between

Low- and High-Resistance States (LRS, HRS – can be Poole-Frenkel (PF) or Ohmic) as a function of applied voltage (default

Rseries I(selected NVM)

(VLRS , ILRS)

INFV(selected NVM)

(VHRS , IHRS) RHRS

V(selected NVM)Vh(VHRS , IHRS)

RHRS-PF

(VLRS , ILRS)

Fig. 2 Generic NVM model for SPICE, with switching between an ohmicLRS and an HRS exhibiting Poole-Frenkel conduction. Inset shows equivalentcircuit for SPICE modeling of bipolar diode-type ADs. Total array power towrite worst-case selected cell (Fig.1) must be estimated.

NVM ParametersNVM ParametersSET Switching VHRS, IHRS 1.2V, 3uARESET Switching VLRS, ILRS 0.8V, 30uAHolding V (SET) Vh 0 35VHolding V (SET) Vh 0.35VResistance States RLRS, RHRS 26.7kΩ, 400kΩPF [email protected] RHRS‐PF 10MΩ

Circuit ParametersCircuit Parameters Array Size N × M 1MbInterconnect R/cell Rint 2.215Ω

Table. 1 Default NVM and Circuit Simulation parameters.

parameters in Table 1). Inner voltages VC and VR for unselectedbitlines/wordlines are chosen for an aggregate unselect leakageof 10uA (e.g. for 1Mb array, 10pA/device). Total array powerto force a worst-case selected NVM through HRS–to–LRS andLRS–to–HRS transitions is estimated.

We consider 4 bipolar Diode-type ADs (D-ADs - MIEC [1],Varistor [5], Metal-amorphous Si-Metal [3] and Silicon NPN [7]- Fig.3). D-ADs are modeled as back-to-back diodes with a noisefloor (Fig. 2, top left inset). For all ADs, if IV data is not atscale (∼32nm CD) or if only current-density data is available, weestimate currents assuming constant current-density.

Voltage Margin (Vm – defined as voltage range over whichcurrent≤10nA), Turn-on Slope (S) and Series Resistance (Rs)parameters are extracted (Table 2). High Vm provides a wide low-leakage zone to accomodate partial-select cells in large arrays. LowS and Rs ensure low Voltage-across-AD (VAD), and consequentlylow total switching voltage (VSW ) to be applied at the edge of the

rent 100uA Series 

R i t

Curr

1uA

10uA Resistance(Rs)

100nA

1nA

10nA Vm

100pA

1nA

10pA

1 A

Voltage[V]‐3 ‐2 ‐1 0 1 2 3

1pA

Fig. 3 IV characteristics of Diode-type ADs (D-ADs): AD parameters –Voltage Margin (Vm – voltage range for current≤10nA), turn-on slope S(voltage for 10× current increase during AD turn-on) and series resistance Rs

are indicated.Diode‐Type ADs

Vm(V) Slope(mV/dec) Rs(kΩ)MaSiM 1 9 454 333 3 17MaSiM 1.9 454, 333 3, 17MIEC 1.54 85, 85 2.8, 2.8NPN 2.56 219, 430 80, 70Varistor 2.4 416, 282 19, 14Varistor 2.4 416, 282 19, 14

Threshold Switching ADsVth (V), Ith (uA) Vh Ron

CTS 1 67 6 2 1 41 1CTS 1.67, 6.2 1.41 1TVS 1.37, 0.87 0 1.8

Table. 2 Default Access Device Simulation parameters – among D-ADs,MIEC has the best turn-on slope and series resistance. Varistor and NPN havebetter voltage margin but slope and/or series resistance are also significantlyhigher and high voltages are required to drive high currents (Fig.3).

0.4 0.8 1.6 2.00.0 1.2Voltage[V]

0.4 0.8 1.6 2.00.0 1.2rr

ent

10uA VAD

Cu 1uA VP<10nA

10nA

100nA1/2Vm

VP>100nA!!

1nA

10nA

10 A

100pA

V10pA

1pA

VUN

Fig. 4 MIEC, Varistor operating points for selected, unselected and partiallyselected ADs under default NVM, circuit parameters. Large Varistor VAD

causes increased total switching voltage VSW , thereby causing high partialselect leakage. MIEC operating conditions are within manageable limits.

rent

10 A

100uA

R Vh

Curr

1uA

10uA Ron Vh

100nA Vth, Ith 

1nA

10nA

100pA

10pA

1pA

Voltage[V]0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

1pA

Fig. 5 I–V characteristics of Threshold-switching ADs(T-ADs): Off-state cur-rent is modeled as a Poole-Frenkel characteristic. V th, Ith represents thresh-old switching condition of AD. Vh represents holding voltage after switching,RON is threshold device ON-state resistance.

array to induce NVM switching (Fig.4, inset). AD operating pointsunder default NVM, circuit parameters are marked on MIEC andVaristor DC IV curves in Fig.4.

Threshold switching ADs (T-ADs, e.g. Threshold VacuumSwitch (TVS) [4] and Chalcogenide Threshold Switch (CTS) [6],Fig. 5) can ‘snapback’ to low holding voltage above a currentthreshold, thereby reducingVAD andVSW at NVM switching. Thismay seem an ‘unfair’ advantage for T-ADs over D-ADs, especiallywhen Vh∼0 (TVS). However, array design can still be constrainedby total switching voltage, power to induce AD thresholding asopposed to NVM switching (Fig.6), and must be included in circuit

I t NVM SET CurrentIxpt NVM SET Current Threshold > AD Switching Threshold

VxptVXPT to Switch AD

VXPT @SET Start

VXPT @SET End ADStart End

Fig. 6 Maximum voltage required at selected cell, and consequently worst-case power consumption in the array, can occur at the threshold condition ofT-ADs (Fig. 5), as opposed to NVM switching conditions – illustrated in thisdiagram, with a representative T-AD IV and varying load lines representinginstantaneous resistances of NVM.

Selected CellPartially (WL) Selected Cells Selected CellPartially (WL) Selected Cells

s

VW

ecte

d Ce

llsy

(BL)

Sel

e

VR

Part

ially

VR

VB

VC

B

Fig. 7 Com-bining allunselect cellsinto a singleaggregateDiode+NVMsignificantlyreduces num-ber of nodes,simplify-ing circuitanalysis oflarge scalecrossbararrays.

Ri tI1+INVMI2+I1+INVM

INVM

Rint

V

1 NVM

V IV IV I

2 1 NVM

INVM VxptV1,I1V2,I2VK,IK

+

V1,I1Vinner—

V IV2,I2

Fig. 8 A hybrid circuit-simulation/analytical approach for analysis crossbararray conditions – by iterating currents and voltages outwards from the selectedcell, one can estimate the voltage/current/power conditions at the edge of thearray to induce NVM switching.

100

Wat

ts]

10

100 Iterative Method

[mill

i-W 10 Method

wer

[

1 SPICE Full Circuit

Pow

0.1Full Circuit

VHRS 1 2V

4Kb 16Kb 64Kb 256Kb 1Mb 4MbSPICE ReducedVHRS = 1.2V

Array SizeFig. 9 Power consumption vs. Array size for 1MIEC+1NVM crossbar arrays:plot shows near-identical correspondence between full-SPICE simulations andapproximate methods described in Figs. 7 and 8 for 2 different NVM VHRS

conditions.

analysis.To evaluate ∼Mb arrays, number of circuit nodes is reduced

by replacing all unselect cells by a single aggregate device (Fig.7).Given operating conditions at selected cell, iterating outwards candetermine voltage/current/power at the edge of the array to induceswitching (Fig.8). Fig.9 shows excellent agreement in power for1MIEC+1NVM using iterative, reduced SPICE and full simulation.

Design Space Exploration of ADsWrite power poses the most stringent constraint for 1AD+1R

designs [2]. Design points become unfavorable if total array powerfar exceeds baseline power to switch AD+NVM. Fig. 10 plots acolor map of total power for MIEC+NVM arrays when varyingVHRS and array size. At favorable design points (blue) most ofthe applied power is consumed at the selected cell; at unfavorable

≥10mW2.25MbArray size

≥10mW

1.89Mb

2.25Mb

1.57Mb

5mW

1Mb

1.26Mb

% Change in VHRS6 b

784Kb

1Mb

HRSfrom nominalVHRS=1.2V

1mW

50% 30% 10%10% 30% 50%256Kb400Kb576Kb

-50% -30% +10%-10% +30% +50%56 b

Fig. 10 Colormap of write power vs. VHRS and array size for MIEC ADsfrom[2]: blue regions represent favorable design points with power consump-tion dominated by selected cell switching, red regions represent unfavorabledesign points with extreme sneak path leakage through partial-select cells.

4Mbe 4Mb

1Mbay S

ize

VLRS=0.8V

256Kb

1Mb

Arra

256Kb

64KbNPN

MaSiM

16Kb

NPN

4KbCTS

0.6 1 1.5 2 2.5 3.0VHRS [V]

0.6 1 1.5 2 2.5 3.0

Fig. 11 Write power consumption contours at 1mW vs. NVM VHRS andarray size demarcating favorable (left and down) and unfavorable (right andup) design points for D-ADs and T-ADs. MIEC ADs can support array sizes≥1Mb at moderate switching voltages. The star marks MIEC + nominal NVMparameters.

points (red), partial select ADs allow significant sneak path currentsthat can dominate power consumption.

Fig.11 shows 1mW power contours used to delineate favorable(left, down) vs. unfavorable (top, right) regions for all ADs. Thegraphs validate that AD suitability is coupled strongly to extrinsicparameters - MIEC ADs can support array sizes up to 2Mb at low-to-moderate switching voltages≤1.2V, whereas Varistor is betterat VHRS≥1.5V but only on much smaller arrays. No AD cansupport high NVM switching voltage and large array sizes at defaultcurrent values. CTS can support only small arrays, since leakageis relatively high, even at low bias. Contour ‘plateaus’ indicateregions where array power is limited by constant VLRS ,ILRS . Anextreme case is NPN, which shows no dependence on VHRS –high series resistance implies large VAD to deliver 30uA. Fig. 12assumes VLRS scales as 2/3VHRS . Trends are similar, but MIECcan support larger array sizes (4Mb) at low switching voltage, asVAD reduces. Fig.13 shows that moderate increase in NVM voltagesupported is achieved with LRS non-linearity for MIEC, TVS andVaristor. Other ADs do not appear since array size (1Mb) is larger

16Mb

4Mb

16Mb

Size VLRS=2/3×VHRS

1Mb

Arra

y

256Kb

64Kb

A

64Kb

16Kb

4Kb0 6 1 1 5 2 2 5 3 0

VHRS [V]0.6 1 1.5 2 2.5 3.0

Fig. 12 Varying VHRS and VLRS simultaneously removes ‘plateau’ contourslimited by constant VLRS assumption. Moderate expansion in supporteddesign space observed for MIEC and Varistor.

110

earit

y

30

n-Li

ne

Array Size: 1Mb

50

RS N

on

yLRS Non‐Linearity= R@SETEnd/[email protected]

70

VM L

R

NPN, MaSiM, CTS90

0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

NV CTS

0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0VHRS [V]

Fig. 13 Increasing NVM non-linearity moderately improves voltage rangessupported by certain ADs since partial select leakage can be reduced. Yet,switching voltages ≥2V are not supported. NVM non-linearity also has noimpact on ADs that were already unsustainable at 1Mb in Fig.12.

than what they can support.Figs.14, 15 plot I vs. V design space for array sizes of 256Kb

and 1Mb, assuming VLRS=2/3VHRS and ILRS=10×IHRS . D-ADs follow their device I-V (e.g. Varistor contour). In linearsegments, D-ADs are limited by Rs – VAD trades off in proportionto VHRS ; exponential segments show diode action (large change incurrent for small change in voltage) which implies that lower NVMswitching voltage is an extremely important design consideration.NPN follows a nearly linear contour, given highRs. At lower ILRS ,IHRS (10uA, 1uA - may be required for interconnect scaling), NPNADs can support 256Kb arrays with a relatively high VHRS of 2.5V.

Vm can be doubled by stacking two ADs in series; VHRS upto 2.5V, and array size of 1Mb can be supported by double MIEC(Fig.16). Stacking is not as effective on other D-ADs with poor S,Rs, since Vm benefits are offset by large increase in VAD.

At ILRS≤10uA, TVS is constrained by NVM switching whereasat higher currents, worst-case power occurs at Vth, Ith (Fig.17). IfAD switching is orders of magnitude faster than NVM, instanta-neous power for AD threshold can be ignored and TVS ADs can

50] 50

40nt

[uA] M

IE

TVS Array Size = 256Kb

VLRS=2/3×VHRS

30

40

Curr

en

EC

S

VLRS=2/3×VHRSIHRS=0.1×ILRS

30

20LRS

C

20

10

IL

10.6 1 1.5 2 2.5 3.0

VHRS [V]0.6 1 1.5 2 2.5 3.0

Fig. 14 At constant array size (256Kb), NVM switching voltage supportedtrades-off against switching current. D-ADs follow their DC IV – linear seg-ments are limited by series resistance: current trades-off in proportion to volt-age, exponential segments indicate large increases in supported current forsmall reduction in voltage.

50] 50

40nt

[uA]

Array Size = 1MbVLRS=2/3×VHRS

30

40

Curr

en MIE

VLRS=2/3×VHRSIHRS=0.1×ILRS

30

20LRS

C

EC

20

10

IL

1CTS0 6 1 1 5 2 2 5 3 0

VHRS [V]0.6 1 1.5 2 2.5 3.0

Fig. 15 1mW contours for Write power showing range of Voltages and Currentssupported for an array size of 1Mb. MIEC ADs can support large arrays at highcurrents and moderate switching voltage. NPN can support large switchingvoltage at extremely low currents.

50] 50

40nt

[uA] Array Size = 1Mb

VLRS=2/3×VHRSIHRS 0 1×ILRS

30

40Cu

rren IHRS=0.1×ILRS

30

20LRS

C

20

10

IL

10.6 1 1.5 2 2.5 3.0

CTS

0.6 1 1.5 2 2.5 3.0VHRS [V]

Fig. 16 Voltage-current design space at 1Mb for a composite series stack oftwo diode-like ADs: Significant gains are seen for MIEC, with a doubling inNVM switching voltage supported at 1Mb array size. Diminished gains forother D-ADs, given doubling in already large slope and series resistance values.

50] 50

40nt

[uA]

30

40

Curr

en Constrained only by NVM conditions if30

20LRS

C Constrained by AD transition

conditions iftAD << tNVM

20

10

IL

10 6 1 1 5 2 2 5 3 0

Constrained by NVM conditions

VHRS [V]

0.6 1 1.5 2 2.5 3.0

Fig. 17 At currents>10uA, power consumption of TVS+1R arrays is con-strained by T-AD threshold point. If AD switching time is much less than NVMswitching time, instantaneous power to switch AD can be ignored and largerNVM voltages (2V for 1Mb arrays) supported.

support a much wider range of NVM V and I (2V at 1Mb in Fig.17).These gains are enabled by low Vh – negligible VAD implies VSW

and consequently, power can be low. TVS design space can alsobe expanded if Ith can be reduced (thereby reducing NVM voltageat Ith) while maintaining Vth (Fig.18).

ADs were also compared against low-current, non-linear, ‘self-select’ RRAM [8]. While series AD increases VSW , this can beoffset by improved leakage mitigation on partial select cells – e.g.in Fig.19 MIEC, NPN show >4× improved array size for the samepower, CTS shows degradation and TVS has little impact.

ConclusionsAD suitability was shown to be dependent upon AD, NVM and

circuit parameters. MIEC ADs were shown to be the best choicefor NVMs with low-to-moderate switching voltages. NPN ADs are

50] 50

40nt

[uA]

30

40

Curr

en

30

20LRS

C

0.2X

0.1X

20

10

IL 0

10 6 1 1 5 2 2 5 3 0

VHRS [V]

0.6 1 1.5 2 2.5 3.0

Fig. 18 TVS design space can also be expanded if threshold current canbe reduced while maintaining threshold voltage. This considerably reducesvoltage across NVM at AD threshold, thereby reducing total crosspoint voltageneeded (refer Fig.6).

1mW

erPo

we

100uW

10uW4Kb 16Kb 64Kb 256Kb 4Mb 16Mb1MbArray Size

4Kb 16Kb 64Kb 256Kb 4Mb 16Mb1Mb

Fig. 19 Integrating D-ADs with low ON-current, high non-linearity NVMs [8]can enable ≥ 4× increase in array size vs. a selector-less array. TVS devicesdo not show any benefit with this NVM, as switching threshold of the AD ishigher than the NVM.

most suitable for larger switching voltages and low currents<5uA –MIEC, TVS, Varistor can support low-current/high voltage NVMsif supplemented by NVM non-linearity. Table 3 summarizes thedesign space. Table 4 identifies key parameters to be improved forthe ADs studied.

256Kb 512Kb 1Mb 2Mb

Low V, Low I

All, CTS<5uA

All, CTS<5uA

All except CTS

MIEC, NPN, Varistor(MaSiM(MaSiM, TVS@1uA)

Low V TVS MIEC TVS MIEC TVS MIEC MIECLow V, High I

TVS, MIEC, Varistor

TVS, MIECVaristor

TVS, MIEC MIEC

High V All@1uA All@1uA NPN<5uA NPN@1uAHigh V, Low I

All@1uA,NPN@5uA

All@1uA,NPN@5uA

NPN<5uA, others+ non‐linear

NPN@1uA, MIEC, Varistor non‐non linear 

NVMVaristor nonlinear NVM

High V, None None None NoneHigh V,High I

None None None None

Table. 3 Design Space Summary

Diode Type ADsDiode‐Type ADsMaSiM Voltage Margin, SlopeMIEC Voltage MarginNPN Slope, Series ResistanceS ope, Se es es sta ceVaristor Slope

Th h ld ADThreshold ADsCTS Low‐bias leakage, IthTVS Ith

Table. 4 AD improvements to expand supported design space

References[1] K. Virwani et al., IEDM Tech. Digest, 2.7 (2012).[2] P. Narayanan et al., DRC, V.A-5 (2014).[3] L. Zhang et al., IEEE EDL, 35(2) 2014).[4] C-H. Ho et al. IEDM Tech. Digest, 2.8 (2012).[5] J. Woo et al. VLSI Tech. Digest, 12-4 (2013).[6] M-J. Lee et al. IEDM Tech. Digest, 2.6 (2012).[7] V.S.S. Srinivasan et al. IEEE EDL, 33(10) (2012).[8] S-G. Park et al., IEDM Tech. Digest, 20.8 (2012).[9] ITRS Interconnect Tables (2011).