P-204L: Late-News Poster: Analysis of Statistical Time Lags Based on Wall Charges ...pde.knu.ac.kr/publication/analysis of statistical time... · 2018-01-03 · Method for Full-HD

P-204L / H. D. Park

P-204L: Late-News Poster: Analysis of Statistical Time Lags Based on Wall Charges Prior to Address Discharge Using Vt Close-Curve

Method for Full-HD AC-PDP Hyung Dal Park, Jae Young Kim, and Heung-Sik Tae

School of Electronic and Electrical Engineering and Computer Science, Kyungpook National University, Daegu 702-701, Korea

Abstract The high speed address is an important parameter to lower cost technology for the realization of full HD-PDP. The wall charge supplied from the reset period is an important factor for affecting the fast and stable discharge characteristics during an address period. It is found that as the voltage level of the negative falling ramp in the reset waveform is lower, the accumulated wall charges during the ramp-up period are more erased, thus reducing the amounts of wall charges prior to address discharge. The resultant changes in the address discharge characteristics were examined in the 42-in. ac-PDP with a high Xe (11 %) content. In particular, the measured Vt close-curves and corresponding IR emission profiles show that less amounts of wall charges prior to an address discharge induce the decrease in the statistical time lag and total address discharge time lag in address period, thereby resulting in the stable and fast addressing. Therefore, it is advantageous to use the electric field from the applied voltage during an address discharge instead of utilizing the wall charges from the reset period for the stable and fast addressing. 1. Introduction The high speed address is still essential for the low cost key technology for the realization of full HD-PDPs. The use of a wall voltage induced by the wall charges accumulating among the three electrodes is the most important factor for the stable driving of ac-PDPs with millions of micro-discharge cells. The stable address discharge especially under a high speed address procedure strongly depends on the wall charge states accumulating among the three electrodes prior to an initiation of address discharge. In this sense, the effects of various wall charges states prior to the address discharge on the high speed address discharge needs to be investigated intensively [1, 2, 3]. In this paper, the relation between the statistical address discharge time lags and the amount of wall charges prior to an address discharge is examined using the Vt close-curve method [1, 4]. Furthermore, the following point is investigated carefully in the viewpoint of a high speed address for the full HD-PDPs; which is more favorable for a high speed address, the address discharge utilizing the wall voltage induced by the wall charges, or the address discharge utilizing the applied voltage without wall charges.

2. Experiments 2.1 Experimental Setup The test panel used in this work was a commercial 42-in. AC-PDP with a box-type barrier rib. The gas mixture and pressure of test panel were Ne-He-Xe (11%) and 420 Torr, respectively. Fig. 1 (a) and (b) show the schematic diagrams of the driving waveforms employed in the current study. In Fig. 1, Vnf, Vsl, Vx, and Va are defined as the negative falling ramp voltage (Vnf), scan low

(a) Case A

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Figure 1. Schematic diagrams of driving waveforms used in this study.

Table 1: Various voltage levels in Fig. 1

voltage (Vsl), X-bias voltage (Vx), and address voltage (Va), respectively. In case A of Fig. 1 (a), the negative falling ramp voltage levels (Vnf) are decreased to the four voltage levels: -85 V (case 1), -115V (case2), -165V (case 3), and -195 V (case 4), whereas the related X-bias voltage level (Vx) is fixed at 110 V. in case A, the voltage difference, ΔVXY = Vx - Vnf is increased for the four cases, 1, 2, 3, and 4. In case B of Fig. 2 (b), the negative

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P-204L / H. D. Park

falling ramp voltage levels (Vnf) are decreased to the four voltage levels: -85 V (case 1), -115V (case2), -165V (case 3), and -195 V (case 4), and the related X-bias voltage levels (Vx) are also simultaneously decreased to the four voltage levels: 190 V (case 1), 160 V (case 2), 110V (case 3), and 80 V (case 4), thus resulting in the same voltage difference between the X and Y electrodes of 275V (ΔVXY=Vx - Vnf). Moreover, the scan low voltage (Vsl) applied to the Y electrode during an address-period is equal to the negative falling ramp voltage (Vnf) applied during the ramp-falling period. The address voltage (Va) is fixed at 80 V, whereas the scan pulse width is 1.2 μs. The detailed voltage levels in Fig. 1 are listed in Table 1.

2.2 Wall Voltage Measurement using Vt Close-Curve

Figs. 2 (a) and (b) show the IR emission during a ramp-falling period for two cases A and B. As shown in Figs. 2 (a) and (b), as the negative falling ramp (Vnf) decreases from -85 V (case 1) to -195 V (case 4), the amount of the IR emission increases, implying the increase in the erased wall charges accumulating on the A and Y electrodes during the ramp-up period. Figs. 3 (a) and (b) show the shifts of Vt close-curves measured at the endpoint of the reset-period in the applied voltage plane of Vt close-curve in the case of adopting the driving waveforms (a) in case A where the negative falling ramp voltage level (Vnf) is variable and the X-bias voltage level (Vx) is fixed at 110V (ΔVXY = 195, 225, 275, and 305V) and

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Figure 3. Shifts of Vt close-curves measured at endpoint of reset period in case of adopting driving waveforms (a) in case A where Vnf is variable but Vx is fixed at 110V and (b) in case B where both Vnf and Vx are variable. References in Figs. 3 (a) and (b) represent Vt close-curve measured in cells with no wall charges. Table 2: Wall voltage differences of three electrodes after reset period for cases A and B.

(b) in case B where both Vnf and Vx are variable (ΔVXY = 275). As shown in Fig. 3 (a), the Vt close-curve is shifted to the right-upward direction because Vnf decreases but Vx is fixed. On the other hand, in Fig. 3 (b) the Vt close-curve is shifted simply to the upward direction because the voltage difference between the X and Y electrodes remains constant. The wall voltage difference among the three electrodes calculated based on the data of the Vt close-curves in Fig. 3 are listed in Table 2. As shown in Table 2, as the negative falling ramp voltage, Vnf decreases, the corresponding wall voltage difference between the A and Y

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(a) case A (b) case B

Figure 4. Schematic diagram of wall charge distribution among three electrodes based on data of Vt close-curves in Figure 3. electrodes, VWAY decreases linearly. Fig. 4 shows the schematic diagram of the wall charge distribution among the three electrodes based on the data of the measured Vt close-curve in Fig. 3.

3. Experimental Results and Discussion Figs. 5 (a) and (b) show the address discharge in the case of applying the various voltages, Vx, Vsl, and Va shown in the Vt close-curves in Fig. 3 for the two cases (a) A and (b) B. The different wall voltage conditions prior to an address discharge result in the different applied voltage conditions to produce an address discharge: in case A, Vsl = - 85 V for case 1, Vsl = -115V for case 2, Vsl = - 165 V for case 3, Vsl = - 195 V for case 4 ,Vx and Va are fixed at 110 and 80V, respectively, and in case B, Vsl = - 85 V (Vx=190V) for case 1, Vsl = - 115 V (Vx=160V) for case 2, Vsl = -165 V (Vx=110V) for case 3, Vsl = - 195 V (Vx=80V) for case 4. In Figs 4. (a) and (b), as the wall charges are more erased, the Vt close-curves are moved to the right and upward direction, meaning that the lower scan low voltage, Vsl can be applied during an address discharge. The cell voltage, VCAY between the A and Y electrodes is a sum of the wall voltage ΔVWAY between the A and Y electrodes and the applied voltage, Vsl +Va, between the A and Y electrodes. That is, VCAY = ΔVWAY + Vsl + Va. For two cases A and B, the detailed voltage values are listed in Table 3 [1]. As shown in Table 3, for case A, the cell voltages applied to the A and Y electrodes, VCAY are 274 V for cases 1 and 2, and 269 V for cases 3 and 4. For case B, the cell voltages applied to the A and Y electrodes, VCAY are 270 V for cases 1 and 2, and 269 V for case 3 and 270 V for case 4. For the cell voltage in cases 1 and 2 in both cases A and B, the portion of wall voltages is larger, whereas for the cell voltage in cases 3 and 4 in both cases A and B, the portion of the applied voltage is larger. Fig. 6 shows IR emission profiles during an address discharge for two cases A and B. The IR emission profiles in Fig. 6 show the overlapped image measured repeatedly 512 times, thus the temporal dispersion of the addressing discharge can be observed easily. The IR emission profiles have different shapes with wall charge states, as shown in cases 1, 2, 3 and 4 of Fig. 6. The IR emission profiles in cases 1 and 2 show the more dispersive

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Figure 5. Address discharge in case of applying voltages, Vx, Vsl, and Va shown in Vt close-curves in Fig. 3 for two cases (a) A and (b) B. Table 3: Detailed values of applied voltages, wall voltages and cell voltages for case A and B.

patterns than those in cases 3 and 4. Since the less dispersive IR emission guarantees the successful addressing, the address discharge utilizing the applied voltage during an application of the scan pulse instead of using the wall voltage induced by the reset discharge is favorable for the stable and high speed address. The address discharge time lags are measured from the infrared emission, which is detected by the photo-multiplier tube (PMT) in the same subfield. The address discharge time lag is defined as a time-period from the time when the scan pulse voltage falls to ten percent of its maximum to the time when the emission signal reaches the ninety-nine percent of the peak, which is measured by

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Figure 6. IR emission profiles during address discharge for two cases A and B at scan pulse of 1.2μs.

using an oscilloscope. The address discharge time lag is measured 500 times in the same experimental conditions and then, the resulting data are treated statistically. The formative time lag (Tf) is defined by the time required to build up the discharge through the avalanche process from the end of initiatory lag, and the statistical time lag (Ts) is defined by the time elapsed between the instant of an application of external voltage and the arrival of initial seed electrons in the gap, respectively [2]. Fig. 7 shows the address discharge probability of the cases A and B and the resultant address discharge time lags relative to the negative falling ramp voltage (Vnf). As shown in Fig. 7, with a decrease in Vnf, the statistical discharge time lag decreases but the formative discharge time lag increases very slightly. In case A, as the Vnf decreases, Tf increases by about 50 ns and Ts decreases by about 200 ns. The resultant total address discharge time lag (Td=Tf+Ts) in case A decrease by about 150 ns. Similarly, in case B, with a decrease in Vnf, the Tf increases by about 65ns and the Ts decreases by about 220 ns. The resultant total address discharge time lag decreases by about 155 ns. This result means that the smaller the portion of the wall voltage in the cell voltage is, the shorter the statistical time lag is. Therefore, it is advantageous to use the electric field from the applied voltage during an address discharge instead of utilizing the wall charges from the reset period for the stable and fast addressing.

4. Conclusions The address discharge characteristics strongly depend on the wall charges that have been accumulated from reset period. The analysis of Vt close-curve and monitoring of the corresponding IR emission show that the less amounts of wall charges prior to an

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Figure 7. Address discharge probability of case A (a) and case B (b) and Address discharge delay time lags (c) during address period.

address discharge induce the decrease of the statistical time lag and total address discharge time lag in an address period, resulting in a stable and fast addressing. To obtain a stable and fast address discharge, there is an advantage to use the electric field from the applied voltage than to use the wall charge from reset period in address discharge.

5. References [1] K. Sakita, K. Takayama, K. Awamoto, and Y. Hashimoto,

“High-speed Address Driving Waveform Analysis Using Wall Voltage Transfer Function for Three Terminals and Vt Close Curve in Three-Electrode Surface-Discharge AC-PDPs,” SID 01 Digest, pp.1022-1025 (2001).

[2] Jae Sung Kim, Jin Ho Yang, Tae Jun Kim, and Ki Woong Whang, “Comparison of Electric Field and Priming Particle Effects on Address Discharge Time Lag and Addressing Characteristics of High-Xe Content AC PDP,” IEEE Transactions on plasma science, Vol. 31, No. 5, pp.1083-1090, October 2003.

[3] Byung-Gwon Cho and Heung-Sik Tae, “A Study on Wall Charge Behavior of Single Sustain Waveform Based on Vt Close Curve Analysis in AC-PDP,” SID ’06 Digest, pp.52-55, 2006.

[4] H. Inoue, Y. Seo, K. Sakita, and Y. Hashimoto, “Numerical Analysis of Vt Close Curve for Non-Uniform Wall Charge Distribution in Three-Electrode AC-PDP,” EURO DISPLAY ’02 Digest, pp.931-934, 2002.

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