-
A T L A S P i x e l s T E M I C V i s i t , J a n 2 0 0 0
K. Einsweiler Lawrence Berkeley National LabATLAS Pixel
Electronics, Jan 28, 2000 1 of 14
Overview of the ATLAS Pixel Electronics
K. Einsweiler, LBNL
Goal: provide an overview of pixel electronics. This talk will
be followed by two technical talks on the major pixel IC’s: the FE
chip and the MCC chip.
Module design concept•Components of the module
Electronics required•Front-end chips
•Module Controller chip
•Prototype Results
Scope and Schedule of Electronics Activities
-
A T L A S P i x e l s T E M I C V i s i t , J a n 2 0 0 0
ATLAS Pixel Electronics, Jan 28, 2000 2 of 14
kerling structure: and opto-link
46K pixels of size
K. Einsweiler Lawrence Berkeley National Lab
Basic Components of Pixel TracModules placed on a mechanical
support/coo
•Silicon sensor with 16 FE chips, controller chip, power
cable
•Each module has active area of 16.4x60.8mm and includes50µ x
400µ each.
-
A T L A S P i x e l s T E M I C V i s i t , J a n 2 0 0 0
ATLAS Pixel Electronics, Jan 28, 2000 3 of 14
mm active area. The trol via serial rial 40 Mbit/s data
by sending a LVL1 its the corresponding
out 800K transistors.
plements a silicon ata, also implements hip, with embedded
to module, data is re VCSELs, receivers ips with LVDS
n module. Flex power 1.5m) followed by onventional cables to
K. Einsweiler Lawrence Berkeley National Lab
FE Electronics ConceptsSystem Design:
•Pixel Array: FE chip of 7.4 x 11.0mm die size with 7.2 x
8.0chip includes 2880 pixel channels, internal analog bias
concommands, and complete zero-suppressed readout with seoutput.
The set of hits from a 25ns crossing is “requested” signal with the
correct latency, and the FE chip then transmdigital hits
autonomously. This is a full-custom chip with ab
•Module Controller: Collects data from 16 FE chips and imevent
builder. Performs basic integrity checks and formats dmodule level
command and control. This is a synthesized ccustom blocks and about
400K transistors.
•Opto-link: Multiplexed clock/control sent over 40 Mbit/s
linkreturned on one or two 80 Mbit/s data links. Transmitters aare
epitaxial Si PIN diodes. There are two small optolink chinterfaces
to support these functions.
•Power Distribution: Significant ceramic decoupling used otape
used to reach services patch-panels on cryostat wall (round cable
to later transition on back of calorimeter, then cUSA15 cavern
(total distance as large as 140m).
-
A T L A S P i x e l s T E M I C V i s i t , J a n 2 0 0 0
ATLAS Pixel Electronics, Jan 28, 2000 4 of 14
ments
ad (nominal ATLAS om sensors of up to e of about 2 years at
hits/pixel/crossing) at e an “in-time” or within 20ns of (about
200e) and low amplifier.
eam crossing. mp/discriminator, relative timing of
r budget of about E chip of about
required functions, esign compromises.
K. Einsweiler Lawrence Berkeley National Lab
Electronics Challenges and RequireMost difficult challenges are
in FE chips:
•Radiation Dose: Operate properly after total dose of 50 MR10
year dose). Also cope with expected leakage currents fr50nA per
pixel. For the B-layer, this corresponds to a lifetimdesign
luminosity.
•Low noise: Operate with low noise occupancy (below 10-6
thresholds of about 3Ke with good enough timewalk to havthreshold
of about 4Ke (hit appears at output of discriminatexpected time).
This requires a small threshold dispersion noise (about 300e), as
well as good peaking time in the pre
•High Speed: Associate all hits uniquely with a given 25ns
bContributions to this timing come from timewalk in the preadigital
timing on FE chip, clock distribution on module, anddifferent
modules.
•Low Power: Meet these specifications with an analog
powe40µW/channel and a total power budget for the complete
F250mW.
•Full Custom design with about 800K transistors to
integratelayout pushes rules to their limits, and still requires
circuit d
-
A T L A S P i x e l s T E M I C V i s i t , J a n 2 0 0 0
ATLAS Pixel Electronics, Jan 28, 2000 5 of 14
s built:
s in 97/98, producing pe (FE-A/FE-C).
sses (TEMIC DMILL rdness.
E-D), and are working planned in late 2000.
nd relatively linear stment.
r threshold vernier.
nd leading-edge plus TE.
buffers at the bottom hich they are flagged /TOT for each
hit.
K. Einsweiler Lawrence Berkeley National Lab
Front-end Electronics PrototypeSeveral generations of prototypes
have been
•First “proof of principle” chips were built in 96.
•First realistic prototypes were designed in two parallel
efforta rad-soft HP prototype (FE-B) and a rad-soft AMS prototy
•Prototypes of critical elements made in both rad-hard proceand
Honeywell SOI) to study performance and radiation ha
•Have just received first version of a complete DMILL chip (Fon
common design Honeywell chip (FE-H). Vendor choice
Features of final design:•Preamplifier provides excellent
leakage current tolerance a
time-over-threshold (TOT) behavior via feedback bias adju
•Discriminator is AC-coupled, and includes 3-bit trim DAC fo
•Readout architecture uses distributed 7-bit timestamp bus,
atrailing-edge latches in each pixel to define times of LE and
•Asynchronous data push architecture used to get data into of
the chip, where they are stored for the L1 latency, after wfor
readout or deleted. Chip transmits Trigger/Row/Column
-
A T L A S P i x e l s T E M I C V i s i t , J a n 2 0 0 0
ATLAS Pixel Electronics, Jan 28, 2000 6 of 14
K. Einsweiler Lawrence Berkeley National Lab
FE-D Chip under test:
-
A T L A S P i x e l s T E M I C V i s i t , J a n 2 0 0 0
ATLAS Pixel Electronics, Jan 28, 2000 7 of 14
K. Einsweiler Lawrence Berkeley National Lab
Details of Bottom of Chip:
-
A T L A S P i x e l s T E M I C V i s i t , J a n 2 0 0 0
ATLAS Pixel Electronics, Jan 28, 2000 8 of 14
Chip) single chips:
ispersions.
e-rad, and noise still and parallel noise
����&� +���
����&�!' ��
�/� )��
�!��
��������(���
K. Einsweiler Lawrence Berkeley National Lab
Lab Measurements (NOT with DMILLExamples of threshold and noise
behavior in
•Using individual Trim DACs, manage to achieve excellent d
•Measured noise is quite good, even for small-gap design
prremains acceptable after irradiation (reduced shaping timefrom
leakage current itself both increase noise).
σ &�!'(��
σ &� �)��
� ����������������
� ��������������
-
A T L A S P i x e l s T E M I C V i s i t , J a n 2 0 0 0
ATLAS Pixel Electronics, Jan 28, 2000 9 of 14
ts:�9����������
����������������������������
�������������������8�
K. Einsweiler Lawrence Berkeley National Lab
Examples of timing and charge measuremen�8����������
������
������������������
•Timing performance at large charge is excellent, and timewalk
is acceptable.
•Charge measurement is high quality, but requires individual
calibrations. Uniformity of internal calibration is good.
-
A T L A S P i x e l s T E M I C V i s i t , J a n 2 0 0 0
ATLAS Pixel Electronics, Jan 28, 2000 10 of 14
Issues:each 25 bits wide and cks.
ed from Verilog
chieve good packing pre- and post-rad, and establish the Chip
must perform time as there is no g goals are critical.
nsistors and a die
rovements underway error handling.
, known as MCC-D0. d decoder. The derstand the
K. Einsweiler Lawrence Berkeley National Lab
Module Controller Chip Prototypes and•Significant on-chip
buffering required on inputs (16 FIFO’s,
32 words deep). These are implemented as full-custom blo
•Complex control functions that must be efficiently
synthesizdescription using Synopsys.
•This requires a high quality standard cell library in order to
aand routing density. This library must be well-characterizedand it
must be possible to back-annotate routing parasiticsexpected
performance of the full design after final routing. event building
on 16 parallel 40Mbit/s input streams in realmechanism for flow
control on data from FE chips, so timin
•Prototype made in AMS 0.8µ process, using about 400K trasize of
about 80 mm2.
•All basic functions worked as expected. There are minor impin
the some of the algorithms used by the chip, particularly
•A partial-scale prototype was made in our recent DMILL runThis
included basic blocks such as the FIFO, and commanintention was to
test the DMILL standard cell library and unperformance of a
synthesized design after irradiation.
-
A T L A S P i x e l s T E M I C V i s i t , J a n 2 0 0 0
ATLAS Pixel Electronics, Jan 28, 2000 11 of 14
µ:
K. Einsweiler Lawrence Berkeley National Lab
Module Controller Chip prototype in AMS 0.8
-
A T L A S P i x e l s T E M I C V i s i t , J a n 2 0 0 0
ATLAS Pixel Electronics, Jan 28, 2000 12 of 14
electronics chip ial standard !)
nts and power.
K. Einsweiler Lawrence Berkeley National Lab
Module Issues:Major issue is interconnection:
•Connect 46K pixel implants on sensor to preamplifiers in
FEusing bump-bonding technology (50µ pitch is not commerc
•Connect 16 FE chips with MCC chip and optolink compone
-
A T L A S P i x e l s T E M I C V i s i t , J a n 2 0 0 0
ATLAS Pixel Electronics, Jan 28, 2000 13 of 14
mall-scale studies. oft electronics.
bare” modules with others as “MCM-D” ll.
K. Einsweiler Lawrence Berkeley National Lab
Module Prototyping:•Built many “single chip” devices using
smaller sensors for s
Some studies were done with irradiated sensors and rad-s
•Built about 10 modules with IZM solder bumps, several as
“interconnections on PC board, several as “Flex” modules, modules.
Some, but not all, of these modules work very we
-
A T L A S P i x e l s T E M I C V i s i t , J a n 2 0 0 0
LAS Pixel Electronics, Jan 28, 2000 14 of 14
te detector. This eps.
ly yields we know d, or approximately of this. About 100
pto-link IC’s.
to be able to meet us concern to us.
jor IC’s in the pixel sting these die since
ting, we have e fabrication r this meeting.
eks time, and a full onth evaluation y well.
2001. This would be ths or so.
IC/DMILL and S pixels.
K. Einsweiler Lawrence Berkeley National LabAT
Scope and Schedule of Project•Total of approximately 2200
modules are required for comple
corresponds to about 35K good FE die after all assembly st
•Assuming 38% fab yield (very optimistic), and other
assembabout, we estimate this requires 150K FE die to be
fabricate1200 wafers. Outer layers of system are about 1050
wafersadditional wafers would be needed for all of the MCC and
O
•We need to achieve about 28% yield for the DMILL FE chipsour
budget (based on frame contract), so yield is of enormo
•We submitted our first full-scale prototypes of each of the
maproject for fabrication by TEMIC in Aug. 99. We have been tethe
wafers returned in late October. Based on this initial
tesidentified several design problems, and we believe also
somproblems. Addressing these problems is our primary goal fo
•We plan to submit a second engineering run in about 4-6
weprototype and irradiation program is planned during a six
mperiod. These next chips must have high yield and work ver
•The next step would be a first “pre-production” run in
Springfollowed by the series production over the following 18
mon
•We are presently building full-scale prototypes with both
TEMHoneywell/SOI, in order to find the optimal solution for
ATLA
Heading1 - Overview of the ATLAS Pixel ElectronicsHeading1 -
Basic Components of Pixel TrackerHeading1 - FE Electronics
ConceptsHeading1 - Electronics Challenges and RequirementsHeading1
- Front-end Electronics PrototypesHeading1 - Lab Measurements (NOT
with DMILL Chip)Heading1 - Module Controller Chip Prototypes and
Issues:Heading1 - Module Issues:Heading1 - Module
Prototyping:Heading1 - Scope and Schedule of Project