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P1500 Architecture Task ForceSummary of Task Force Mission and Scope
Goals of IEEE P1500Goals of IEEE P1500Standardize a Core Test Architecture which:
1. Defines a core test interface between an embedded core and the system chip.
2. Facilitate test reuse for embedded cores through core access and isolationmechanisms, and provide testability for system chip interconnect and logic.
3. Facilitates core test interoperability, with plug-and-play protocols, in order toimprove the efficiency of test between core providers and core users.
Scope of IEEE P1500Scope of IEEE P15004 Standardize core test mechanisms, for core access and isolation, including
protocols and test mode control.
7 System Chip test access mechanism is defined by the system chip integrator.
7 The core test method is defined by the core provider – P1500 supports, andenables, various different methods (e.g., scan, BIST, Iddq, etc.).
q P1500 Wrapper Instruction Register (WIR) and Data Registers provide:l Serial Shift from WSI to WSO
l Parallel Update4 Updated output data held stable during shift operations from WSI to WSO4 Required for WIR to prevent Wrapper & Core Modes from toggling during WIR shift
l Parallel Capture4 Required for WBR to provide interconnect and UDL test capability4 Optional for WIR to provide capture of test control information, or for testing of WIR
P1500 Wrapper Boundary CellsOverview of Cell Modes
Cell Functional Input
q Cell Modes4 Normal: No Effect, core functions normally4 Inward Facing: Affects the core, test is directed towards core4 Outward Facing: Affects the core, test is directed outward from core4 Safe: Affects the core & ensures wrapper does not damage core or system (a
recommended mode)
WrapperCell
Model
Cell Test Output
Cell Test InputCell Functional Output
CFI CFO
CTI
CTO
Note: Inward and Outward Facing Test Modes Mirror one another
P1500 Wrapper Boundary CellsOverview of Cell Events
Cell Functional Input
q Cell Events4 Shift: Move data through shift path4 Capture: Sample data4 Apply: Moment when test data becomes active and effective4 Update: 1149.1-type Update4 Transfer: Move data from Update element to Shift path
To Define Instructions for the WIR;q To operate the wrapper to allow for internal and external
testing.lCORETEST and WEXTEST
q To operate the wrapper such that it provides a safe mode forthe core and if needed, the logic adjacent to the core (from theoutputs of the core).lSAFESTATE
q To operate the wrapper to allow for debug.lWSCORETEST, SCORETEST, CORETEST
q To operate the wrapper to allow IddQ measurements.lSCORETEST
WEXTEST allows testing of off-core logic and interconnect.
Rulesq WEXTEST Instruction Mandatoryq Wrapper Boundary Register accessed serially between WSI and WSOq Core in a Safe Modeq All signals driven out of the wrapper output terminals are defined by the
values held in the wrapper boundary registerq Wrapper input terminals load only during captureq 3-state output cell must be loaded with safe data by use of WPRELOAD
WBYPASS allows the Wrapper Boundary Register to bebypassed from WSI to WSO. This instruction alsoforces the core into its normal operation mode.
Rulesq WBYPASS instruction mandatoryq Wrapper Bypass Register accessed serially between WSI and WSOq Operation of test logic will not affect functional operationq All wrapper cells will perform their system functionq Wrapper input terminals load only during capturePermissionsq Binary code for the instruction may be defined by the user
WCLAMP clamps the state of the output terminals ofthe WBR and Selects the Bypass Register betweenWSI and WSO.
Rulesq WBYPASS Register selectedq Data on the output terminals defined by the WBRq Core in a safe modeq Parallel output states shall not changeq States on the inputs to the core shall not damage the core
Recommendationsq Core should be put in a quiet modePermissionsq Binary code for the instruction may be defined by the user
Same function as WCLAMP, but does not require use ofthe WPRELOAD instruction. Clamped values must besafe. Important enough for its own instruction.
Rulesq WBYPASS Register selectedq Data on output terminals driven by safe valuesq Core in a safe modeq Parallel output states shall not changeq States on the inputs to the core shall not damage the core
Recommendationsq Core should be put in a quiet modePermissionsq Binary code for the instruction may be defined by the user
WPRELOAD loads a Dedicated Shift Path in the WBR withdesired values, then Updates the Update Stage.
Rulesq If there is a dedicated shift path in the WBR, WPRELOAD is Mandatoryq Dedicated shift path is serial – connected between WSI and WSOq Shift does not affect the core or user-defined logicq Data will be loaded to the update stage during the update operationq States on the inputs to the core shall not damage the core
Recommendationsq Core should be put in a quiet modePermissionsq Binary code for the instruction may be defined by the user
CORETEST configures the Wrapper for Core TestingRulesq At least one CORETEST instruction is mandatoryq During CORETEST, no external logic or core shall be affected
Permissionsq Binary code for the instruction may be defined by the userq Any number of CORETEST instructions may be defined
P1500 InstructionsWSCORETEST Instruction (SIL) (In discussion)
WSCORETEST configures the Wrapper Serially forCore Testing
Rulesq WBR serial access is between WSI and WSOq Core must be capable of single-step operationq Core outputs are defined by the WBR during the Apply cycle onlyq All non-clock core input values are driven by the WBRq Core output data shall be loaded into the WBR before shifting the
WBR
Recommendationsq External Logic should not affect the input cells of the WBR
Permissionsq Binary code for the instruction may be defined by the user
Configures the Wrapper and Internal Scan ChainsSerially for Core TestingRulesRecommendationsPermissionsWill exactly follow the WSCORETEST Rules, but will attach theinternal serial scan chain as well.