Oversampling Analog to Digital Converters 21st International Conference on VLSI Design, Hyderabad Shanthi Pavan Nagendra Krishnapura Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India 4 January 2008 Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
226
Embed
Oversampling Analog to Digital Convertersnagendra/presentations/20080104vlsiconf/20080104vlsiconf.pdf · Oversampling Analog to Digital Converters 21st International Conference on
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Oversampling Analog to Digital Converters21st International Conference on VLSI Design, Hyderabad
Shanthi PavanNagendra Krishnapura
Department of Electrical EngineeringIndian Institute of Technology, Madras
Chennai, 600036, India
4 January 2008
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Outline
Introduction to sampling and quantizationQuantization noise spectral densityOversamplingNoise shaping-∆Σ modulation
High order multi bit ∆Σ modulators
Stability of ∆Σ A/D convertersImplementation of ∆Σ A/D converters
Loop filter designMulti bit quantizer designExcess delay compensationClock jitter effects
Mitigation of feedback DAC mismatchDynamic element matchingDAC calibration
Case study15 bit continuous-time ∆Σ ADC for digital audio
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Signal processing systems
DSP...0100011011...
Digital Processing
Interface Electronics
(A-D and D-A Conversion)
. . .
Sensor(s) Actuator(s)
. . .. . .
(Signal Conditioning)
Continuous-timeContinuous-amplitude
Discrete -timeDiscrete -amplitude
Continuous-timeContinuous-amplitude
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Signal processing systems
Natural world: continuous-time analog signals
Storage and processing: discrete-time digital signals
Data conversion circuits interface between the two
Wide variety of precision and speed
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Continuous time signals
Continuous−time analog signal
0T
s2T
s3T
s4T
s5T
s6T
s7T
s8T
s9T
s10T
s
0
VLSB
2VLSB
3VLSB
4VLSB
5VLSB
6VLSB
7VLSB
Signals defined for all t
Signals can take any value in a given range
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Discrete time signals
Discrete time signal
0 1 2 3 4 5 6 7 8 9 100
VLSB
2VLSB
3VLSB
4VLSB
5VLSB
6VLSB
7VLSB
Signals defined for discrete instants n
Signals can take any value in a given range
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Digital signals
Sampled quantized(digital) signal
0 1 2 3 4 5 6 7 8 9 100
VLSB
2VLSB
3VLSB
4VLSB
5VLSB
6VLSB
7VLSB
Signals defined for discrete instants n
Signals can take discrete values kVLSB
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Sampling and quantization
A segment of a continuous-time signal has an infinitenumber of points of infinite precision
Discretization of time (sampling) andamplitude (quantization) results in a finite number of pointsof finite precision
Sampling and quantization = Analog to digital conversion
Errors in the process?
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Signals in time and frequency domains
Continuous time signal xct(t)
Frequency domain representation using its Fouriertransform Xct(f )
Xct(f ) =
∫ ∞
−∞xct(t) exp(−j2πft)dt
Discrete time signal xd [n]
Frequency domain representation using its Fouriertransform Xd (ν)
Xd [ν] =∞
∑
n=−∞
xd [n] exp(−j2πνn)
Xd [ν] periodic with a period of 1
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Signals in time and frequency domains
Continuous−time analog signal
0T
s2T
s3T
s4T
s5T
s6T
s7T
s8T
s9T
s10T
s
0
VLSB
2VLSB
3VLSB
4VLSB
5VLSB
6VLSB
7VLSB
0
fb
fs
2fs
0
1.0
Fourier transform of a continuous−time signal
Xct(f ) =
∫ ∞
−∞xct(t) exp(−j2πft)dt
Signal bandwidth fb: |Xct(f )| = 0 for f > fb
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The maximum ADC input must be smaller than thequantizer range. (called the Maximum Stable Amplitude(MSA)).More “shaped” noise → More likelihood of instability.
More shaped noise → Lesser in-band noise.
An aggressive NTF will have a reduced MSA.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Estimating Maximum Stable Amplitude (MSA)
Simulation is the best way.Keep stepping up the input sinewave amplitude.
For every amplitude, compute in-band SNR.Beyond the MSA, the closed loop poles move out of theunit-circle.Noise shaping is lost ⇒ In-band SNR falls.Quantizer input tends to infinity.
Time consuming.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Estimating MSA Without Sinewave Inputs
Originally proposed by Lars Risbo.Put a slowly increasing ramp into the ADC.
Beyond the MSA, the closed loop poles move out of theunit-circle.Quantizer input tends to infinity very rapidly.The value of the ADC input when the quantizer input blowsup is the MSA.
Found (empirically) to result in an MSA close to thatpredicted by the sinewave method.
Much quicker than the sinewave technique.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Estimating MSA Without Sinewave Inputs
Lfs Vout
VDAC
t
Vin
Very Slow Ramp(0 to 1 over 1 second)
Vq
0
1
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Estimating MSA Without Sinewave Inputs
0 0.2 0.4 0.6 0.8 1−15
−10
−5
0
5
10
15
20
ADC Input
log(
Qua
ntiz
er In
put)
MSA
log(Quantizer Input) versus ADC InputMSA is about 90% of the quantizer range
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
MSA vs OBG for a Third Order NTF
2 3 4 5 6 7 80.4
0.5
0.6
0.7
0.8
0.9
Out of Band Gain
Max
imum
Sta
ble
Am
plitu
de
4−bit quantizer
3−bit quantizer
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
A Systematic NTF Design Procedure
NTFs of the form (1 − z−1)N have stability problems.
Why ?
The OBG is too high (2N ).
This saturates the quantizer even for small inputs, causinginstability.
The MSA is small.
Worse for low quantizer resolutions.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
A Systematic NTF Design Procedure Solution
Introduce poles into the NTF.
NTF (z) =(1 − z−1)N
D(z−1).
Recall that NTF (∞) = 1.
⇒ D(z = ∞) = 1.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Why do poles help ?
0 0.2 0.4 0.6 0.8 10
1
2
3
4
5
6
7
8
ω/π
|NT
F|
Properly chosen poles reduce OBG of the NTF, enhancingstability.
However, stability comes at the expense of increasedin-band noise.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
A Systematic NTF Design Procedure
Commonly used pole positions : Butterworth, Chebyshev,Inv. Chebyshev etc.
Coefficients for these approximations readily gotten fromMATLAB.
Schreier’s Delta-Sigma Toolbox is an invaluable design aid.
One should understand what the toolbox does.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
A Systematic NTF Design Procedure
Choose the order of the NTF.OSR, number of levels (n) and desired SNR are known.
Example : Order = 3, OSR = 64, n = 16, SNR = 115 dB.
Basically, the NTF is a high-pass filter transfer function.Example : Choose a Butterworth Highpass.
Choose the 3 dB corner of the high pass filter -Example : ω3dB = π
8 .For a Butterworth NTF, specifying the cutoff specifies thecomplete transfer function.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
A Systematic NTF Design ProcedureGet the transfer function from MATLAB
[b,a]=butter(3,1/8,’high’)
H(z) =0.6735 − 2.0204z−1 + 2.0204z−2 − 0.6735z−3
1 − 2.2192z−1 + 1.7151z−2 − 0.4535z−3
MATLAB sets |H(ejπ)| = 1.
Recall that for H(z) to be a valid NTF, H(∞) = 1.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
A Systematic NTF Design ProcedureScale H(z) by 1
0.6735 to obtain NTF (z).
NTF (z) =(1 − 3z−1 + 3z−2 − z−3)
1 − 2.2192z−1 + 1.7151z−2 − 0.4535z−3
0 0.2 0.4 0.6 0.8 10
0.5
1
1.5
ω/π
|H| H
NTF
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
A Systematic NTF Design Procedure
Find loop filter using 11+L(z) = NTF (z).
Simulate the equations describing the modulator.Compute the peak SNR.
In our example, we obtain SNR=102 dB after simulation.MSA = 0.85.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
A Systematic NTF Design ProcedureIf SNR is not enough, repeat the entire procedure abovewith a higher cutoff frequency for the Butterworth high passfilter.
This will increase the OBG (intuition on this later).The MSA will reduce.
If SNR is too high, repeat the entire procedure above with alower cutoff frequency for the Butterworth high pass filter.
This will decrease the OBG (intuition on this later).The MSA will increase.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
A Systematic NTF Design Procedure
SNR obtained with 3 dB cutoff of π8 is inadequate.
So, we increase the cutoff frequency to π4 .
The peak SNR is around 116 dB.
OBG = 2.25, MSA = 0.8.
We are done.
This iterative process is coded into synthesizeNTF inSchreier’s toolbox.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
A Systematic NTF Design Procedure : RemarksButterworth is one of several candidate high pass filters.
All the zeros of transmission are at the origin.
Another useful family is the inverse Chebyshevapproximation.
Has complex zeros (on the unit circle).
0 0.01 0.02 0.03 0.04−140
−120
−100
−80
−60
−40
ω/π
|NT
F|
Inverse Chebyshev
Butterworth
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Sensitivity of a Feedback Loop
L(z) +
E(z)
+-
Xin(z) V(z)
E is a disturbance injected into the feedback loop.
V (z) = X (z) L(z)1+L(z) + E(z) 1
1+L(z) .
If L(z) = ∞, V (z) = X (z).
The loop rejects E(z), or the loop is insensitive to E(z).
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Sensitivity of a Feedback Loop
L(z) +
E(z)
+-
Xin(z) V(z)
L(z) cannot be ∞ at all frequencies.
V (z) = X (z) L(z)1+L(z) + E(z) 1
1+L(z) .
The loop rejects E at frequencies where the loop gain ishigh.
How effectively this is done is called the sensitivity function.
Sensitivity is 11+L(ejω)
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Sensitivity of a Feedback Loop
In a ∆Σ loop, sensitivity is the same as the NTF.
Recall : The first sample of the NTF impulse response is 1.
Equivalent to NTF (∞) = 1
The NTF can be written as (1+a1z−1)(1+a2z−1+a3z−2)···(1+b1z−1)(1+b2z−1+b3z−3)···
Poles must be within the unit circle (for a stable loop).
The zeroes are on the unit circle (or inside).
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Sensitivity of a Feedback Loop
It can be shown that∫ π
0log(|1 + a1e−jω|) dω = 0, if
|a1| ≤ 1.
0 0.2 0.4 0.6 0.8 1−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
ω/π
log(
|1 +
aejω
| C1
C2
The area above the 0 dB in the log magnitude plot is equal tothe area below the 0 dB line.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Sensitivity of a Feedback Loop∫ π
0log(|1 + a2e−jω + a3e−j2ω|) dω = 0
if the roots of 1 + a2z−1 + a3z−2 lie within (or on) the unitcircle.
Straightforward to derive, if one accepts the previous result.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Bode Sensitivity Integral∫ π
0log |NTF (ejω)|dω = 0
The Integral of the Log Magnitude of an NTF is 0
0 0.2 0.4 0.6 0.8 1−70
−60
−50
−40
−30
−20
−10
0
10
20
ω/π
10 lo
g |N
TF
|
C1
C2
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Bode Sensitivity Integral
0 0.2 0.4 0.6 0.8 1−70
−60
−50
−40
−30
−20
−10
0
10
20
ω/π
20 lo
g |N
TF
|
Good inband performance at the expense of poorout-of-band performance .
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Bode Sensitivity Integral
0 0.2 0.4 0.6 0.8 1−70
−60
−50
−40
−30
−20
−10
0
10
20
ω/π
20 lo
g |N
TF
|
Complex zeros better than choosing all NTF zeros at theorigin.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Bode Sensitivity Integral
0 0.05 0.1 0.15 0.2 0.25 0.3−70
−60
−50
−40
−30
−20
−10
0
10
ω/π
20 lo
g |N
TF
|
Complex zeros better than choosing all NTF zeros at theorigin.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Bode Sensitivity Integral
0 0.2 0.4 0.6 0.8 1−70
−60
−50
−40
−30
−20
−10
0
10
20
ω/π
20 lo
g |N
TF
|
Higher order ⇒ less in-band noise.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Loop Filter Architectures
1z-1
1z-1
+k1
k2
-+U Y V
Remember : A quantizer = ADC + DAC.
Needs ONE DAC.
Loop filter gain goes to infinity at DC, with order 2.
Both NTF zeros at DC (z = 1).
Called CIFF (Cascade of Integrators Feed Forward)
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Loop Filter Architectures
1z-1
1z-1
+k1
k2/k1
- -U +
Remember : A quantizer = ADC + DAC.
Needs TWO DACs.
Loop filter gain goes to infinity at DC, with order 2.
Both NTF zeros at DC (z = 1).
Called CIFB (Cascade of Integrators Feed Back).
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Loop Filter Architectures
1z-1
1z-1
+k1
k2
-+U Y V
-γ
CIFF loop with complex zeros.
NTF zeros are at 1 ± j√
γ.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Loop Filter Architectures
1z-1
1z-1
+k1
k2/k1
- -U +
γ
-
CIFB loop with complex zeros.
NTF zeros are at 1 ± j√
γ.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Loop Filter Implementation
Traditionally done in discrete-time.
Implemented using switched-capacitor techniques.Switched capacitor circuits have several advantages.
Exact nature of settling is irrelevant, only the settled valuematters.Pole-zero locations of the loop filter are set by capacitorratios, which are exteremely accurate.Insensitive to clock jitter, as long as complete settlingoccurs.Easier to simulate.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Loop Filter Implementation Switched capacitor loop filters havedisadvantages too -
Difficult to drive from external sources due to the largespike currents drawn.
Upfront sampling : requires an anti-alias filter.
Integrator opamps consume more power thancontinuous-time counterparts.
Require large capacitors to lower kT/C noise.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Continuous-time Loop Filters
Vout [n]Vin (t)
Vdac(t)
-Σ
DAC
L(s) ADC
What is the NTF ?
How does one design such a loop ?
How does this compare with a discrete-time loop filter ?
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
DAC Modeling
DACn t
In Out
In Out
t
Out
NRZ DAC RZ DAC
The input to the DAC is a digital code ak that changesevery Ts.
The DAC output is an analog waveform.
Output =∑
k akp(t − kTs)
p(t) is called the pulse-shape.
Commonly used shapes are the Non-Return to Zero (NRZ)and Return-to-Zero (RZ) pulses.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Loop Modeling
Vout [n]
Vdac(t)
-
DAC
L(s) ADC
Vdac(t)
-L(s)
p(t)
e[n]
Ts
1NRZ DAC
Set input to zero.
Replace ADC-DAC with quantization noise e(n).
DAC is modeled as a filter with impulse response p(t).
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Loop Modeling
Vdac(t)
-L(s)
p(t)
e[n]
Ts
1NRZ DAC
L(s)p(t)p(t)*l(t)
kTs
l[n] =Break the loop after the sampler.
Apply a discrete time impulse.
What comes back is l[n] = p(t) ∗ l(t)|kTs .
The z-transform of l[n] is the equivalent discrete time loopfilter.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
A First Order Example
1s +
e(n)
+Ts= 1
Vin Vout
-
1
1
1
11s
t t
Discrete-time equivalent impulse response of the loop filter0, 1, 1, 1, 1 · · ·L(z) = z−1
1−z−1
NTF (z) = 11+L(z) = 1 − z−1
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
A Second Order Example
L(z) =(k1 + 0.5k2)z−1 + (−k1 + 0.5k2)z−2
(1 − z−1)2 .
To achieve NTF (z) = (1 − z−1)2, we need
L(z) =2z−1 − z−2
(1 − z−1)2 .
⇒ k1 = 1.5, k2 = 1.
Vout [n]Vin (t)
Vdac(t)
-
DAC
ADC1s
1s +
1.5
1Ts=1
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Continuous-time Sigma-Delta Summary
It is possible to “emulate” a D-T loop filter with a C-T one.
The equivalence depends on the DAC pulse shape.The technique can be extended to high order NTFs -
From the desired NTF (z), find L(z)Convert L(z) into L(s) using the DAC pulse shapeThe MATLAB command d2c will do it for you, for an NRZDAC.Implement L(s) using any one of the loop filter topologies.
A CT loop filter has several other advantages ... listen on.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Anti-Aliasing Feature of CT ∆Σ Modulators
Vout [n]Vin (t)
Vdac(t)
-Σ
DAC
L(s) ADC
Vout [n]Vin (t)
Vdac(t)
-Σ
DAC
L(s) ADC
L(s)
Move L(s) outside the loop
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Anti-Aliasing Feature of CT ∆Σ Modulators
Vout [n]
Vdac(t)
-Σ
DAC
ADC
L(s)
Vout [n]Vin (t)
Vdac(t)
-Σ
DAC
L(s) ADC
L(s)
Vin (t) L(s)
Move the sampler outside the loop
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Anti-Aliasing Feature of CT ∆Σ Modulators
Vout [n]Vin (t)
Vdac(t)
-Σ
DAC
L(s) ADC
L(s)
Vout [n]Vin (t)
-ΣL(s)
L(z)
e[n]
+
Replace the cascade of the DAC and L(s) by theequivalent discrete-time filter L(z).
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Anti-Aliasing Feature of CT ∆Σ Modulators
Vout [n]Vin (t) L(s) 1 + L(z)1
NTF(z)
Vout [n]Vin (t)
-ΣL(s)
L(z)
e[n]
+
NTF (z) = 1/(1 + L(z))
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Anti-Aliasing Feature of CT ∆Σ Modulators
Vout [n]Vin (t) L(s) 1 + L(z)1
NTF(z)
Consider a tone at frequency ∆f in the signal band.
Response to frequency ∆f is L(∆f )NTF (∆f ).
In a general ADC, a tone (∆f + fs) can alias as ∆f .
What about a CTDSM ?
Response to frequency (∆f + fs) is L(∆f + fs)NTF (∆f )
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
The Anti-Aliasing Feature of CT ∆Σ Modulators
|L|(dB)
Signal bandf∆f ∆f + fs
AliasRejection
Alias rejection is | L(∆f )L(∆f+fs)
|Implicit anti-aliasing without an explicit filter !
Valuable feature of CT Delta-Sigma modulators.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Effect of Time-Constant Variations in the Loop Filter
On-chip RC’s vary with process and temperature.
On an integrated circuit, ratios of like elements are tightlycontrolled.
We need to only worry only about quantities with“dimensions”.
What happens due to absolute variation of RC timeconstants ?
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Analog calibration
I0 Iout
φ φ φ
φφ
φ
Calibrate all current sources against a master source
Use M + 1 current sources and calibrate one at a time
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Calibration: summary
No additional components in the loop ⇒ no excess delay
Measuring DAC characteristics inline is challenging
Additional digital or analog complexity
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
References
Randomization: L. R. Carley, “A noise-shaping coder topology for 15+ bit converters,” IEEE Journal ofSolid-State Circuits, vol. 24, pp. 267 - 273, April 1989.
Data weighted averaging: R. T. Baird and T. S. Fiez, “Linearity enhancement of multibit δΣ A/D and D/Aconverters using data weighted averaging,” IEEE Transactions on circuits and systems-II, vol. 42, pp. 753 -762, December 1995.
Individual level averaging: B. H. Leung and S. Sutarja, “Multibit Σ-∆ A/D converter incorporating a novelclass of dynamic element matching techniques,” IEEE Transactions on circuits and systems-II, vol. 39, pp.35-51, January 1992.
Theoretical analysis: O. J. A. P. Nys and R. K. Henderson, “An analysis of dynamic element matchingtechniques in sigma-delta modulation,” Proceedings of the 1996 IEEE International symposium on circuitsand systems, vol. 1, pp. 231-234, May 1996.
Comparison through simulation: Zhimin Li, T. S. Fiez, “Dynamic element matching in low oversamplingdelta sigma ADCs,” Proceedings of the 2002 IEEE International symposium on circuits and systems, vol. 4,pp. 683-686, May 2002.
Digitally calibrated ∆Σ modulator: M. Sarhang-Nejad and G. C. Temes, “A high-resolution multibit Σ ∆ADC with digital correction and relaxed amplifier requirements,” IEEE Journal of Solid-State Circuits, vol.28, pp. 648 - 660, June 1993.
Analog calibrated DAC: D. Wouter J. Groeneveld et al., “A self-calibration technique for monolithichigh-resolution D/A converters,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 1517 - 1522, December1989.
Higher order mismatch shaping: R. Schreier and B. Zhang, “Noise-shaped multibit D/A convertoremploying unit elements” Electronics letters, vol. 31, No. 20, pp. 1712-1713, 28th September 1995.
Additional filtering of DEM errors: M. H. Adams and C. Toumazou, “A Novel Architecture for Reducingthe Sensitivity of Multibit Sigma-Delta ADCs to DAC Nonlinearity,” Proceedings of 1995 IEEE Internationalsymposium on circuits and systems, vol. 1, pp. 17-20, May 1995.
Additional filtering of DEM errors: J. Chen and Y. P. Xu, “A Novel Noise Shaping DAC for Multi-bitSigma-Delta Modulator,”IEEE Transactions on Circuits and Systems II-Express Briefs, vol. 53, no. 5, pp.344-348, May 2006.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
CASE STUDY
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
A 15-bit Continuous-time ∆Σ ADC for Digital Audio DesignTargets
Audio ADC (24 kHz Bandwidth)
15 bit resolution
OSR = 64 (fs = 3.072 MHz)
0.18µm CMOS process, 1.8 V supply
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Continuous-time versus Discrete-time A continuous-timeimplementation was chosen
Implicit anti-aliasing
Resistive input impedance
Low power dissipation
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Architectural Choices
Single-bit versus multibit quantization ?
Single loop versus MASH ?
NTF ?
Loop Filter Architecture ?
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Architecture : Single-bit vs Multibit
Single bit quantizer
Simple hardware
Gentle NTF
High jitter sensitivity
Metastability
Opamp slew rate
Multibit quantizer
Complex hardware
Aggressive NTF
Low jitter sensitivity
Metastability : no issue
Reduced slew rate
A 4-bit quantizer is used.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Architecture : Single Loop vs MASH
Matching of transfer functions are needed in a MASH design
More complicated
Might require calibration
A single loop design is chosen.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Architecture : Choice of the NTF
A maximally flat NTF is chosen
Small OBG
High in-bandquantization noise
Low jitter noise
Increased MaximumStable Amplitude (MSA)
Large OBG
Low in-bandquantization noise
High jitter noise
Reduced MaximumStable Amplitude (MSA)
An OBG of 2.5 is chosen as a compromise
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Effect Of OBG On Jitter And Quantization Noise
1.5 2 2.5 3 3.595
100
105
110
115
120
125
SN
R (
dB)
Out of Band Gain
Peak SQNR
Peak SJNR (100ps jitter)
Peak SJNR (50ps jitter)
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Effect Of Systematic RC Time Constant Variations On The NTF
0 0.1 0.2 0.3 0.4 0.50
0.5
1
1.5
2
2.5
3
3.5
4
4.5
ω/π
|NT
F(e
jω)|
Nominal
30 % Higher
30 % Lower
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
MSA And SQNR With Systematic RC Time Constant Variations
0.7 0.8 0.9 1 1.1 1.2 1.3 1.4105
110
115
120
125
130
Pea
k S
NR
(dB
)
0.7 0.8 0.9 1 1.1 1.2 1.3 1.4−1.6
−1.4
−1.2
−1
−0.8
−0.6
[RC]nom
/[RC]
Max
imum
Sta
ble
Am
plitu
de (
dBF
S)
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Simulated Output Bit Stream
100 200 300 400 500
−10
−5
0
5
10
n
Qua
ntiz
er O
utpu
t
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Feedfoward versus Distributed Feedback Loopfilters
ω1s
ω2s
ω3s-
+k1k2
k3
ω1s
ω2s
ω3s-
+- -
(a)
(b)
ω1= 2.67, ω2= 2.08, ω3= 0.059
ω1= 0.34, ω2= 0.71, ω3= 1.225
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Feedfoward versus Distributed Feedback Loopfilters
Feedforward
First integrator is fasest.
Third integrator isslowest.
First opamp is powerhungry (for noisereasons).
Third opamp is lowpower (slowestintegrator).
Small capacitor area.
Distributed Feedback
Third integrator isfastest.
First integrator isslowest.
First opamp is powerhungry (for noise).
Third opamp is powerhungry (fastestintegrator).
Large capacitor area.
A feedforward loop filter is used.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Loop Filter
+
-+-
+
-+-
+
-+-
+
-+-
idacp
idacm
R1
C1
vom1
vop1
R2
C2
R3
C3
vip
vim
vop2
vom2
vom3
vop3
RfR11
R21
R31
vop1
vop2
vop3
vom1
vom2
vom3 vop
vom
A1 A2
A2
Cs
100K 400K 500K
1.05346pF 730fF 8.6264pF
R11 = 337 K
R21 = 506 K
R31 = 112 K
Rf = 200K
Cs = 172fF
A2
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Excess Delay Compensation : Conventional
−
+
−
+
Rest of Loop Filter
. . . .
DAC1
DAC2
Vi
Excess DelayCompensation
Ri
C1
Rf
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Excess Delay Compensation : Proposed
−
+
−
+
Rest of Loop Filter
. . . .
DAC1
Vi
Cx
Ri
C1
Rf
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
First Opampvdda
gnda
vip vim
o1mo1p
vom
Vtail
cmfbn1
biasn2
Rz
Cc M1
M2
M3
M4
M5
M6
M7
M8
M9
vdda
(a)
M61
M11 M51
M31
M21
M81
M71M41
vop
1.5IQ 1.5IQ
IQIQ
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Second Opamp
M1
M2
M3
M4 M5
M6
M7
M8
M9
M10
M11
Rz
Cc
vdda
gnda
Vip Vim
Vcmfb
Vbiasp
Vbiasp
v1m vop vomv1p
v1m v1m v1p v1p
Vcm
Vtail
Vcmref
v1p
v1m
M11
M16
M17
Cc2
M3
M4
Vbiasp
Cc2
Vcmfb
Second StageFirst Stage
Vtail
CMFB
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Flash ADC Block Diagram
ipim
ipim
. . . .
Vtop
Vtop
Vbot
Vbot
. . . .
. . . .
Vref<15>
Vref<0>
Vref<15>
Vref<0> d<15>
db<15>
d<0>
db<0>
4-bit data
to DEM/DAC
(ADC output)
DIG
ITA
L BA
CK
EN
D
15
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Comparator
ip
Vrefp Vcm
im
Vrefm Vcm
Cb
Vdda
gnda
Lb
L
LC
LC
LC
LC
LaL
LR
C2MOS
Ld
L
L La
op
om
M1 M4
M2 M3
, La
LC
LR
Ld
(a)
(b)
Td
Cb
XY
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Effect of Random Offset in the Comparators
0 0.1 0.2 0.3 0.495
100
105
110
115
120
125
σoffset
(in LSB)
SN
R (
dB)
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Digital Backend
Therm. to Binary
Converter
in<0:14>
A<0:3>
4 - Bit Adder
B<0:3>
S<0:3>
Cout
Ci n
Barrel ShifterFLASH
O/P(
) DAC_in<0:14>
Latch<0:14>
( DAC I/P )
dem_clkd
EN
15 15
4
4
4
15
D Q
D Q
+4
dem_clk
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Unit DAC Resistor
Vrefp1.6 MΩ
Vrefm1.6 MΩ
dacp
dacm
To input terminalsof first opamp
From ReferenceGenerator
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Reference Generation Circuitry
−
+
+
-
gnd
vdd
I
I
R
R
Vdda
gnd
Vrefp
Vrefm
C1 Cext
(Vrefp - Vcm)(15/R)
(Vcm - Vrefm)(15/R)
Rx
Rx
(b)
−
+
Vref
R1
Vdda
gnd
I
I(a)
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Test Setup and Die Layout
LOOP FILTER
REFERENCES
FLASH ADC/DEM/DAC
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Test Setup Schematic
Σ∆ Converter4 bits
Vip
Vim
Vrefp Vrefm1 µF
VddIbias
500 nA
Clock
Vcmref
0.1 nF0.9 V
(3.072 MHz)
To Logic Analyzer
DifferentialAudioSource
Vcm
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Measured Dynamic Range
−100 −80 −60 −40 −20 0−20
0
20
40
60
80
100
Input Power (dB FS)
SN
R (
dB)
93.5 dB
SNR SNDR
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
In Band Spectrum
0 5 10 15 20
−100
−80
−60
−40
−20
0
Frequency (kHz)
PS
D (
dB)
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Out of Band Spectrum
100
101
102
−100
−80
−60
−40
−20
0
Frequency (kHz)
PS
D (
dB)
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Performance Summary
Table: Summary of Measured ADC performance.
Signal Bandwidth/Clock Rate 24 kHz / 3.072 MHzQuantizer Range 3 Vpp,diff
Input Swing for peak SNR -1 dBFSDynamic Range/SNR/SNDR 93.5 dB/92.5 dB/90.8 dBActive Area 0.72 mm2
Figure of Merit(DR/SNR) 0.049 pJ/level,0.054 pJ/level
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Some References ...
Delta-Sigma Data Converters: Theory, Design andSimulationS. Norsworthy, R. Schreier and G. Temes, IEEE PressThe Yellow Bible of ∆Σ ADCs
Understanding Delta-Sigma Data ConvertersR. Schreier and G. Temes, IEEE PressThe Green Bible of ∆Σ ADCsBoth the above are essential reading !
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters
Some References ...
Theory, Practice, and Fundamental Performance Limits ofHigh-Speed Data Conversion Using Continuous-TimeDelta-Sigma ModulatorsJ. Cherry, Ph.D Dissertation, Carleton University.Excellent reading on continuous-time Delta-Sigmamodulator design.
A Power Optimized Continuous-time ∆Σ ADC for AudioApplicationsS. Pavan, N. Krishnapura et. al, IEEE Journal of SolidState Circuits, February 2008.Detailed description of the case study discussed inthis tutorial.
Shanthi Pavan Nagendra Krishnapura Oversampling Analog to Digital Converters