Overall Project Objective:

RF Triangulator: Indoor/Outdoor Location Finding 18-525 Architecture ProposalGiovanni FonsecaDavid FuAmir GhitiStephen RoosDesign Manager: Myron Kwai

Overall Project Objective:Overall Project Objective:Design a Radio-Frequency indoor/outdoor navigation Design a Radio-Frequency indoor/outdoor navigation system, utilizing the existing wireless infrastructure.system, utilizing the existing wireless infrastructure.

Design Stage Objective:Design Stage Objective:Final LVS and simulationFinal LVS and simulation

StatusStatus• Structural Verilog complete.Structural Verilog complete.• Schematics completed.Schematics completed.• Layout of basic components complete.Layout of basic components complete.• Major Layouts:Major Layouts:

• ~90% done~90% done FPU: Done, tested.FPU: Done, tested. Lookup: Done, tested.Lookup: Done, tested. Calc: interconnects.Calc: interconnects. Top Three: Finishing layout: 85% doneTop Three: Finishing layout: 85% done

• Global routing still needs to be doneGlobal routing still needs to be done

Current Transistor countsCurrent Transistor counts•Total: 27,150 transistors*•Top Three: 6,500 trans.

3 x FPU Add/Sub Unit 1500 trans. Control Registers & Muxes: 2000 trans.

•Calc: 17,950 trans. 2 x FPU Add/Sub Unit: 1500 trans. 1 x FPU Mult/Div Unit: ~5000 trans. 1 x Logshifter: 200 trans. 1 x Comparator: 800 transistors. FSM Logic: 850 transistors 25 x 12-bit M-S En Reg: 6600 trans. total 8-1,6-1,4-1,2-1 Mux Sets: 3000 trans. total

•Lookup: 2,700 trans. Control Registers & Muxes: 2000 trans. Control Logic: 163 trans.•SRAM: 12k trans

* count not including SRAM, with SRAM: ~38k

Floorplan

FPU LayoutsFPU Layouts

Multiplication & Division Layout

FASU Layout

Lookup LayoutLookup LayoutTotal transistor count: 15018 in layout 14851 in schematic

Area = 208.8*232.3 = 48504u^2.

Density:.31 transistor per u^2.

Top Three ProgressTop Three Progress

Last week’s

This week’s

Lookup rise timeLookup rise time

Lookup fall timeLookup fall time

Lookup propagation timeLookup propagation time

To doTo do

Lookup: doneLookup: done FPU: doneFPU: done Calc:Calc:

• Finish up the interconnects.Finish up the interconnects. Top Three: Top Three:

• Finish up the interconnects.Finish up the interconnects.• Split the schematics and layout into parts Split the schematics and layout into parts

for LVSfor LVS

Questions/ConcernsQuestions/Concerns

Large block simulations take a long Large block simulations take a long timetime

Getting top3 and calc to lvs before Getting top3 and calc to lvs before carnival!carnival!