OVA&OTAVA & OTA - University of Belgradetnt.etf.bg.ac.rs/~ms1aik/AIC-15_OTA_1.pdf · •The op-amp (OVA and OTA) is a fundamental building block in Mixed Signal design. •Employed

OOVA & OTAVA & OTAOOVA & OTA VA & OTA

1Radivoje Đurić, 2015, Analogna Integrisana Kola

OOVAVA--OperationalOperational VoltageVoltage AmplifierAmplifier• Ideally a voltage-controlled voltage source

Typically contains an output stage that can drive “arbitrary” loads including small• Typically contains an output stage that can drive “arbitrary” loads, including smallresistances• Predominantly used for board-level circuitry

OOTATA--Operational Transconductance AmplifierOperational Transconductance Amplifier• Ideally a voltage controlled current source• Typically restricted to capacitive (or moderate resistive) loads• Primarily used in integrated circuits• Primarily used in integrated circuits

•The op-amp (OVA and OTA) is a fundamental building block in Mixed Signal design.• Employed profusely in data converters, filters, sensors, drivers etc.•Continued scaling in CMOS technology has been challenging the established

di f d i


paradigms for op-amp design.

•With downscaling in channel length (L) Transition frequency increases (morespeed)p )Open-loop gain reduces (lower intrinsicgain)Supply voltage is scaled down (lowerheadroom)headroom)VDD is scaling down but VTH is almostconstant (Design headroom is shrinkingfaster))Random offsets due to devicemismatches

1THV WL

WL

•Integration of Analog into Nano-CMOS?Design low-VDD op-amps.Design low VDD op amps. Replace vertical stacking (cascoding) by horizontal cascading of gain stagesExplore more effective op-amp compensation techniques.Offset tolerant designs.Al i i i d l t t k ith th di it l t dAlso minimize power and layout area to keep up with the digital trend.Better power supply noise rejection (PSRR)

•Even if we employ wide-swing biasing for low-voltage designs, three- or higher stage opampswill be indispensable in realizing large open-loop DC gain.

Radivoje Đurić, 2015, Analogna Integrisana Kola3

will be indispensable in realizing large open loop DC gain.

The op amp (operational amplifier) is a high gain, dc coupled amplifier designed to beused with negative feedback to precisely define a closed loop transfer function.

The basic requirements for an op amp:q p p• Sufficiently large gain (the accuracy of the signal processing determines this)• Differential inputs• Frequency characteristics that permit stable operation when negative feedback is applied

Other req irementsOther requirements:• High input impedance• Low output impedance• High speed/frequencyg p q y

OP AMP CHARACTERIZATION•Linear and Static Characterization of the CMOS Op AmpA model for a nonideal op amp that includes some of the linear, static nonidealities:


whereRid = differential input resistanceCid = differential input capacitanceRicm = common mode input resistanceRicm = common mode input capacitanceVOS = input-offset voltageCMRR = common-mode rejection ratio (when v1=v2 an output results)CMRR common mode rejection ratio (when v1 v2 an output results)

= voltage-noise spectral density (mean-square volts/Hertz)

Linear and Dynamic Characteristics of the Op Amp

2ne

Differential and common-mode frequency response:

1 21 2 2out v c

V s V sV s A s V s V s A s

Differential-frequency response:

0

1 2 31 1 1 ...

vv

AA ss s sp p p

1 2 3p p p

i ip


Other Characteristics of the Op Amp•Power supply rejection ratio (PSRR):

•Input common mode range (ICMR):ICMR = the voltage range over which the input common-mode signal can varyICMR = the voltage range over which the input common-mode signal can vary

without influence the differential performance

•Slew rate (SR): maximum current available to charge and discharge a capacitanceSR = output voltage rate limit of the op amp

•Settling time (Ts): the time needed for the output of the output of the op amp to reach a finalvalue value when excited by a small signal (SR is a large-signal phenomenon) Small-signalvalue value when excited by a small signal (SR is a large-signal phenomenon). Small-signalsettling time can be completely determined from the location of the poles and zeros in thesmall-signal equivalent circuit.


OP AMP CATEGORIZATIONAmplifiers generaly consist of a cascade of V-I (transconductance stage) or I-V (load stage)

•Classification of CMOS Op Amps


Output configuration– Single ended

Differential– Differential• Predominantly used for integrated high-performance or high precision amplifiers• Requires common mode feedback circuit

– Class-A• Output cannot source/sink currents larger than quiescent point bias current

– Class-AB• Output can provide large drive currents “on demand”

– Dynamic comparator-based– Dynamic, comparator-based• Still a research topic

Two-stage single ended Miller CMOS OTA


•Classical two-stage CMOS op amp broken into voltage-to-current and current-to-voltagestages:

•Folded cascode CMOS op amp broken into stages:


Two-stage Single ended Folded-Cascode CMOS OTA


COMPENSATION OF OP AMPS•Objective of compensation is to achieve stable operation when negative feedback is appliedaround the op amp. L s A s F s L s A s F s

1A s

CLG sA s F s

0 0 0 01dB dB dBA j F j L j

0 0

0

2 arg

2 argM dB dB

dB

A j F j

L j


Why Do We Want Good Stability?•Consider the step response of second-order system which closely models the closed-loopgain of the op amp connected in unity gain.g p p y g

•A “good” step response is one that quickly reaches its final value.•Therefore, we see that phase margin should be at least 45° and preferably 60° or larger.

(A rule of thumb for satisfactory stability is that there should be less than three(A rule of thumb for satisfactory stability is that there should be less than three rings.)•Note that good stability is not necessarily the quickest rise time.


Root Locus1st order feedback system

•A so-called “root locus” plot shows the movement of the poles in the s plane as we vary thelow-frequency loop gain T0

2nd order feedback system2nd order feedback system


•Consider a feedback network consisting of a forward amplifier with three identical poles, anda feedback network with a constant transfer function f

3rd order feedback system

a feedback network with a constant transfer function f

The poles of A(s) are therefore the solution to


MATLAB:

The transfer function with three poless = tf('s');p1=-1; p2=-2; p3=-4;T = 1 / [(1-s/p1)*(1-s/p2)*(1-s/p3)];rlocus(T)rlocus(T)


Adding a Zero:s = tf('s');z=-5; p1=-1; p2=-2; p3=-4;z 5; p1 1; p2 2; p3 4;T = (1-s/z) / [(1-s/p1)*(1-s/p2)*(1-s/p3)];rlocus(T)


Benchmarking•In order to compare the merit of various compensation techniques, it makes sense to inspect the loop’s unity gain frequency before and after the compensation is applied•Rationale: The maximum bandwidth we can possibly expect from a feedback amplifier is theunity gain frequency of the loopRegardless of the order of the feedback system, the closed-loop response departs from1/f as |T(s)| crosses unity1/f as |T(s)| crosses unity

Consider a loop transfer function with n “dominant” poles that occur before the unitycrossover

The product of the low frequency loop gain and all dominant poles is called the loop gainpole product (LP product)pole product (LP product)Note that in a first-order system, the LP product is simply the gainbandwidth product


Feedback Zero CompensationLeave amplifier poles unchanged and introduce a zero in the feedback network

•Efficiency of Feedback Zero Compensation


To first order, since we do not change the poles, the LP product and ωu are (approximately)unchanged.Feedback zero compensation is therefore bandwidth efficient, since we do not need top ,sacrifice bandwidth to stabilize the circuit.To second order, the LP product will change slightly due to loading from the capacitanceadded in the feedback networkNarrowbanding Compensation

Idea: Make one of the loop poles dominant,leave other poles unchanged

•Efficiency of Narrowbanding

ωp1 that gives a maximally flat magnitude responsefor the closed-loop amplifier?


The crossover and bandwidth is limited to some fraction of ωp2 At first glance, this makes narrowbanding appear to be inefficientHowever, provided that ωp2 is close to the transit frequency of the process technology, this, p p2 q y p gy,compensation approach is acceptable and hard to surpass in terms of absolute achievableclosed-loop speedExample: Single Gain Stage with Current Bufferp g g

•Cgs introduces a non-dominant pole athigh frequencies ωp2 = ωT•CL is adjusted until the circuit achieves thedesired phase margin•This type of narrowbanding is called “loadcompensation,” since stability is ensured byproperly sizing the load capacitance CLproperly sizing the load capacitance CL

Example Realizations


Two-Stage OTA•The two-stage amplifier shown below has two comparable poles, assuming that there is noadditional significant pole from the feedback networkg p

If the feedback network is resistive, we maybe able to compensate the amplifier byintroducing a feedback zerooduc g a eedbac e oWhat can we do if the feedback iscapacitive?

Narrowbanding is not a good idea since both poles are at low frequenciesNarrowbanding is not a good idea, since both poles are at low frequencies

Miller CompensationPurposely connect a capacitor across the second transconductor!p y p

•Two interesting things happenLow frequency input capacitance of secondstage becomes large – moves the first pole tog g pa lower frequencyQualitatively speaking, at high frequencies,Cc turns the second stage into a “diodeconnected device” low impedance i e largeconnected device – low impedance, i.e. largeωp2


• Using the dominant pole approximation:

RHP zero:

We can approximate further as shown below

GBW set by gm1 and CcGBW set by gm1 and Cc

“Pole Splitting”: Increasing Cc reduces ωp1 , and increases ωp2p g g p1 p2


A very nice “knob” for adjusting the phase margin of the circuit!

•Graphical View of Pole Splitting

Miller Compensation of the Two-Stage Op Amp

The various capacitors are:The various capacitors are:Cc = accomplishes the Miller compensationCM = capacitance associated with the first-stagemirror (mirror pole)CI = output capacitance to ground of the first-stageCII = output capacitance to ground of the second-stage


Compensated Two-Stage, Small-Signal Frequency Response Model SimplifiedUse the CMOS op amp to illustrate:• Assume that:

36 3 3 1, , m

C gd m ds ds uM

gC C g g g GBC

1 6,m mI m mIIg g g g

1 1R R 2 4 6 7

,I IIds ds ds ds

R Rg g g g

2 4 6 6 7 7,I db db gs II L db db gdC C C C C C C C C


2I I c c out mI inG s C C V sC V g V

Nodal Equations:

2 0mII c II II c outg sC V G s C C V

out mI mII cV s g g sC

2in I II II I II I II c mII c I II c I c IIV s G G s G C C G C C g C s C C C C C C

0 1/

sA

0

2/

1mII cout

in I I II II II c mII I II c I I I II c I c II

g CV sV s s R C C R C C g R R C s R R C C C C C C

g gg g 1 60

2 4 6 7

m mI II

I II ds ds ds ds

g gg gAG G g g g g

21 11 1 1s s sD

1 2 1 2 1 21 1 1D s s

p p p p p p

2

22 1 1 1s sp p D s as bs 2 1

1 1 21 1p p D s as bs

p p p

1 21 , ap pa b


2 4 6 7

16

1 1 ds ds ds ds

I I II II II c mII I II c mII I II c m c

g g g gpR C C R C C g R R C g R R C g C

62

I I II II II c mII I II c mII mR C C R C C g R R C g gap

I c IIC C C

2I I I II c I c II II L

pb R R C C C C C C C C

Right-half plane zero: 61

mII m

c c

g gzC C

The unity gain bandwidth:

c c

10 1

1 mI mI II

I II mII I II c c c

g gg gGB A pG G g R R C C C

ωp2 must be greater than unity-gainbandwidth or satisfactory phase margin will not beachieved.•Influence of the Mirror Pole

Th t f f ti f th i t t th t t lt f th fi t t

3 1 3 3 4M db db gs gsC C C C C C

The transfer function from the input to the output voltage of the first stage

01 1 3 1 3 1 3 31

/ 2 2 /1m m ds ds m m

d d d d d d

sV s g g g g g g C

sV s g g g g g sC g g


2 4 3 1 3 3 2 4

3 31

/in ds ds m ds ds ds ds

m

sV s g g g g g sC g gg C

3 3 32 /mz g C

3 3 3/mp g C

Th i t f 45° h i i•The requirement for 45° phase margin is:

1 2 1

180 arg 180 45Mp p z

A j F j arctg arctg arctg

1 1, 1,2,pi i zp i z

Let ω = GB and assume that ωz1 >=10GB, GB GB


1 2

45 180 0.1p p

GB GBarctg arctg arctg

0 02

135 0.1 , 1p

GBarctg A arctg arctg A

2 2135 90 5.7 135 90 5.7

p p

GB GBarctg arctg

22 2

39.3 0.818 1.22pp p

GB GBarctg GB

If 60° phase margin is required then the following relationships apply:If 60 phase margin is required, then the following relationships apply:

1 210 2.2z pGB GB

6 16 1

10 10m mg g g g 6 110m mc c

g gC C

6 12

2.2 0.22m mc

g g C CC C

c cC C

CMOS op amp Slew Rate (SR)Sl t h t fl i i it b li it d d i i•Slew rate occurs when currents flowing in a capacitor become limited and is given as

limCdvI C

dt


5 6 5 7 56 5min , ,

c L c

I I I I ISR I IC C C

5 7 5 5

7 5min , ,c L c

I I I ISR if I IC C C

Therefore, if CL is not too large and if I7 is significantly greater than I5, then the slew rate ofthe two-stage op amp should be, I5/Cc.

RIGHT-HALF PLANE ZERO

Controlling the Right-Half Plane ZeroWhy is the RHP zero a problem?Because it boosts the magnitude but lags the phase the worst possible combination forBecause it boosts the magnitude but lags the phase - the worst possible combination forstability.Solution of the problem: The compensation comes from the feedback path through Cc, butthe RHP zero comes from the feedforward path through Cc so eliminate the feedforward path!


Use of Buffer to Eliminate the Feedforward Path through the Miller Capacitor

021

outV s AV s s R C C R C g R R C s R R C C C

1in I I II II II mII I II c I II II I cV s s R C C R C g R R C s R R C C C

2 4 6 7

16

1 1 ds ds ds ds

I I II II II mII I II c mII I II c m c

g g g gpR C C R C g R R C g R R C g C

6I I II II II mII I II c mII I II c m cg g g

I I II II II mII I II mII cR C C R C g R R g Ca

I c IIC C C

2

I I II II II mII I II mII c

I II II I c II I c

g g Capb R R C C C C C C

Poles are approximately what they were before with the zero removedFor 45° phase margin ω must be greater than GBFor 45 phase margin, ωp2 must be greater than GBFor 60° phase margin, , ωp2 must be greater than 1.73GB


Use of Buffer with Finite Output Resistance to Eliminate the RHP Zero•Assume that the unity-gain buffer has an output resistance of Ro

• It can be shown that if the output resistance of the buffer amplifier, Ro, is not neglected thatanother pole occurs at,

and a LHP zero at 4

0

1

I c I cp

R C C C C

and a LHP zero at

Although the LHP zero can be used for compensation, the additional pole makes this

20

1

cz

R C

method less desirable than the following method.

Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero)


01

cImI in I I I out

I c z

sCVg V sC V V VR sC R

Nodal Equations:

I c z

01

cImI I II out out I

II c z

sCVg V sC V V VR sC R

2 3

1

1

cmI mII I II z c

mIIout

i

Cg g R R s R CgV s

V s bs cs ds

1inV s bs cs ds

I I c II II c mII I II c z cb R C C R C C g R R C R C

R R C C C C C C R C R C R C I II I II c I c II z c I I II IIc R R C C C C C C R C R C R C

I II I II c zd R R C C C R

If Rz is assumed to be less than RI or RII and the poles widely spaced then the roots of theIf Rz is assumed to be less than RI or RII and the poles widely spaced, then the roots of theabove transfer function can be approximated as

11 1 1

1I I c II II c mII I II c z c mII II I c mII II I cp

R C C R C C g R R C R C g R R C g R R C

2mII c mII

c I I II c II II

g C gpC C C C C C C

1

111

c z

zC R

g


41

z Ip

R C mIIg

Note that the zero can be placed anywhere on the real axis!We desire that z1 = p2 in terms of the previous notation

2 11 1c IIII

c z zmII mII c mII

C CCp z C R Rg g C g

With p2 canceled, the remaining roots are p1 and p4(the pole due to Rz) . For unity-gainstability, all that is required is that

0AA GB 4 0 1p pmII II I c

A GBg R R C

1 mIg GBR C C

Substituting Rz into the above inequality and assuming CII >> Cc results in

z I cR C C

mIgC C C

This procedure gives excellent stability for a fixed value of CII (≈ CL).Unfortunately, as CL changes, p2 changes and the zero must be readjusted to cancel

c I IImII

C C Cg


y g p g jp2!

Incorporating the Nulling Resistor into the Miller Compensated Two-Stage Op Amp

62

mII m

II L

g gpC C

1

0

1 mI mI

mII II I c mII mI II I c c

g gpg R R C g g R R C A C

41

z Ip

R C 1

6

11

c zm

zC R

g

6mg

•Design of the Nulling Resistor (M8)For the zero to be on top of the second pole (p2), the following relationship must hold

1 1 1c II c L c LC C C C C CR


6 6 62 /c II c L c L

zc mII c m c D p ox

RC g C g C I C W L

The resistor, Rz, is realized by the transistor M8 which is operating in the active regionbecause the dc current through it is zero. Therefore, Rz, can be written as

1 1

The bias circuit is designed so that voltage VA is equal to VB. As a result

8

8 8 880

1 1/ /

DS

zD DS p ox SG THPV

Ri v C W L V V

Equating the two expressions for Rz gives

1010 8

10

2/

DGS THP GS THP

p ox

IV V V VC W L

q g p g

101010 8

8

/1 1/ 22/

/

zp ox DD

p ox

W LR

W L C IIC W LC W L

810/p

p oxC W L

10

106 8

/1 1/ 22 /

c Lz

c p ox DD

W LC CRC W L C II C W L

106 86

68 10 6

10

2 /

/ / /

c p ox DD p ox

c D

c L D

I C W L

C IW L W L W LC C I

1011 6

11 66

DGS GS

D

IW WV VL I L

210 6

811

/ //

/c

c L

W L W LCW LC C W L


•An Alternate Form of Nulling Resistor

To cancel p2To cancel p2,

6 66 6

1 1 1c L Lz m m B

c m m B c

C C CR g gC g g C

6 6

6 6

2 2 1/ /

D D B L

p ox p ox cB

I I CC W L C W L C


Increasing the Magnitude of the Output Pole

12 4 9

1

d d dR

g g g

26

1

d dR

g g

2 4 9ds ds dsg g g 6 7ds dsg g

Nodal equations:8

1 1 8 8 1 1m c

in m s outg sCI G V g V G V V

g sC

S l i f th t f f ti V t/Ii i

8m cg sC

86 1 2 2

80 m c

m outm c

g sCg V G sC Vg sC

Solving for the transfer function Vout/Iin gives

6 8

21 2 62 1 2

1

1

c

out m m

in c c m c

sCV s g gI s G G C C g CC C C


21 2 62 1 2

8 2 2 1 2 8 21in c c m c

m m

C C g CC C Cs sg G G G G g G

Using the approximate method of solving for the roots of the denominator gives

1 21 6p C C g CC C

262 6

8 2 2 1 2

c c m c m ds c

m

C C g CC g r Cg G G G G

26 2m ds cg r C

28 2 6 8

2 22 2

8 2

66 3

m ds m m ds

c

m

g r G g g rp pC C Cg G

8

2m

c

gzC

where all the various channel resistance have been assumed to equal rds and p2’ is the outputpole for normal Miller compensation.Result: Dominant pole is approximately the same and the output pole is increased by ≈gmrdsIn addition there is a LHP zero at gm8/sCc and a RHP zero due to Cgd6 (shown dashed inIn addition there is a LHP zero at -gm8/sCc and a RHP zero due to Cgd6 (shown dashed inthe previous model) at gm6/Cgd6.Roots are:


FEEDFORWARD COMPENSATIONUse two parallel paths to achieve a LHP zero for lead compensation purposes

mIIgs

1out c c

i c II

II c II

sV s AC ACV s C C s

R C C

•To use the LHP zero for compensation, a compromise must be observedPlacing the zero below GB will lead to boosting of the loop gain that could deteriorate thephase marginPlacing the zero above GB will have less influence on the leading phase caused by thePlacing the zero above GB will have less influence on the leading phase caused by thezero

• Note that a source follower is a good candidate for the use of feedforward compensationThis type of compensation is often used in source followers. The capacitor will provide a


path that bypasses the transistor at high frequencies

♦ POWER SUPPLY REJECTION RATIO OF THE TWO-STAGE OP AMP

What is PSRR?

00

v dd

dd in

A vPSRR

A v

00

v ss

ss in

A vPSRR

A v

Method for calculating PSRR:

11

dd ddout dd dd dd

v v

A AV V V VA A PSRR

2out dd dd v dd dd v outV A V A V A V A V

v v

dd

out

VPSRRV

ss

out

VPSRRV

If we connect the op amp in the unity-gain mode and input an AC signal of Vdd (Vss) inseries with VDD (VSS), PSRR will be equal

ddVPSRR ssVPSRR


outPSRR

V

outPSRR

V

Negative PSRR

1 0I c I mI c outG sC sC V g sC V 1I c I mI c outg

1 7 7 7mII c II c II gd out ds gd ssg sC V G sC sC sC V g sC V

Solving for Vout/Vss and inverting:C C C C C C C C C C

2

7

ss

out m I c I

V as bs cV g G s C C

g g

Solve for approximate roots:

7 7c I I II II c I gd c gda C C C C C C C C C C

7I c II gd II c I c mII mIb G C C C G C C C g g

I II mII mIc G G g g Solve for approximate roots:

77

1 1 c I c II c IIc

mI mII css mII mI

dI d

C C C C C CCs sg g CV g gPSRR

CV G g C C


77

71 1 gdout I ds c I

I ds

CV G g C Cs sG g

21 11 1

0c II

pmI mII II vss mII mI

s sC Cs s GBg g G AV g gPSRR

7 77 7

7 71 1 1 1gd gdout I ds dsc mI

ds I ds I

PSRRC CV G g gC gss s sg G g GB G

Comments:Comments:• DC gain has been increased by the ratio of GII to gds7• Two poles instead of one, however the pole at -gds7/Cgd7 is large and can be ignored.


Positive PSRR

The nodal equations:

1I c I mI c out I ddG sC sC V g sC V G V

1 4 2 4 6 7 1 2 6, , ,I ds ds ds ds II ds ds mI m m mII mG g g g g G g g g g g g g 1 6mII c II c II out mII ds ddg sC V G sC sC V g g V

Using Cramers rule to solve for the transfer functionVout/Vdd, and inverting the transferfunction gives the following result

1 4 2 4 6 7 1 2 6, , ,I ds ds ds ds II ds ds mI m m mII mG g g g g G g g g g g g g

2ssV as bs c


6 6 6

ss

out I ds c mII I ds I mII dsV G g s C g G g C g g

c I I II II ca C C C C C C

I c II II c I c mII mIb G C C G C C C g g

I II mII mIc G G g g

We may solve for the approximate roots of numerator as

6

1 1

1

c I c II c IIc

mI mII cdd mII mI

out I ds mII c

C C C C C CCs sg g CV g gPSRR

V G g g Cs

Where gmII > gmI and that all transconductances are larger than the channel conductances:

61 mII c

I dssG g

2

6 6

1 11 10

01 1

c II

pmI mII II vdd mII mI

out I ds ds II vmII c

s sC Cs s GBg g G AV g gPSRRV G g g G Ag C s

At approximately the dominant pole the PSRR falls off with a -20dB/decade slope and

6 6

6 61 1out I ds ds II vmII c

I ds ds

g ggsG g GB g

At approximately the dominant pole, the PSRR falls off with a 20dB/decade slope anddegrades the higher frequency PSRR + of the two-stage op amp.


Approximate Model for PSRR+The M7 current sink causes VSG6 to act like a battery2) Therefore, Vdd couples from the source to gate of M63) Th th t th t t i th h it f t t d i f M63) The path to the output is through any capacitance from gate to drain of M6Conclusion: The Miller capacitor Cc couples the positive power supply ripple directly to theoutput.Must reduce or eliminate Cc!


Approximate Model for Negative PSRR with VBias Connected to GroundApproximate Model for Negative PSRR with VBias Connected to Ground

Path through the inputstage is not important aslong as the CMRR is highg g


Path through the output stage:

7t t tV I Z g V Z 7out ss out m ss outV I Z g V Z

1||1

outout out

out out out

RZ RsC sC R

7

1out m out

ss out out

V g RV sC R

The two-stage op amp will never have good PSRR because of the Miller compensationThe two-stage op amp is a very general and flexible op amp


Cascoding!

•The compensation scheme used in this paper employs a feedforward path to create LHPeros b t does not se an Miller capacitor

Feedforward compensation without Miller Capacitor

zeros, but does not use any Miller capacitor.•The dominant pole is not pushed to lower frequencies, resulting in a higher gain-bandwidthproduct with a fast step response.

0, 1,2,3mi

vii

gA ig

0

0, 1,2j

pjj

gj

C

3

1 2 3 1 1 vv v v

s A sA A AA A A

1 1 2 3 1

1 2 3

1 2 1 21 1 1 1

p v v v pv v v

p p p p

A A AH s A A A

s s s s

The OTA transfer function has two poles and a LHP zero created by the feedforward path.The location of the LHP zero is

1 2 1 21 v v m mA A g gz


1 13 01 3

1 pv m

zA C g

The second and feedforward stages can be designed such that the negative phase shift dueto ωp2 is compensated by the positive phase shift of the LHP zeroWhen the frequency of ωp2 exactly coincides with that of the LHP zero, the amplifier phaseq y p2 y , p pmargin is 90 and the unity-gain frequency is given by

1 2 3 1 2 1v v v v v pGB A A A A A

(a) Perfect pole–zero cancellation (b) Pole–zero mismatch

This compensation scheme results in an amplifier with high gain and fast responseThe bandwidth improvement is due to the fact that the poles are not split, as is the case in any amplifier with Miller compensation


OVA&OTAVA & OTA - University of Belgradetnt.etf.bg.ac.rs/~ms1aik/AIC-15_OTA_1.pdf · •The op-amp (OVA and OTA) is a fundamental building block in Mixed Signal design. •Employed

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