Outphasing RF Power Amplifiers for Mobile Communication Base Station Applications Differenzphasengesteuerte Hochfrequenz-Leistungsverst¨ arker f¨ ur die Anwendung in Mobilfunk Basisstationen der Technischen Fakult¨ at der Friedrich-Alexander-Universit¨ at Erlangen-N¨ urnberg zur Erlangung des Doktorgrades Dr.-Ing. vorgelegt von M.Sc. Zeid Abou-Chahine aus Al-Manara, Libanon
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Outphasing RF Power Amplifiersfor Mobile Communication Base Station Applications
Differenzphasengesteuerte Hochfrequenz-Leistungsverstarkerfur die Anwendung in Mobilfunk Basisstationen
der Technischen Fakultat
der Friedrich-Alexander-Universitat Erlangen-Nurnberg
zur Erlangung des Doktorgrades
Dr.-Ing.
vorgelegt von
M.Sc. Zeid Abou-Chahine
aus Al-Manara, Libanon
Als Dissertation genehmigt
von der Technischen Fakultatder Friedrich-Alexander-Universitat Erlangen-Nurnberg
Tag der mundlichen Prufung: 18.06.2015
Vorsitzende des Promotionsorgans: Prof. Dr.-Ing. habil. Marion Merklein
Gutachter: Prof. Dr.-Ing. Georg FischerProf. Dr.sc.techn. Renato Negra
All praise be to Allah, the Lord of the worlds.
Alles Lob gehort Allah, dem Herrn der Welten.
AbstractThe continuously growing focus on reducing energy consumption worldwide has infiltrated
into the telecommunications domain in its both mobile terminals and base stations. This
has led eventually to the introduction of advanced power amplifier (PA) architectures.
This work investigates the suitability of outphasing PAs for use as a high efficiency solu-
tion in next generation base station applications. Besides the classical Chireix concept,
several newly emerging outphasing variants are analyzed and compared. The effects of the
nonlinear output capacitance are considered in detail. It is shown that harmonic isolation
is vital for the Chireix PA realization using transistor devices. In addition, the power
capability of the Chireix outphasing PA is discussed and a load-pull simulation technique
for the complete PA is proposed. The findings are used to develop a method for designing
practical Chireix PAs.
A proof of concept 60 W Chireix PA prototype using state of the art GaN HEMTs is
presented. Measurements with 5 MHz 1-Carrier and 20 MHz 2-Carrier W-CDMA signals
of 7.5 dB PAR resulted in respectively 45 % and 44 % average drain efficiencies.
UbersichtFur Telekommunikationsausruster Endgeratehersteller wie Infrastrukturlieferanten liegt der Schwerpunkt weltweit mehr und mehr auf einem geringen Energieverbrauch.
Dieser Schwerpunkt erfordert die Einfuhrung fortgeschrittener Leistungsverstarker-
architekturen.
Diese Arbeit untersucht die Eignung des Outphasing-Konzepts im Hinblick auf hochef-
fiziente Leistungsverstarker fur fortschrittliche Sendestationen der drahtlosen Kommu-
nikation. Neben dem klassischen Chireix-Verfahren werden verschiedene moderne
Outphasing-Varianten untersucht und gegeneinander abgewogen. Es wird gezeigt, dass
es bei Verwendung von Transistoren im Chireix-Verstarker vordringlich auf die Isolation
der beiden Pfade bei den Vielfachen der Grundfrequenz ankommt. Ferner wird die Eig-
nung von Outphasing-Verstarkern fur hohe Ausgangsleistungen untersucht und ein neues
Load-Pull-Simulationsverfahren zur Verstarkerentwicklung vorgeschlagen. Die Ergebnisse
laufen in einem neuen Entwurfsverfahren fur Chireix-Leistungsverstarker zusammen.
Die Eigenschaften des Entwurfsverfahren werden herausgerabeitet und seine Eignung
anhand eines 60 W Chireix-Verstarker basierend auf GaN-HEMT-Bauelementen nach-
gewiesen. Messungen zeigen bei 7, 5 dB Spitzen- zu Mittelwertleistung einen Wirkungs-
grad von 45 % bei einem 5 MHz breiten W-CDMA-Signal, und 44 % bei 2 W-CDMA-
Signalen und 20 MHz Signalbandbreite.
Acknowledgements
The completion of the research work presented in this doctoral thesis would not have been
affordable without the support of numerous people.
I would like to thank deeply Prof. Dr.-Ing. Georg Fischer for his supervision through-
out this phase. His guidance and support have been a great help to me for completing
this thesis. I am thankful to all his suggestions and valuable comments. My grateful
appreciations are also extended to Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel for the
opportunity to join the Institute for Electronics Engineering and pursue a doctoral degree
at the Friedrich-Alexander University in Erlangen.
This work was funded by Nokia Siemens Networks in Ulm, Germany. I would like to
thank NSN for their generous backing. As a member of the Radio Frequency Research
and Predevelopment team, I have been surrounded by inspiring advisers and colleagues
who have provided me with a productive environment to conduct research and explore
new ideas. I would like to thank especially Dr.-Ing. Tilman Felgentreff for the project su-
pervision and guidance. His professional assistance has helped me in keeping my progress
on schedule. I wish to thank the colleagues in the RF team too, namely Karlheinz Borst,
Dr.-Ing. Abhijit Ghose, Helmut Heinz, Norbert Huller, Wilhelm Schreiber and Georg
Wissmeier for all their support, and last but not least Dr.-Ing. Christoph Bromberger
for his support and for the many interesting discussions we made. My thanks are also
extended to Dr. Christian Schieblich and his entire team for sharing their technical in-
sights in several occasions. The work progress would have been much slower without the
support with the remote simulations server. For that, I would like to thank Jorg Zopnek.
Also, many thanks go to Hans Jugl for his skilled care when it came to the circuit boards
construction.
I would like to express my vast appreciations to Frank Dechen. His expert support espe-
(2.32) is evaluated for the same parameter values, as well as the Wilkinson’s efficiency
expression presented in [14]. The simulated curve plotted in Fig. 2.4 confirms the derived
analytical efficiency expression. The earlier form encountered in literature presents an
incomplete description of the ideal Wilkinson’s combiner efficiency, where it is limited to
selections of V1, V2, θ1 and θ2 such that θ3 is an arbitrary constant2.
0 5 10 15 20 25 30 35 40 45 505
10
15
20
25
30
35
40
45
50
V2 (V)
η(%
)
Simulated (2.34)Analytical (2.32)Analytical [14]
Figure 2.4: Wilkinson’s η assessment: V1 50 V, θ1 70 and θ2 30 .
2If 0 V1,2 and 0 ¤ θ1,2 ¤ π2 then θ3 shall be 0 for outphasing amplifier applications.
11
2 Outphasing Architecture Analysis
2.2.3 Amplifier Loads
From (A.2b), rIL1pλ4q j
V 1
Z0
p1 Γ1q (2.35)
Substituting V 1 by its form in (2.22) and solving results in
rIL1pλ4q j
2ZL
rV1=pθ1q V2=pθ2qs (2.36)
Similarly rIL2pλ4q j
2ZL
rV1=pθ1q V2=pθ2qs (2.37)
rIiso rV1pλ
4q rV2pλ
4q
2ZL
V1=pπ2 θ1q V2=pπ
2 θ2q
2ZL
j
2ZL
rV1=pθ1q V2=pθ2qs (2.38)
The currents generated by the PAs are therefore
rI1 rIL1pλ4q rIiso j
ZL
V1=pθ1q (2.39a)
rI2 rIL2pλ4q rIiso j
ZL
V2=pθ2q (2.39b)
The impedances seen by each amplifier are respectively
Z1 rV1pλ
4qrI1
(2.40a)
Z2 rV2pλ
4qrI2
(2.40b)
Using (2.12a) and (2.39a), this translates into
Z1 V1=pπ
2 θ1q
jZL V1=pθ1q
jV1=pθ1q jZL V1=pθ1q
ZL (2.41)
Similarly Z2 ZL ñZ1 Z2 ZL (2.42)
This means that the loads seen by each amplifier are constants no matter what the
other variables are. Employing a Wilkinson combiner signifies that no load modulation
is occurring. This is an integral difference to the Chireix combiner case which is analyzed
in the next Section.
12
2.3 Outphasing with Chireix Combiner
2.3 Outphasing with Chireix Combiner
A first step toward an RF realization of the Chireix combiner would be to omit the
isolating resistance of the Wilkinson combiner (Fig. 2.2). The resulting impedances that
the PA devices see then become
Z1 rV1pλ
4qrIL1pλ
4q Z2
0
ZL1
(2.43a)
Z2 rV2pλ
4qrIL2pλ
4q Z2
0
ZL2
(2.43b)
For Z0 ?2ZL and considering the symmetric case using (2.26a) and (2.26b), the
impedances can be written as
Z1 2ZL
p1 =p2θqq ZL p1 j tanpθqq (2.44a)
Z2 2ZL
p1 =p2θqq ZL p1 j tanpθqq (2.44b)
The admittances follow then as
Y1 1
Z1
p1 =p2θqq2ZL
(2.45a)
Y2 1
Z2
p1 =p2θqq2ZL
(2.45b)
ñ
Y1 1 cosp2θq2ZL
jsinp2θq
2ZL
(2.46a)
Y2 1 cosp2θq2ZL
jsinp2θq
2ZL
(2.46b)
For Yi Gi jBi, the conductances and susceptances are
G1 1 cosp2θq2ZL
(2.47a)
B1 sinp2θq2ZL
(2.47b)
G2 1 cosp2θq2ZL
(2.47c)
B2 sinp2θq2ZL
(2.47d)
The described configuration might be named the uncompensated Chireix combiner. Be-
sides performing outphasing on the excitation sources, Chireix’s consequent idea is that
13
2 Outphasing Architecture Analysis
by compensating the susceptances at a specific angle θc, the impedances seen by the PA
devices are set to exhibit only a real part. In power engineering, this is known as reactive
power control. Together with the usage of PAs in their nonlinear regime, this would bring
overall efficiency benefits as shown in the following.
2.3.1 Chireix Analysis with Ideal Class-B PAs
The analysis so far has required that the voltage excitations (2.9a) and (2.9b) be sinusoidal
with no further conditions. Therefore in this ideal case, the voltages should be free of
harmonic content. This can be approached by assuming that all harmonics are terminated
with a short circuit. From this perspective, the pure class-B PA constitutes an ideal
candidate for the PA blocks of the outphasing architecture. Besides its sinusoidal output
voltage waveform, its uncompromised power for efficiency over class-A PA [13] makes
it ultimately suitable for the outphasing architecture. One could as well consider the
use of class-C PA seeking higher efficiency, however this is expected to occur at the
expense of available output power as the class-C PA’s power continuously decreases below
class-A’s power with the conduction angle decreasing below π [13]. The magnitude of
the fundamental component of class-B PA’s output current in relation to the consumed
current IDC can be found by applying the Fourier series decomposition to the output
current waveform. From [12]:
IDC 2
πrIfund
(2.48)
Simultaneously, the fundamental output currents can be written as:
rI1 Y1 rV1pλ4q (2.49a)
rI2 Y2 rV2pλ4q (2.49b)
Therefore by noticing that (2.46a) and (2.46b) assume a complex conjugate relationship
(Y1 Y 2 ) and that for the symmetric case
rV1pλ4q rV2pλ
4q V0, the consumption
currents can be expressed as:
IDC1 IDC2 2
π V0 |Yi| (2.50)
Assuming a full-swing all-time positive output voltage waveform for the class-B blocks,
their DC voltage should be equal to V0. The combined DC power consumption is hence:
PDC 2V0 IDCi 4
π V 2
0 |Yi| (2.51)
Adapting (2.31) to the symmetric case results in:
PL V 20
ZL
cos2pθq (2.52)
14
2.3 Outphasing with Chireix Combiner
The efficiency of an outphasing amplifier employing an uncompensated Chireix combiner
and ideal class-B blocks is therefore:
η PL
PDC
π
4 cos2 θ
ZL |Yi| (2.53)
A direct observation for improving the efficiency is trying to diminish the magnitude |Yi|.The second step toward the Chireix combiner therefore is to add shunt jX and jXelements compensating respectively the susceptances (2.47b) and (2.47d) at a specific
outphasing angle θc so that
X sinp2θcq2ZL
(2.54)
The resulting topology is depicted in Fig. 2.5. To calculate the resulting new Yi ad-
Figure 2.5: Outphasing with Chireix combiner.
mittances, it is sufficient to add the terms jX and jX to respectively (2.46a) and
(2.46b); as long as the voltage excitation sources are symmetrically sinusoidal, introduc-
ing shunt admittances is valid and is not expected to perturb the analysis. Therefore the
admittances become
Y1 1 cosp2θq2ZL
jsinp2θq
2ZL
jsinp2θcq
2ZL
Y2 1 cosp2θq2ZL
jsinp2θq
2ZL
jsinp2θcq
2ZL
(2.55a)
(2.55b)
Fig. 2.6 shows on the Smith-chart the impedances of the uncompensated Chireix combiner
(2.44) along with the impedances of the compensated Chireix combiner (reciprocal of 2.55)
with an illustrative compensation angle θc 15 . As inferred by the equations, the real
part in the uncompensated case is constant. Although the combiner itself is lossless,
this hints to an overall continuous degradation of efficiency as the operation point moves
15
2 Outphasing Architecture Analysis
away from desirable load values while θ and subsequently the delivered power is being
modulated. In a striking difference to that and to the Wilkinson combiner case (2.42),
the real parts of the compensated Chireix impedances3 do vary as θ is being modulated.
Recalling that θ’s modulation is implied by the input signal’s magnitude (2.3), both the
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
3.0
4.0
5.0
10 2020
-20
10
-10
5.0
-5.0
4.0
-4.0
3.0
-3.0
2.0-2
.0
1.8
-1.8
1.6
-1.6
1.4
-1.4
1.2
-1.2
1.0
-1.0
0.9
-0.9
0.8
-0.8
0.7
-0.7
0.6
-0.6
0.5-0
.5
0.4
-0.4
0.3
-0.3
0.2
-0.2
0.1
-0.1
Theta (0.000 to 89.000)
Ga
mm
a1U
Ga
mm
a2U
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
3.0
4.0
5.0
10 20
20
-20
10
-10
5.0
-5.0
4.0
-4.0
3.0
-3.0
2.0-2
.0
1.8
-1.8
1.6
-1.6
1.4
-1.4
1.2
-1.2
1.0
-1.0
0.9
-0.9
0.8
-0.8
0.7
-0.7
0.6
-0.6
0.5-0
.5
0.4
-0.4
0.3
-0.3
0.2
-0.2
0.1
-0.1
Theta (0.000 to 89.000)
Ga
mm
a1C
Ga
mm
a2C
Figure 2.6: Uncompensated (left) vs. compensated Chireix combiner impedances loci.
real and imaginary parts of the admittances (2.55) and their corresponding impedances are
in fact being indirectly modulated by the input signal’s magnitude rptq. This is a pivotal
point for the Chireix PA as it means that the device’s load is modulated for each input
power level and consequently for each output power level. That load modulation behavior
is what exactly classifies the Chireix PA as a typical load modulated PA architecture. The
impedance loci dependence on the design parameter θc and on ZL is shown in Fig. 2.7.
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
3.0
4.0
5.0
10 20
20
-20
10
-10
5.0
-5.0
4.0
-4.0
3.0
-3.0
2.0-2
.0
1.8
-1.8
1.6
-1.6
1.4
-1.4
1.2
-1.2
1.0
-1.0
0.9
-0.9
0.8
-0.8
0.7
-0.7
0.6
-0.6
0.5-0
.5
0.4
-0.4
0.3
-0.3
0.2
-0.2
0.1
-0.1
Theta (0.000 to 89.000)
Gam
ma1
Gam
ma2
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
3.0
4.0
5.0
10 20
20
-20
10
-10
5.0
-5.0
4.0
-4.0
3.0
-3.0
2.0-2
.0
1.8
-1.8
1.6
-1.6
1.4
-1.4
1.2
-1.2
1.0
-1.0
0.9
-0.9
0.8
-0.8
0.7
-0.7
0.6
-0.6
0.5-0
.5
0.4
-0.4
0.3
-0.3
0.2
-0.2
0.1
-0.1
Theta (0.000 to 89.000)
Gam
ma1
Gam
ma2
Figure 2.7: Impedance loci sets for different θc and ZL settings. The arrows indicate
orientations of increasing (left) θc and (right) ZL, respectively from 10 to 30
in 5 steps for ZL 50 Ω, and from 10 Ω to 50 Ω in 10 Ω steps for θc 15 .
3Recall that the real part of a complex impedance is not equal to the reciprocal of the real part of its
equivalent admittance.
16
2.3 Outphasing with Chireix Combiner
As suggested by (2.52), the power back-off (PBO) level can be written as the following
function of θ
PBO 10 log
maxpPLq
PL
20 logpcospθqq (2.56)
The real and imaginary parts of the compensated Chireix impedances can now be replotted
as a function of the PBO. The load modulation behaviour of the Chireix PA can hence
be clearly seen in Fig. 2.8 and 2.9, where only Z1 has been shown since Z1 Z2 .
−30 −27 −24 −21 −18 −15 −12 −9 −6 −3 00
500
1000
1500
2000
PBO (dB)
realZ1(Ω
)
θc =10
θc =15
θc =20
θc =25
θc =30
(a)
−30 −27 −24 −21 −18 −15 −12 −9 −6 −3 0−1500
−1000
−500
0
500
1000
PBO (dB)
imagZ1(Ω
)
θc =10
θc =15
θc =20
θc =25
θc =30
(b)
Figure 2.8: Modulated (a) real and (b) imaginary parts of the compensated Chireix
impedance Z1 for different compensation angle settings; ZL 50 Ω.
−30 −27 −24 −21 −18 −15 −12 −9 −6 −3 00
200
400
600
800
PBO (dB)
realZ1(Ω
)
ZL =10 Ω
ZL =20 Ω
ZL =30 Ω
ZL =40 Ω
ZL =50 Ω
(a)
−30 −27 −24 −21 −18 −15 −12 −9 −6 −3 0−600
−400
−200
0
200
PBO (dB)
imagZ
1(Ω
)
ZL =10 Ω
ZL =20 Ω
ZL =30 Ω
ZL =40 Ω
ZL =50 Ω
(b)
Figure 2.9: Modulated (a) real and (b) imaginary parts of the compensated Chireix
impedance Z1 for different ZL settings; θc 15 .
The incorporation of compensation elements into the combiner does not only compensate
the susceptances and consequently boosts the power factor, but remarkably results in a
modulation of the real part instead of a constant one in (2.44). It can be noted that
the real part peaks at a PBO that is related to θc. The relationship can be found by
determining the real part of the reciprocal of (2.55). On the other hand, the imaginary
part nulls two times, one corresponding to θ θc and the other one to θ π2 θc.
17
2 Outphasing Architecture Analysis
The ideal class-B Chireix efficiency expressed in (2.53), can now be reevaluated for the
compensated Chireix combiner as
η π
2 cos2 θ
|1 cosp2θq j sinp2θq j sinp2θcq| (2.57)
and plotted as shown in Fig. (2.10) for an arbitrarily selected θc 15 compensation.
The efficiency advantage can be noticed by comparison with the outphasing efficiency
of the uncompensated case and when employing a Wilkinson combiner (2.33). Due to
Figure 2.10: Outphasing efficiencies assuming ideal class-B PA blocks.
the nature of the function (2.57), two efficiency peaks emerge for the Chireix curve, one
located at θ θc and the other at θ π2θc. If PBOHD and PBOLD designate how deep
respectively the high drive and low drive peaks fall in PBO, and ∆ their distance in dB,
then
PBOHD 20 logpcospθcqqPBOLD 20 logpcosp90 θcqq
∆ PBOHD PBOLD
20 logpcotpθcqq
(2.58a)
(2.58b)
(2.58c)
At this stage, it should be mentioned that linearity is not questioned with regard to the
two PAs’ class of operation since the reconstruction of the amplitude in an outphasing
PA is ultimately performed by modulating θ. In the following Chapter, some emerging
outphasing variants are considered.
18
Chapter 3
Emerging Outphasing Variants Study
“Methods hitherto employed for reducing power consumption include the high level
class B modulation system, such as is used at WLW, and the ingenious method of
“outphasing modulation” invented by Chireix and employed in a number of European
installations.”— William H. Doherty, A New High Efficiency Power Amplifier for Modulated Waves
In addition to the original concept, several outphasing variants have appeared in the
last two decades. These suggested efficiency enhancement techniques can be classified
into two outphasing PA families; one employing an isolating combiner where no mutual
load modulation is occurring, and the other employing a nonisolating combiner, e.g. the
Chireix combiner, with some further external mechanism. In this Chapter, an assessment
of a multitude of these variants is reported. After defining a benchmark for the efficiency
calculations, a comparison of the discussed variants is presented.
3.1 PA-Engine Analogy
To gain an understanding of the efficiency enhancement techniques applicable for PAs in
general, it might be handy to draw an analogy between the PA as a system converting
DC to RF energy, and the internal combustion engine converting chemical to mechanical
energy. Fig 3.1 shows the fuel consumption of a traditional car. With the x-axis (speed)
relating power and the y-axis (mpg) relating efficiency, it can be seen how efficiency is
not the same for all output powers. The car performs best in terms of fuel consump-
tion around 40 mph (65 km/h). The inevitable need for accelerating and decelerating
requires however a system to modulate the engine’s load. Without a gearbox it would
be extremely hard to accelerate from a stationary position while the gear ratio is 5 for
instance. If it is not going to choke, the car would burn a lot of fuel without barely moving
a tiny distance forward. A gearbox allows to present the engine with the “right” load
at each operating output power level or output power level interval. Considering now
and Baliga’s figure-of-merit (JFM [44] and BFM [45]) are respectively derived from
JFM Eb vsat
2π(4.1a)
BFM ε µ E3g (4.1b)
The high breakdown field of GaN HEMTs allows operation at high drain voltages. This
leads to two main contributions concerning PA performance: first, in order to deliver the
same power level when compared with other technologies, a higher drain voltage means a
lower internal current and therefore less internal losses. Second, the higher drain voltage
translates for the same power level into a higher output impedance level, resulting in
lower loss matching circuits [42] due to the enhanced proximity to 50 Ω. On the other
hand a smaller dielectric constant results in smaller capacitances, leading in turn to higher
cutoff frequency. As the cutoff frequency relates to the gain-bandwidth product [46], the
result is the ability to support higher bandwidth. Furthermore, the higher saturated
velocity results in smaller charge densities for the same current. This means that the area
can be reduced [43] leading to further reduction in capacitances. The GaN advantages
constituted a motivation to select the GaN HEMT as the building block in this work.
The reported Chireix PA and other single track PAs are therefore all GaN based.
32
4.2 Maximum Power Capability
4.2 Maximum Power Capability
Since not only efficiency but the figure watt(s) per currency unit is concerned too, it
is important to estimate the maximum achievable power of a Chireix PA using specific
transistor devices. The maximum power condition emanating from the delivered power
equation of a Chireix PA (2.52) is θ 0 . That equation suggests also that by making
ZL smaller, e.g. using an impedance transformer, the maximum obtainable power can be
enhanced accordingly. However that would be applicable to ideal sources only. In practice,
the maximum voltage Vmax and current Imax levels a given transistor can withstand do
limit its achievable maximum power, and therefore the architecture’s potential. To be
able to extract the maximum power from a single device1 at θ 0 as well, it is desired
to have:
|Y1,2p0q| Imax
Vmax
(4.2)
Evaluating (2.55) at θ 0 allows to write 1
ZL
jsinp2θcq
2ZL
Imax
Vmax
(4.3)
Consequently, the task translates into finding the optimum Chireix load ZL denoted Zopt
that maximizes the output power capability. This results in:
Zopt 1
2 Vmax
Imax
b
sin2p2θcq 4 (4.4)
The maximum achievable power can hence be found by reevaluating (2.52) at θ 0 for
ZL Zopt:
Pmax V 20
Zopt
(4.5)
Under full-swing operation, while the output bias DC voltage, VDC, is equal to V0, the
corresponding rail-to-rail voltage 2VDC should then be equating Vmax. The absolute max-
imum power that can be obtained from a Chireix PA employing two transistors with
breakdown limits Vmax and Imax can be estimated to be
Pmax 1
2 Vmax Imaxa
sin2p2θcq 4(4.6)
As can be seen, the impact of the technology is direct; while higher transistor’s maximum
ratings intuitively point out to a higher Chireix PA power ability, the design parameter
θc introduces too a traceable though much less heavier impact on the architecture’s capa-
bilities. A more detailed understanding can be gained by considering the classical class-B
1For more on loadline match and conjugate match, the reader is referred to [13].
33
4 Practical Considerations for Chireix PA Design
PA abilities built using a single transistor. The Fourier analysis suggests the following
relation between Imax and the magnitude of the fundamental:rIfund
Imax
2(4.7)
The obtainable maximum power out of a single device (in an isolated class-B configura-
tion) is hence
Pimax V0?2
rIfund
?
2 1
8 Vmax Imax (4.8)
That is in principle what is reflected in load-pull (LP) measurements. By comparing this
to (4.6), it can be stated that the Chireix PA using two devices in class-B bias does not
exactly possess twice the power capability of a classical class-B PA built out of one of
these same devices. In fact, that’s only valid in the particular case when θc 0 , or in
other terms when the Chireix PA degenerates to the uncompensated Chireix case. The
following graph shows an exemplary Pmax curve for a class-B Chireix PA out of two GaN
devices marketed for the 30 W range with the following ratings at room temperature [47]:
Vmax 84 V and Imax 3 A. Regardless of the power application, the maximum power
0 5 10 15 20 25 30 35 40 4556
57
58
59
60
61
62
63
θc ()
Max
imum
Pow
er (
W)
−0.51
−0.43
−0.36
−0.28
−0.21
−0.14
−0.07
0
Pow
er D
egra
datio
n (d
B)
(a)
0 5 10 15 20 25 30 35 40 45−0.5
−0.4
−0.3
−0.2
−0.1
0
θc ()
Max
Pow
er D
egra
datio
n (d
B)
(b)
Figure 4.2: (a) 2 31.5 W Chireix’s maximum power capability vs. the design parameter
θc and (b) the generic defined degradation factor κ.
degradation factor κ can be defined as the ratio of a class-B Chireix’s maximum achievable
power to what would have been obtained from the same employed two devices, having
however each operated as a single class-B PA:
κ 10 log
Pmax
2Pimax
10 log
d4
sin2p2θcq 4
(4.9)
At its worst case, the “losses” attributed to κ remain below 0.5 dB (Fig. 4.2). Recalling
from (2.57) that θc is ideally the only parameter affecting the overall efficiency perfor-
mance, low values of κ means that the selection of θc is sustained. Furthermore extreme
34
4.3 Transistor Model
selections of θc nearby 45 that result in the highest κs are not expected2.
Often, it is desired to keep in practice some margin away from the ratings, for instance
due to their temperature dependent nature. One option is therefore to slightly lower V0
while keeping VDC Vmax2. This measure is useful as well when it is desired to keep the
drain voltage above the transistor’s knee voltage Vk. In this case, Zopt is adjusted to
Zopt 1
2 VDC V0
Imax
b
sin2p2θcq 4 (4.10)
and Pmax becomes
Pmax 2V 20 Imax
VDC V0
1asin2p2θcq 4
(4.11)
where κ still holds3. Accordingly, a good balance in the selection of VDC and V0 should
be made to meet a certain desired power capability. It must be noted that the obtained
expressions are only approximations. Nevertheless it was found for instance that (4.4)
and (4.10) serve as a very good starting point in the design and optimization of a Chireix
PA combiner based on a more sophisticated ADS model4.
4.3 Transistor Model
Modeling of a GaN HEMT can get quiet complex. In fact [48] reports a 22-element small-
signal model accounting for the various parasitic elements of the device. This allows
to reflect the device physics over wide bias and frequency ranges. A scalable LS model
can be consequently constructed from the obtained multibias small-signal model [49, 50].
When it comes to circuit design, indeed the accuracy of such models play a vital role for
the success of the design. Furthermore, the load-modulation rich behavior of the Chireix
outphasing architecture (Fig. 2.8) necessitates an accurate and reliable transistor model,
as classical LP measurements at specific operation points do not constitute at all a suitable
design option. While indeed a complex model was employed in circuit simulations, this
Section presents a primitive model that paves the way for a realistic understanding of
the behavior of the Chireix PA when implemented using transistors rather than tubes.
Fig. 4.3 shows a simplified small-signal equivalent circuit model of a packaged HEMT
assuming a lossless package. The intrinsic model’s Π topology suggests the application of
Y-parameters [51] to characterize its electrical properties. Focusing for now only on the
intrinsic part of the packaged HEMT is partly justified by the possibility to compensate
2The compensation angles for the applicable examples studied in Section 3.5 did not surpass 20 .3Recall that the optimum load for a class-B PA becomes RB pVDC V0qpImaxq.4This is presented in the design Chapter, i.e. Chapter 5.
35
4 Practical Considerations for Chireix PA Design
Figure 4.3: Packaged GaN HEMT simplified small-signal equivalent circuit model.
reactive parts of the package parasitics since the remaining resistive losses (corresponding
resistances not shown) are unavoidable in reality. This helps in reaching the sought-after
functional understanding of the Chireix PA operation using transistors. These parameters
are [52]:
y11 Ri C2
gs ω2
D jω
Cgs
D Cgd
(4.12a)
y12 jω Cgd (4.12b)
y21 gm ejωτ1 jRi Cgs ω jω Cgd (4.12c)
y22 gd jω pCds Cgdq (4.12d)
where D 1 R2i C2
gs ω2.
The equivalent Y-parameters representation is shown in Fig. 4.4 for both conduction and
pinch-off conditions (ON and OFF states), where the output capacitance is the equivalent
parallel combination of the drain-source and gate-drain capacitances:
Cout Cds Cgd (4.13)
(a) (b)
Figure 4.4: Y representation of the intrinsic HEMT in (a) ON and (b) OFF states.
36
4.4 Practical Chireix Analysis
4.4 Practical Chireix Analysis
The original Chireix analysis encompassed some idealistic assumptions. To be able to
closely approach the very promising Chireix efficiency curve (Fig. 2.10) in reality, devia-
tions from ideal case that emerge upon the use of solid-state transistors should be carefully
considered, and whenever possible minimized. In parallel to the Chireix combiner design,
the major points to be considered in that quest are identified as:
Gate bias voltage: The gate bias should be set such that the transistor is ON
half the time, resulting in a drain current as much close as possible to a half-sine
waveform. Strongly deviating from this bias for instance by operation in class-AB
means a departure from the analysis that inherently assumed that, and expectedly
a direct hit to efficiency. On the other hand, operating in deep class-C means less
power capability.
Package parasitics compensation: Unpackaged transistors are not suitable for
high power BTS applications. In order to mimic the ideal Chireix combiner (Fig.
2.5), it is necessary to de-embed the undesired package parasitic elements of a pack-
aged transistor (Fig. 4.3) at least on the output side. It must be said that if
the transistor is internally prematched, the internal matching should equally be de-
embedded. In this regard, employing unmatched transistors is more convenient for
the design of a Chireix PA.
Harmonic shorted terminations: The presented analysis in Chapter 2 assumed
sinusoidal voltage waveforms at the Chireix combiner inputs. This can be ap-
proached by short-circuiting the harmonics. In fact, the inclusion of a 2nd harmonic
termination at the right reflection angle can account for around 20% increase in the
efficiency regardless whether the class is E, C or F [53]. Although about 10% can be
gained with a proper 3rd harmonic termination [53], the class-B current waveform’s
odd-overtones free content suggests that no short circuits are required for the odd
harmonics. This constitutes a significant leverage in the output network design.
Additional efficiency can theoretically be gained by properly terminating additional
higher order (even) harmonics. In practice, the complexity of the matching networks
becomes an issue especially that the obtained reward is minor. It must be noted
that the care required for harmonic terminations reenforces the choice of using un-
matched transistors. Otherwise an internal prematch transformation could hinder
the realization of the optimal harmonic terminations. In the design Chapter, it is
seen how the compensation of the package’s output parasitics and the 2nd harmonic
short are codesigned.
37
4 Practical Considerations for Chireix PA Design
Output capacitance compensation: In contrast to package parasitics, the out-
put capacitance is a nonlinear component (Fig. 4.4). Under large RF drives, which
is the dominant regime when operating a Chireix PA, the intrinsic HEMT elements
become dependent on the extrinsic voltages and not uniquely on the bias conditions.
At the time the Chireix PA was invented, vacuum tubes (triodes, tetrodes...) were
the only choice for amplification as the transistor as a device did not appear until
more than a decade later. Since the interelectrode capacitances of a specific tube,
most significantly the grid to cathode capacitance, are basically solely dependent on
its geometrical characteristics [54], the compensation task required at HF was more
or less not complicated. Unlike that, the nonlinear nature of the output capacitance
of a GaN HEMT introduces a compensation milestone. The task of completely
resonating it out and getting closer in shape to the ideal topology (Fig. 2.5) is not
straightforward. One could think for instance of some form of dynamic matching
by introducing active elements in the output matching path. Unfortunately, this in
turn brings other complications5.
In light of that, the ideal Chireix analysis is refined in a basic manner, leading to a
better understanding of a transistor-implementation of the Chireix PA. Since the network
parameters [51] were developed for analyzing linear systems or nonlinear systems in their
linear regime operation, the obtained Y representations cannot be directly applied to
the analysis of the Chireix PA. The extrinsic voltage dependence of the intrinsic HEMT
elements under large RF drive become even exacerbated by operation in class-B. As the
transistor is continuously toggling between ON and OFF states, the concept of a single
equivalent circuit Y representation of it would collapse. An alternative option to couple
the transistor model into the Chireix architecture is to define harmonic admittances. In
fact, the complexity and unfamiliarity of a nonlinear time-variable impedance/admittance
is mitigated by applying the Fourier series analysis. This allows to restore a “fixed”
admittance albeit relating harmonic components of the output current and voltage. In
the following, an expression for the nonlinear capacitance Cout is developed.
4.4.1 Nonlinear Output Capacitance
The equation linking the current ic and voltage vc across a nonlinear Cout is given by
ic d
dtpCout vcq Cout dvc
dt vc dCout
dt(4.14)
where all of the entities ic, vc and Cout vary with time (the ptq is dropped for simplicity).
Two essential cases can be distinguished:
5Subsection 3.4.1 briefly described the use of active elements in the combiner.
38
4.4 Practical Chireix Analysis
Chireix combiner with short circuits at the harmonics
This scenario represents the ideal class-B case being adapted to a transistor implementa-
tion of the Chireix PA. The higher order harmonic content of the current source cycles
through the short circuits, leaving no high order harmonic current content through Cout.
The drain voltage higher order harmonic content gets nullified as well. This results in the
capacitor voltage and current having the forms:
icptq A cospω0tBq (4.15a)
vcptq VDC V0 sinpω0t θq (4.15b)
With that, a solution to the differential equation (4.14) can now be pursued. The solution
can be found to be:
Coutptq Qres Asinpω0tBq
ω0
VDC V0 sinpω0t θq (4.16)
where Qres is a constant following from integration. The designation of this constant
by Qres stems from the form of the capacitance (4.16) where a voltage dimensioned de-
nominator implied a charge dimension for the numerator given in Coulomb. Indeed the
numerator is the indefinite integral of icptq (4.15a), representing a variable charge across
Cout. For Cout to retain a meaningful positive value, Qres has to be ¡ Aω0
. Although (4.16)
gives an adequate representation of the output capacitance in real time, it is of higher
interest to try to seek for it a frequency domain representation. The complete answer can
be found by applying the Fourier transform to (4.16):
Coutpfq F pCoutptqq (4.17)
Unfortunately, the raw solution for that, although might have a closed-form expression
[55], is extremely complex to handle. A simplified approach can hence be investigated
with the goal of determining what factors affect the fundamental frequency component
of Cout. The first simplification relies on the understanding that the output capacitance
decreases with increasing drain voltage, leading to a Qres " Aω0
. The second comes by
inspection that θ won’t be affecting the magnitudes in the frequency domain. These
together yield the following Cout simplification for further analysis:
Coutptq Qres
VDC V0 sinpω0tq (4.18)
Using the obtained expression, an illustrative example reflecting the parameters of a 30 W
GaN HEMT (Table 4.2) is shown in Fig. 4.5a. The corresponding more familiar form
of the output nonlinear capacitance as a function of the drain or capacitor voltage vc is
plotted in Fig. 4.5b. By noting that this function is periodic, the Fourier series ex-
39
4 Practical Considerations for Chireix PA Design
Table 4.2: Parameters reflecting an exemplary 30 W GaN transistor.
f0 T0 Qres VDC V0
2140 MHz 0.4673 ns 4e-11 C 28 V 26 V
0 0.2 0.4 0.6 0.80
5
10
15
20
t (ns)
Cou
t(p
F)
T0
(a)
0 10 20 30 40 50 600
5
10
15
20
vc (V)Cout(pF)
(b)
Figure 4.5: Cout stemming from simplified circuit analysis for the harmonically shorted
case (a) as a function of time and (b) as a function of variable capacitor (or
drain) voltage for the parameters given in Table 4.2.
pansion can be applied, instead of the transform, to determine its fundamental frequency
component Fourier coefficients a1 and b1. Additionally a0 is determined. The derivation
is summarized in appendix C. It was found that
CoutpDCq QresaV 2
DC V 20Coutpf0q
2Qres
V0
VDCaV 2
DC V 20
1
(4.19a)
(4.19b)
To verify the validity of the obtained expressions, the numerical FFT algorithm is applied
to (4.18) in MATLAB. Both results are plotted as a function of the drain’s DC bias VDC
(Fig. 4.6a) and against the fundamental voltage magnitude V0 (Fig. 4.6b). The results
in Fig. 4.6b shall not be confused with the understanding of a decreasing Cout versus an
increasing drain voltage, since these point out to the DC and fundamental components of
the nonlinear output capacitance and not to Coutptq (Fig. 4.5).
Having reached that, it can be argued that the presented results are ungeneralized namely
due to the undertaken simplification Qres " Aω0
. To overcome this uncertainty, an alter-
native complementary path for inspecting the nonlinear output capacitance is presented.
Cout is extracted from the nonlinear LS model of Cree’s CGH27030F GaN HEMT [47] used
for the Chireix PA realization. The extraction is based on the method presented in [50].
The result is plotted in Fig. 4.7 as a function of the gate and drain bias voltages vgs and
40
4.4 Practical Chireix Analysis
25 30 35 40 45 50 550
1
2
3
4
5
6
VDC (V)
|Cout|(pF)
DC − AnalyticalDC − FFTf0 − Analyticalf0 − FFT
(a)
14 16 18 20 22 24 26 280
1
2
3
4
5
6
7
V0 (V)
|Cout|(pF)
DC − AnalyticalDC − FFTf0 − Analyticalf0 − FFT
(b)
Figure 4.6: Parametric Cout’s DC and fundamental components for the simplified harmon-
ically shorted case (a) with respect to VDC and (b) with respect to V0 with the
fixed parameter values as given in Table 4.2.
vds. As can be seen, the output capacitance is also a strong function of the gate voltage.
−10−9−8−7−6−5−4−3−2−10
01020304050607080
0
10
20
30
vgs
(V)vds
(V)
Cou
t (pF
)
FittedExtracted
Figure 4.7: Extracted (dotted) and fitted (colored surface) CGH27030F’s Cout.
By comparison to (4.16), it can be speculated that the factor A could be exhibiting some
gate voltage dependency. Although the investigation of a simplified Cout can lead to some
useful results [56], taking into account the gate bias effect is recommended especially for
LS applications where for instance the Chireix PA transistors are biased in class-B and
operated in full-swing mode. With that in mind an empirical form of the extracted Cout
is pursued. The fitted expression taking into account the cross-coupling between vgs and
vds was based on the equation models presented in [57] with minor modifications:
Cout a 1 tanhpbvgs cv2gsq 1 tanhpdvgsvds evds fv2
dsq g ppFq (4.20)
The constants after fitting using MATLAB are summarized in Table 4.3. The surface fit
41
4 Practical Considerations for Chireix PA Design
Table 4.3: Empirical Cout constants in (4.20) for the CGH27030F HEMT.
Figure 4.9: Cout’s first three spectral components as a function of the parameter V0.
This makes the fundamental component of the nonlinear output capacitance significantly
dependent on it (Fig. 4.10).
0 1 2 3 4 5 6 7 8 9 100
0.5
1
1.5
2
2.5
3
3.5
Vds2 (V)
|Cout(f0)|(pF)
Figure 4.10: Cout’s fundamental component for the nonharmonic design case.
4.4.2 Implications on Chireix PA Design
The previous analysis points out that the nonlinear output capacitance component at f0
is not only dependent on the DC bias settings, but also on the magnitudes of the har-
monic voltages. The analysis suggests that the output capacitance at the fundamental
can uniquely be constant if the voltage magnitudes of the harmonics are constants too. At
the fundamental, a constant input drive level and a low drain-to-source resistance helps
stabilizing the fundamental voltage magnitude at the output. For the latter, GaN is a
43
4 Practical Considerations for Chireix PA Design
suitable choice [42]. As the transistor’s nonlinear behavior in class-B will result in the
generation of even only overtones, a constant and hence “compensatable”Coutpf0q
can
be guaranteed by shorting at least the 2nd harmonic in the combiner so that Vds2 0 for all
outphasing θ angles. Otherwise leaving it unshorted would result in a floating Vds2 as the
outphasing angle varies. Furthermore, the output capacitance value to be compensated
is not the one obtained from small-signal analysis: while Coutp3.8 V, 38 Vq 2.17 pF
(Fig. 4.7),Coutpf0q
hints to a higher value depending on the selected outphasing LS
drive level magnitude (Fig. 4.9). It can be noticed that as V0 decreases, i.e. approach-
ing small-signal operation, the converging to 2.17 pF DC component will prevail (Fig. 4.9).
On the other hand, it has been observed using GaN HEMTs from SEDI [58] that leaving
out the 2nd harmonic termination together with modulating the input drive level allows to
reconstruct the original Chireix PAE curve [33, 34]. In light of the discussed understanding
of Cout, this behavior can be interpreted by the following mechanism: asCoutpf0q
becomes
a variable of the harmonics too, changing the input drive level will result in a compensatedCoutpf0q albeit occurring each time at a different outphasing angle θ. If that happens to
coincide with the transistor characteristics, the compensation points will form a continuity
allowing in principle to digitally recapture the original Chireix PAE curve by selecting
the proper drive levels and outphasing angles sets (Fig. 4.11). Furthermore, a remarkable
correlation when it comes to the ideal Chireix peaks distance and simulated IAMO ones
is noticed (Fig. 4.11 and Table 4.5). It must be said that the implementation of such a
variant requires the availability of solid LS models that enable describing the transistor
characteristics in vast areas of load impedances and voltages.
30 32 34 36 38 40 42 44 46 48 500
10
20
30
40
50
60
70
Pout (dBm)
PA
E (
%)
(a)
30 32 34 36 38 40 42 44 46 48 500
10
20
30
40
50
60
70
Pout (dBm)
PA
E (
%)
(b)
Figure 4.11: IAMO PAE LS simulations with (a) θc 15 and (b) θc 30 designs.
44
4.4 Practical Chireix Analysis
Table 4.5: Peaks distances comparison for two different designs.
Peaks distance comparison θc 15 θc 30
Chireix theoretical (2.58) 11.4 dB 4.8 dB
LS IAMO simulations 10.8 dB 4.1 dB
4.4.3 Load Modulation
So far, it has been discussed that a main difference with the original analysis is the
presence of the output capacitance. In order to move one step closer to a transistor-
based implementation, the Chireix topology is slightly modified to include the output
conductance and capacitance of each transistor. As can be noted from (2.55a) and (2.55b),
the expression of Yi does not depend on V0. Under the assumption that the voltage is
sinusoidal, accounting for the output conductance and capacitance by adding them in
parallel can be safely made. This allows to obtain the new admittance expressions instead
of rederiving them. Assuming an unpackaged transistor for now, the block to be inserted
between the ideal current sources and the Chireix combiner is shown in Fig 4.12a.
(a)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
3.0
4.0
5.0
10 20
20
-20
10
-10
5.0
-5.0
4.0
-4.0
3.0
-3.0
2.0
-2.0
1.8
-1.8
1.6
-1.6
1.4
-1.4
1.2
-1.2
1.0
-1.0
0.9-0
.9
0.8-0
.8
0.7-0
.7
0.6-0
.6
0.5-0
.5
0.4
-0.4
0.3
-0.3
0.2
-0.2
0.1
-0.1
Theta (0.000 to 89.000)
Gam
ma
1G
amm
a2
(b)
Figure 4.12: (a) Blocks inserted between the Chireix ideal current sources and Chireix
combiner and (b) transformed loci at die’s plane.
In order to mimic the original Chireix combiner as much as possible, it is then required to
compensate for each of the output capacitances with a parallel inductance inserted in the
combiner such that its admittance is equal to jωCoutpf0q
. With that, the admittances
45
4 Practical Considerations for Chireix PA Design
seen by the transistors can be written as
YTR1 1 cosp2θq2ZL
jsinp2θq
2ZL
jsinp2θcq
2ZL
jωCoutpf0q
(4.23a)
YTR2 1 cosp2θq2ZL
jsinp2θq
2ZL
jsinp2θcq
2ZL
jωCoutpf0q
(4.23b)
This implies some transformation of the Chireix loci on the Smith-chart from the location
seen in Fig. 2.7 to the one depicted in Fig 4.12b.
4.5 Bandwidth Considerations
As the outphasing concept relies on encoding the amplitude modulation into additional
phase modulation, some bandwidth expansion is expected after the SCS. This is man-
ifested by the arccos function, that is ideally used to generate the outphasing angle θ
(2.3), taking the amplitude of the original signal as its independent variable. Indeed,
calculations show how the spectrum of a W-CDMA 5 MHz-wide input signal considerably
expands after splitting it into two outphasing signals (Fig. 4.13a). This was confirmed
by measurements6 as seen in Fig. 4.13b. The obtained outcome has been reenforced by
inspecting the spectrum of a 2-Carrier W-CDMA 20 MHz-wide signal (Fig. 4.14).
In order to study the impact of the bandwidth expansion on the system requirements, the
instantaneous frequency [59, 60] of the individual outphasing signals is first considered.
−15 −10 −5 0 5 10 15Instantaneous Frequency Shift (MHz)
Num
ber
of O
ccur
ence
s
(b)
Figure 4.15: (a) Instantaneous frequency shift for the individual outphased signals from
a 5 MHz W-CDMA signal and (b) its zoomed view.
47
4 Practical Considerations for Chireix PA Design
neous frequency is equal to the sampling frequency of the baseband input signal, which
amounted in this case to 307.2 MHz. Given that the broadband matching of any load
impedance is subject to limitations emanating from the bounded value of the integral in
[61],8»0
ln1
|Γpωq|dω (4.25)
the expansion would translate into a challenging matching problem7. As a consequence,
designing the PA cores to cope with the considerable full bandwidth expansion due to
outphasing is extremely hard at a center frequency of 2.14 GHz, if not impossible. Taking
however a zoomed look at the instantaneous frequency plot (Fig. 4.15b), it can be noted
that the bell shaped distribution falls mostly in a much narrower range than the fully
expanded one. For the given three signal configurations, the percentage of outphased
data contained in a presumably limited frequency range supported by the PA cores is
calculated and depicted in Fig. 4.16. It can be seen that 95 % or more of the outphased
data in terms of instantaneous frequency occurrences is contained in respectively about
7 MHz, 20 MHz and 60 MHz BW of the outphased signals. Subsequently, the impact of
having a restricted BW support from the PA cores can be studied.
100
101
102
103
75
80
85
90
95
100
PAISupportingIBWI(MHz)
Pre
serv
edIIn
foI(
D)
05MHzIW-CDMA10MHzIW-CDMA20MHzIW-CDMA
Figure 4.16: Preserved outphased data as a function of the PA cores’ supported BW.
4.5.2 Modulation Accuracy
While the instantaneous frequency gives a statistical idea reflecting the percentage of
outphased data in a given BW in terms of frequency occurrences, a more discrete and
standardized metric to consider would be the error vector magnitude (EVM). The EVM
is employed in many communication standards as a figure-of-merit of the transmitter’s
7The reflection factor can be minimized to a certain limit in a given frequency band.
48
4.5 Bandwidth Considerations
modulation accuracy [62, 63, 64, 65], i.e. the fidelity in transmitting a given signal. The
EVM can be computed using
EVMrms
gffe°Nk1
pIk rIkq2 pQk rQkq2
°N
k1pI2k rQ2
kq 100 (4.26)
where
Ik is the in-phase component of the kth symbol in the reference signal,
Qk is the quadrature phase component of the kth symbol in the reference signal,rIk is the in-phase component of the kth symbol in the tested/transmitted signal,rQk is the quadrature phase component of the kth symbol in the tested/transmitted signal,
N is the vector length of the reference signal [66].
To check how the EVM gets affected upon BW truncation of the outphased signals, the
Gedankenexperiment represented by Fig. 4.17 is performed: an ideal bandpass filter with
adjustable BW is equally applied to each of the outphased signals. At different desired
checkpoints along the flow of the signals, “EVM-meters” are placed as seen in Fig. 4.17.
Two “PAR-meters” are introduced as well. An illustration of a truncated outphased sig-
nal in frequency domain that corresponds to the 2-Carrier W-CDMA 20 MHz-wide signal
configuration is depicted in Fig. 4.188. By adjusting the bandpass width, the virtual
SCS
(BB I and Q)
EVM
EVM
PAR
PAR
s1
EVM
BW
BWs2
s1Filtered
s2Filtered
ssL
Figure 4.17: Outphased signals BW truncation virtual test setup.
setup allows to evaluate these metrics as a function of the Chireix PA supporting BW.
EVM at the checkpoint s1Filtered (with reference to s1) is plotted in Fig. 4.19. Applying the
95% rule (EVM1 5%) leads to the minimum required BWs of approximately 32 MHz,
75 MHz and 187 MHz for the respective signals, which is significantly more demanding
than what was estimated using the instantaneous frequency metric in the previous sub-
section. Comparing these to the original BWs of 5 MHz, 10 MHz and 20 MHz, it is found
that the expansion factor varies between 6.4 and and 9.4 accordingly.
8Due to the similar properties of the two outphased signals, path 1 is only illustrated.