Advanced SAR ADCs Efficiency, Accuracy, Calibration & References Pieter Harpe Eindhoven University of Technology Eindhoven The Netherlands Pieter Harpe TU/e Outline Introduction Selected literature examples (1997 2017) Detailed design examples Conclusions & Outlook 2 Pieter Harpe TU/e Outline Introduction Selected literature examples (1997 2017) Detailed design examples Conclusions & Outlook 3 Pieter Harpe TU/e ADC Architectures over Time C. Hammerschmied, Q. Huang 1 m CMOS 10b, 200kS/s 109pJ/conv.step 4 Data from B. Murmann, Performance Survey S.-E. Hsieh, C.-C. Hsieh 90nm CMOS 11b, 600kS/s 0.4fJ/conv.step SAR: rapid development during last decade
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Outline - eit.lth.se · Pieter Harpe TU/e Outline Introduction Selected literature examples (1997 2017) Detailed design examples A 1nW 1kS/s 10bit SAR ADC An oversampled 12/14b SAR
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Advanced SAR ADCsEfficiency, Accuracy, Calibration & References
Pieter Harpe
Eindhoven University of TechnologyEindhoven The Netherlands
Pieter Harpe TU/e
Outline
Introduction
Selected literature examples (1997 2017)
Detailed design examples
Conclusions & Outlook
2
Pieter Harpe TU/e
Outline
Introduction
Selected literature examples (1997 2017)
Detailed design examples
Conclusions & Outlook
3 Pieter Harpe TU/e
ADC Architectures over Time
C. Hammerschmied, Q. Huang 1 m CMOS 10b, 200kS/s 109pJ/conv.step
ISSCC 2007 Craninckx, Van der Plas: 9b 0-50MS/s SAR ADCCharge-sharing DAC; Dynamic circuitry (power-speed adaptability)
ISSCC 2008 van Elzakker, et al.: 10b 1MS/s SAR ADC4.4fJ/conversion-step, adiabatic DAC, efficient comparator, asynchronous timing
Pieter Harpe TU/e
Low Power SAR ADCs
Minimize power & Maximize SNR / linearity
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Comparator- Noise
DAC- Mismatch- Resolution
Circuit Algorithm Calibration,Error-shaping
Layout,Switching scheme
Pieter Harpe TU/e
Comparator: Efficient Circuits
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van Elzakker, et al.(ISSCC 2008)
Liu, et al.(ISSCC 2015)
Bindra, et al.(ESSCIRC 2017)
Pieter Harpe TU/e
Comparator: Efficient Algorithms
Redundancy: relax comparator in most cycles
2 comparators Giannini, et al. (ISSCC 2008)1 comparator, 2 modes Harpe, et al. (ISSCC 2012)
Oversampling or noise-shapingNoise shaping Fredenburg, Flynn (ISSCC 2012)Selective oversampling Harpe, et al. (ISSCC 2013)Adaptive averaging Morie, et al. (ISSCC 2013)
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Coarse (N k) Fine (k + 1)(with over range)
Pieter Harpe TU/e
DAC: Switching SchemesSplit capacitor switchingGinsburg, et al. (VLSI 2006)Monotonic capacitor switchingLiu, et al. (JSSC Apr. 2010)Merged capacitor switchingHariprasath, et al. (E. Let. Apr. 2010)Vcm-based switchingZhu, et al. (JSSC June 2010)Charge average switchingLiou, et al. (ISSCC 2013)Detect-and-skip, aligned switchingTai, et al. (ISSCC 2014)Swap-to-resetLiu, et al. (ESSCIRC 2016)
etcEspecially useful for higherresolutions (larger CDAC)
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VREF GND
C0C1C2b0b1b2
Different bit transitions Different energye.g. 011 to 100 transition = costly
Pieter Harpe TU/e
DAC: Capacitor Implementation
kT/C noise limit (ignoring mismatch):
<10b ADCs usually overdesigned>10b ADCs require a lot of units and large Ctotal
MOMCAPArea efficientEasy to wire in arrayCmin < 0.5fF
Harpe, et al.(ISSCC 2010 /JSSC Jul. 2011)
Pieter Harpe TU/e
DAC: Mismatch Non-Linearity
Calibration: measuring and correcting errors
Rotation / DEM / Mismatch error shaping
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VREF GND
C0C1C2b0b1b2
Ding, et al. (ISSCC 2015)
Digitalcalibration
loop
VREF GND
C0C1C2b0b1b2
Rotation: Distortion NoiseLiu, et al. (ESSCIRC 2016)
1 Z-1 error shapingShu, et al. (ISSCC 2016)
Pieter Harpe TU/e
Outline
Introduction
Selected literature examples (1997 2017)
Detailed design examplesA 1nW 1kS/s 10bit SAR ADCAn oversampled 12/14b SAR ADCA 13b SAR ADC with background calibrationA 10b SAR ADC with a DAC-compensated reference
Conclusions & Outlook15 Pieter Harpe TU/e
10bit SAR ADC
Based on ADC architecture as in [1]Self-synchronized ADC Only need clock at 1kS/sClock boosting Linearity & low-voltage operationDynamic circuits only Power scales down with Fsample
Small unit caps, custom design (250aF)Total Cin = 300fF (with parasitics)
3b Unary / 7b Binary segmentationImproves power and DNL
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7b binary3b unary
Pieter Harpe TU/e
Binary:
Unary:
Impact of Unary/Binary Segmentation
Less switching elements lower power and DNLNote: advantage depends on switching scheme
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1 1 1 1 1 1 1
4 2 1
4
2
Code
Code6 switchingelements
Code
Code2 switchingelements
1 1 1 1
1 1
Pieter Harpe TU/e
Comparator: Efficient Pre-amplifier
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van Elzakker, et al.(ISSCC 2008)
Liu, et al.(ISSCC 2015)
Pieter Harpe TU/e
Digital Logic: Low-Speed Operation
Technology scalingActive power , Leakage power
Power at low speed limited by leakageOptimized by: Low VDD, high Vt transistorsReduce number of gates in the logicManual design rather than synthesized logic
Leakage 0.15nWDAC is about 20% of total power consumption
Power efficiency1.5fJ/conversion-step at 100kS/s1.7fJ/conversion-step at 1kS/s
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88nW @ 100kS/s
1nW @ 1kS/s
Pieter Harpe TU/e
Outline
Introduction
Selected literature examples (1997 2017)
Detailed design examplesA 1nW 1kS/s 10bit SAR ADCAn oversampled 12/14b SAR ADCA 13b SAR ADC with background calibrationA 10b SAR ADC with a DAC-compensated reference
4X oversampling (i.e. 4X power) +6dB SNRHelps for thermal noise and quantization noise,but not for 1/f noise or distortion
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fsample/2
fsample
Nyquist-rate
4X OSR
noise
noise
signal
signalfsample = 4fsample
Pieter Harpe TU/e
System Level Chopping
fchop = fsample / 2Negligible power/area overhead
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Pieter Harpe TU/e
Chopping Result
1/f noise and distortion modulated with fchop
fchop = ½ fsample and OSR 2X1/f noise and even-order HD out of baseband
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fsample/2
Without chopping
fsample/2
With chopping
Baseband for OSR = 2X
distortionsignal
1/f noise
Pieter Harpe TU/e
Majority Voting
Analog scaling: 4x Ecmp 2x lower Vnoise
Digital majority voting (oversampling / averaging):Repeat the same comparison k times (10110)Majority voting on k samples to decide ( 1)Effectively reduces input-referred noiseMajority-voting on 5 samples 4x analog scaling
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Vin
Vnoise
Vin
Output probability
0
1P1P0
0 0
Vnoise
Ecmp
Pieter Harpe TU/e
Data-Driven Noise Reduction (DDNR)
Only a few comparator decisions are noise criticalSelective majority voting for critical cases only
Detailed design examplesA 1nW 1kS/s 10bit SAR ADCAn oversampled 12/14b SAR ADCA 13b SAR ADC with background calibrationA 10b SAR ADC with a DAC-compensated reference
Conclusions & Outlook41 Pieter Harpe TU/e
6.4MS/s 13b SAR ADC in 40nm CMOS
ULP radio receiver
Problem:13b intrinsic linearity Power and area hungryCalibration Often also power and area hungry
If code A is detected @ 15th cycle, then:16th cycle is performed, repeating 15th cycle, but:
DAC code is switched from A to BSign of the error is determined by C15C16
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code A ( code B (
Comparator outputs:
Pieter Harpe TU/e
Detailed 13b ADC Architecture
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Comparator correctionDAC mismatch correction
Detection Only sign detection necessaryBackground, low activation rateAnalog correction = low power
Pieter Harpe TU/e
Die Photo and Power Breakdown
Calibration is low cost4% of chip area5% of power consumption
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500 m 135 m
Calibration logic
Pieter Harpe TU/e
Code
With comparator and DAC calibrations
Code
INL(
LSB)
DN
L(LS
B)S&H non-linearity
Measured Static Performance
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Without calibrationIN
L(LS
B)
DN
L(LS
B) Comparatoroffset error
With comparator calibration only
INL(
LSB)
DN
L(LS
B)DAC mismatch error
Pieter Harpe TU/e
Measured Spectrum @ 6.4MS/s
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Without calibration
Pow
er(d
BFS)
With comparator calibration only
Pow
er(d
BFS)
Spurs due to DAC mismatch
With comparator and DAC calibrations
Pow
er(d
BFS)
HD3 due to S&H distortion
20dB
Input Frequency (MHz)
Pieter Harpe TU/e
ADC Performance Benchmark
All ADC papers in ISSCC/VLSI 1997-2014 with fs > 1MS/sSource: http://web.stanford.edu/~murmann/adcsurvey.html
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5.5fJ/c.s
Pieter Harpe TU/e
ADC Performance Summary[2] [4] [5] [8] This
workTechnology (nm) 130 28 28 65 40Resolution (bit) 12 14 14 14 13Sample rate (MS/s) 22.5 200 80 0.032 6.4Power (µW) 2790 2300 1500 0.352 46Nyquist SNDR (dB) 70.11 65 66 69.7 64.1FOMW_Nyq. (fJ/c.s) 50.8 7.9 11.5 4.4 5.5FOMS_Nyq. (dB) 165.9 171.4 170.3 176.3 172.5Calibration Off-chip Off-chip On-chip N.A. On-chipCal. Circuit Area (mm2) 0.01* Not incl. Included N.A. 0.0026Cal. Circuit Power (µW) 200* Not incl. Included N.A. Included
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*Estimated
Pieter Harpe TU/e
Outline
Introduction
Selected literature examples (1997 2017)
Detailed design examplesA 1nW 1kS/s 10bit SAR ADCAn oversampled 12/14b SAR ADCA 13b SAR ADC with background calibrationA 10b SAR ADC with a DAC-compensated reference
Conclusions & Outlook53 Pieter Harpe TU/e
SAR ADC is Energy-
Reference buffer required for the DACCan be significant in chip area (A) or powerconsumption (P)
0
1
2
3
4
5
[9] C.-C. Liu, et al., JSSC 2016
[8] M. Inerfield, et al., VLSI 2014
[7] W.-H. Tseng, et al., JSSC 2016
Aref buf /AADC
Pref buf /PADC
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Liu, et al. (ESSCIRC 2017)
Pieter Harpe TU/e
Charge-Redistribution DAC
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Reference Buffer
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Pieter Harpe TU/e
Passive Driving by CDEC
Large CDEC Approximates ideal binary search
Smaller CDEC Non-binary DistortionCan be solved with DAC compensation
57 Pieter Harpe TU/e
DAC-Compensated ReferenceIf CDEC is not largeVREF,DEC drops and depends on the code (Di)
Compensation DAC for 3MSBsCompensation capacitors:
MSB requires no compensation (code-independent loss)MSB-1 compensation depends on first 2 decisions (00, 01, 10, 11)Calculated analytically with extracted parasitic informationSame capacitor type as the DAC array for matchingTotal compensation capacitance ~1% CT Low power + small area
VDACP
GND
VDACN
VREF
C011 C101
VREF
GND
C01 C10 C11 C00
C01 C10 C11 C00
C001 C111
Compensation for the2nd switching step
C100 C010 C110 C000
Compensation for the 3rd
switching step
C011 C101 C001 C111C100 C010 C110 C000
C1 C2
9b binary DAC
C1
C1
C1 C2
C2
C2
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Pieter Harpe TU/e
Die Photo in 65nm CMOS
CDEC, pre-charger and DAC-compensationAdd 10.1% chip area to the SAR ADCCDEC takes most of this 10.1%
Static PerformanceWithout and with DAC compensation
0 1023-20246
[-1.0LSB, 3.3LSB][-1.0LSB, 5.0LSB]
Code
0 1023-5
0
5
[-3.2LSB, 3.2LSB]
[-4.2LSB, 4.2LSB]
Code
0 1023-2-1012 No comp.
Code
0 1023-2-1012 3b comp.
Code
0 1023-2-1012 6b comp.
Code
0 1023-2-1012 9b comp.
Code
Behavioral simulationsChip measurements
65 Pieter Harpe TU/e
Power and Area Overhead
CDEC, pre-charger and DAC compensation:10.8% more power to the SAR ADC10.1% chip area to the SAR ADC
0
1
2
3
4
5
This work
Aref buf /AADC
Pref buf /PADC
[9] C.-C. Liu, et al., JSSC 2016
[8] M. Inerfield, et al., VLSI 2014
[7] W.-H. Tseng, et al., JSSC 2016
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Pieter Harpe TU/e
ConclusionsA passive DAC-compensated driving scheme is proposed
Continuous-time buffer Duty-cycled buffer Low powerDAC compensation enables small CDEC Small areaCombines the advantages of CR and CS DACs:
DACarchitecture
Precision(noise,
parasitics)
Usereference
buffer
Buffer cost(area & power)
Charge-redistribution Simple Good Frequently High
Charge-sharing Complex Poor Only during
tracking Low
This work Simple Good Only duringtracking Low
67 Pieter Harpe TU/e
Outline
Introduction
Selected literature examples (1997 2017)
Detailed design examples
Conclusions & Outlook
68
Pieter Harpe TU/e
Conclusions & Outlook
Techniques for low-power / noise / linearityMany different solutions (circuit, algorithm, A / D)Still substantial progress; not yet at fundamental limits
OutlookRecent years show a shift to SAR-based rather thanpure SAR ADCs (more speed, more resolution)Simple SAR ADCs excellent for ~6-12b, DC-100MS/sMore attention needed for surrounding circuits