Out-of-Order OpenRISC Stage 1: Implementation of OpenRISC on XUP5 board Project Characterization By: Vova Menis-Lurie Sonia Gershkovich Advisor: Mony Orbach.

Out-of-Order OpenRISCStage 1: Implementation of OpenRISC on XUP5 board

Project Characterization

By: Vova Menis-Lurie

Sonia Gershkovich

Advisor: Mony Orbach

Spring Semester 2012

Content:

1.Project Overviewa. Goalsb. Background and the challenge

2. Specificationsa. OpenRISC 1200b. Working Environment

3. Workflow4. Timetable – Gantt Chart

Project Overview Project Goals

Primary Goal:

• Implementation of Out-of-Order execution engine on the base of

OpenRISC CPU

Primary Goal – semester A:

• Creating a complete system-on-a-chip based OpenRISC, on XUP5

board, as a platform for further work, including:

• Choosing Configuration for the CPU

• Simulation and Synthesis

• Implementation

• Debugging

• Testing the system

Project Overview Our Goals• Understanding of the fundamentals of computer architecture

• Acquiring computer designer’s skills, including experience in CPU

design, computer organization , hardware implementation and

debugging.

• Learning and practicing Verilog HDL (OpenRISC implementation

language)

Project Overview Background

• OpenRISC is an OpenCores community project aiming to develop a

series of general purpose Open Source RISC architectures

• Only one architecture has been released till now – OpenRISC 1000

• Configurable implementation, written in Verilog HDL has been

introduced - OpenRISC 1200, supporting Basic Instruction Set, DSP

extension and FP extension.

Our challenge is to configure the convenient architecture

implementation for XUP5 board, and create the

environment to ensure proper work and testability of the

system.

The OpenRISC 1200

• Starting Configuration for

Project (may be changed)

• Original Unit Scheme

The OpenRISC 1200

IMMU

PIC

DC

CPU

IC

DWB

IWB

DU

PM

TT

I/O Signals

• Data Wishbone Signals

• Instruction Wishbone Signals

• System Signals

• Optional Units Signals

Working Environment – HardwareXUP5 Board

OR1200 on XUP5

Working Environment - Software• Project Management

- ISE (optional – PlanAhead for special tasks)

• Simulation

- ISim(ISE);

- or1ksim (optional, requires Unix OS)

-Icarus (optional)

• Synthesis

- XST(ISE)

• Debugging:

- ChipScope

- or1ksim (optional, requires Unix OS)

Workflow:1. Choosing the configuration: what optional/configurable parts we will include

(interrupts/cache/debug unit, etc.).

2. Complete system compilation, including CPU and buses and other parts according to section 1.

3. Synthesis and post-synthesis simulation, pin-assignments.

4. Burning the system to the chip and basic debugging.

5. Choosing a way to test the system, for example creating simple C program and executable file to be run on the OR1200 .

6. After verifying the design, go ahead to creating and implementation OoO unit (semester B).

Hello world!

Project Timetable- Gantt Chart

Thank you!