OSI Physical Layer Components

7/27/2019 OSI Physical Layer Components

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OSI Physical Layer

Components

Digital and Data Communications



Data Communication Link

DTE DCE DCE DTE

RS -232C RS -232CTransmission

Medium



UNITS of COMMUNICATION LINK

UART –Transmitter side

needs 8 data bus lines for a 8-bit

parallel data to be converted into a

serial data stream. Idle line one/marking state

Some are onboard

Example – ACIA by Motorola



Options Found in UARTs

Character Type Option for an 8-bit bus

No. of Stop bits required

Use of parity type

Use of diff. data rates



ACIA

AsynchronousCommunications

Interface Adapter

by Motorola



MC6850 – Pin Assignment

CPU Pin Data Bus (D0-D7)

Control Bus (R/W, E, CS)

Address (RS, CS)

Other: IRQ

EIA-232 Pin

Data (Rx, Tx)

Control (RTX, CTS, DCD) Baud Clock (Rx CLK, Tx CLK)



Definition of ACIA Register Contents



ACIA Control Register (8-bit)

7 6 5 4 3 2 1 0

RX IR

RTS TX

IR

WORD

SIZE

STOP &

PARITY COUNTER DIVIDE



ACIA Control Register (8-bit)



UART Receiver

Use of Divide ratio

In half of the bit period where a start

bit can be verified

Use of shift register

Clock Skew



UART – Status Register

7 6 5 4 3 2 1 0

IRQ PE OVRN FE CTS DCD TDRE RDRF



Checking UART Performance

Use of Status Register

Use of TDRE

From buffer register to the shift-register

Use of RDRF

From shift-register to the buffer register

Use of OVRN failure to read the data from the buffer

register



Checking UART Performance

Use of Parity Error Use of Framing Error

Use of IRQ

2 conditions when IR functions at theControl register TDRE or RDRF is high

a received error has occurred



RS-232C Specifications

Most common by EIA

Uses a D-type 25 pin connector

uses voltage levels of +3 to +25 V (SPACE,data 0, on, green) and -3 to -25 V (MARK, data

1, off, red)



RS-232C Specifications

Cable impedance

330Ω min – Tx

7000 Ω max - Rx

Line Capacitance -2500 pf

50 pf/ foot limited to 100kb/s

Ideal for short distance less than 50ft



RS-232C

Since the link only uses about 7 wires, DB-9

connectors are frequently used now for seriallinks,



Handshaking Lines

DTE uses a signal called RTS on pin 4, while

DCE uses a signal called CTS on pin 5.

Data is transmitted from DTE to DCE on pin 2,

and from DCE to DTE on pin 3.



NULL Modem



RS-449

Uses D-type connectors 37-pin

9-pin

2 Mbps transfer rate Max length -200 feet

w/ loop-back feature



RS-422

balanced electrical interface

implemented using a D-type connector with 37pins – RS-449 specifications

logic 1 (Mark) is represented by the A outputbeing more negative than the B output.

logic 0 (Space) is represented by the A outputbeing more positive than the B output.



RS-423

unbalanced electrical interface

implemented using a D-type connector with 37pins – RS-449 specifications

low speed communications

generally operate at +/- 6 VDC and are

compatible with RS-232 devices



RS-423 very sensitive, capable of detecting

Mark/Space states at +/- 0.4 VDC

has separate Signal Grounds for transmittersand receivers

A binary one (Mark) is represented by aNegative voltage level

and a binary zero (Space) is represented by aPositive voltage level.





i.e. CCITT V.21 for 300 baud modems:

Originating Sending

Modem Modem1270 Hz 1 2225 Hz

1070 Hz 0 2025 Hz

loss of amplitude will not cause errors in transmission

FSK Modem



Limitations of FSK modems

Limited to the telephone BW (300-3kHz)

Limited data rates



a modulation technique to vary the phase of the sinewave (or carrier wave) to transmit ones and zeroes

A different phase shift, 0 to 360 degrees, is used to

transmit one or more bi ts

PSK Modem



Balanced Modulator

Permits the varying the phase of the fc

Logic 1 - 0° phase

Logic 0 – 180° shift

Basic Components:Transformers

Semiconductor device



DPSK

Is an alternative

form of PSKwherein the binaryinput info. iscontained in thedifferencebetween twosuccessivesignaling elementsrather than the

absolute phase

Q- Q signal phase

0 0 1 0°

0 1 0 180°

1 0 0 180°

1 1 1 0°



DPS d l i i



DPSK Modulator circuit

Q- Q M1 M2 LS

0 0 sin180° cos180° 360° or

0°

0 1 sin80° cos180° 180°

1 0 sin180° cos0° 180°

1 1 sin0° cos0°

360° or

0°

N N PSK M d



N-Nary PSK Modems

M = 2n

P = 360°/ M

C = BW (log2 M ) = BW x n

S= D/n

Uses bit-splitter shift registers

Where:

M- no. of symbols

n – no. of bits

per symbol

QPSK



QPSK

QPSK M d l i i



QPSK Modulator circuit

B A M1 M2 LS

0 0 -sin180° -cos270° 225°

0 1 sin0° -cos90° 315°

1 0 -sin180° cos270° 135°

1 1 sin0° cos90° 45°

QAM



QAM

Both Phase and Amplitude are varied Higher data rates over telephone BW

Ex. 9600 baud/(4 bits/symbols) = 2400 Hz sps

PSK D d l t



PSK Demodulators

Uses preamble before the data is received for clock recovery

using a ½ bit delay and XOR

The same ckt. w/ the Modulator but having a

different signal converter

DAC –modulator & ADC-demodulator

V 34 M d



V.34 Modems

ITU standard 33 Kbps

Uses QAM at 28.8 Kbps

Suitable for dial-up and leased lines

V 90 M d m



V.90 Modems

ITU standard 64 Kbps

Uses PCM at 56 Kbps

Suitable for dial-up and leased lines

OSI Physical Layer Components

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