OSCILLATION TEST METHODOLOGY FOR MOSFET CIRCUITS AKANKSHA GUPTA, ISHITA GUPTA, R ASHOK KUMAR, ARUN KUMAR 1 Chapter-1 INTRODUCTION Objective of the project To test fault in a MOSFET circuit using Oscillation Test Methodology. To improve the fault diagnosis and testability of the oscillation test methodology applied to a typical two-stage CMOS operational amplifier with Monte Carlo analysis. 1.1 Brief description With the growing use of analog circuits in commercial mixed-signal integrated circuits and systems, testing of analog integrated circuits is considered as one of the most important problems in analog and mixed-signal integrated circuit design. Analog circuits have traditionally been tested for critical specifications e.g., ac gain over a range of frequencies, common-mode rejection ratio, signal-to-noise ratio, linearity, slew rate, due to the lack of simple fault models. The functional testing usually results in longer test times because of redundant testing. It does not provide either a good test quality or a quantitative measure of test effectiveness or fault coverage. Reducing test time by optimizing the functional test set while achieving the desired parametric fault coverage has also been studied. However, the technique needs a reasonably large number of sample circuits for collecting the test data. Analog CMOS circuits have also been tested by varying the supply voltage in conjunction with the inputs. This technique aims to sensitize faults by causing the transistors to switch between different regions of operation. A ramped power supply voltage has been used to test faults in op-amp circuits. In an ac supply voltage has been used for improving the fault coverage. Although these techniques have achieved high fault coverage, the number of faults injected was quite small. Using this idea of varying supply voltage and combining it with supply current monitoring, larger analog circuits have been tested for short circuit fault detection. But the method suffers from the fact that, gate-source shorts that have negligible effect on supply current and gate-source shorts of transistors which do not switch their mode of operation to any applied stimulus, could not be detected. Other testing methods for analog circuits include dc testing, power-supply quiescent current (IDDQ) monitoring and digital signal processing techniques. On-chip design-for- test (DfT) technique has been suggested as one of the methods to reduce test costs in analog and mixed-signal integrated circuits. An overview of defect oriented testing and DfT optimization of mixed-signal integrated circuits is presented. Several DfT studies have been published, including work on a current mode DAC where test vectors are optimized and redundancies removed, on analog filters where the controllability and observability are improved to test a number of stages separately and on flash ADC. A functional self-test technique, based on using digital circuitry to generate functional test signals, has been extensively investigated. This technique also achieves substantial accuracy by moving analog signal measurement to the digital domain. However, one limitation of the functional test technique is that the functionality of the filter can only be guaranteed if all specifications have been tested. In absence of suitable models, one cannot
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OSCILLATION TEST METHODOLOGY FOR MOSFET CIRCUITS
AKANKSHA GUPTA, ISHITA GUPTA, R ASHOK KUMAR, ARUN KUMAR 1
Chapter-1
INTRODUCTION
Objective of the project To test fault in a MOSFET circuit using Oscillation Test Methodology.
To improve the fault diagnosis and testability of the oscillation test methodology
applied to a typical two-stage CMOS operational amplifier with Monte Carlo
analysis.
1.1 Brief description
With the growing use of analog circuits in commercial mixed-signal integrated circuits
and systems, testing of analog integrated circuits is considered as one of the most important
problems in analog and mixed-signal integrated circuit design. Analog circuits have
traditionally been tested for critical specifications e.g., ac gain over a range of frequencies,
common-mode rejection ratio, signal-to-noise ratio, linearity, slew rate, due to the lack of
simple fault models. The functional testing usually results in longer test times because of
redundant testing. It does not provide either a good test quality or a quantitative measure of
test effectiveness or fault coverage. Reducing test time by optimizing the functional test set
while achieving the desired parametric fault coverage has also been studied. However, the
technique needs a reasonably large number of sample circuits for collecting the test data.
Analog CMOS circuits have also been tested by varying the supply voltage in
conjunction with the inputs. This technique aims to sensitize faults by causing the transistors
to switch between different regions of operation. A ramped power supply voltage has been
used to test faults in op-amp circuits. In an ac supply voltage has been used for improving the
fault coverage. Although these techniques have achieved high fault coverage, the number of
faults injected was quite small. Using this idea of varying supply voltage and combining it
with supply current monitoring, larger analog circuits have been tested for short circuit fault
detection. But the method suffers from the fact that, gate-source shorts that have negligible
effect on supply current and gate-source shorts of transistors which do not switch their mode
of operation to any applied stimulus, could not be detected.
Other testing methods for analog circuits include dc testing, power-supply quiescent
current (IDDQ) monitoring and digital signal processing techniques. On-chip design-for-
test (DfT) technique has been suggested as one of the methods to reduce test costs in analog
and mixed-signal integrated circuits. An overview of defect oriented testing and DfT
optimization of mixed-signal integrated circuits is presented. Several DfT studies have been
published, including work on a current mode DAC where test vectors are optimized and
redundancies removed, on analog filters where the controllability and observability are
improved to test a number of stages separately and on flash ADC.
A functional self-test technique, based on using digital circuitry to generate
functional test signals, has been extensively investigated. This technique also achieves
substantial accuracy by moving analog signal measurement to the digital domain. However,
one limitation of the functional test technique is that the functionality of the filter can only be
guaranteed if all specifications have been tested. In absence of suitable models, one cannot
OSCILLATION TEST METHODOLOGY FOR MOSFET CIRCUITS
AKANKSHA GUPTA, ISHITA GUPTA, R ASHOK KUMAR, ARUN KUMAR 2
make general deductions about the ability of a circuit to satisfy all its functional
specifications by testing only a few specifications.
Quiescent current (IDDQ) testing is a cost effective test method to identify defects,
which cannot be identified by conventional functional tests and cannot be modelled by
classical fault models. IDDQ testing refers to the
integrated circuit (IC) testing method based upon measurement of steady state power supply
current. IDDQ stands for quiescent IDD, or quiescent power-supply current. The quiescent
current testing has proved to be very efficient for improving test quality of analog circuits.
The test methodology based on the observation of the quiescent current on power supply
buses allows a good coverage of physical defects such as gate oxide shorts, floating gates and
bridging faults.
A DfT based oscillation-testing methodology (OTM) suitable for both functional
and defect oriented testing, has been successfully applied to CMOS analog circuits such as
the analog to digital converters, digitally programmable switched-current bi-quadratic filters,
active RC filters, and to circuitry used as embedded blocks. OTM is conceptually simple,
does not need major circuit modifications and can be implemented in without any additional
signal generation circuitry. The test methodology is based on transforming the circuit under
test (CUT) into an oscillator whose frequency of oscillation is related to the component
values or to the circuit parameters. Hence, a change in the oscillation frequency from its
nominal value indicates the possibility of faults in the CUT. OTM is shown to be an effective
functional ‘go’ and ‘no-go’ test to verify if the circuit under test conforms to the required
specifications. The method achieves good fault-coverage removing test vector generation and
output evaluation, while reducing test complexity, area overhead, and test cost.
In this thesis, we discuss a DfT method for a two-stage CMOS amplifier, based on
oscillation testing methodology followed by Monte Carlo testing, for improving fault-
coverage, and testability. The proposed test method takes the advantage of good fault
coverage through the use of simple oscillation based test technique, which needs no test
signal generation and combines it with Monte Carlo testing to improve the fault coverage.
Fault detection is achieved using a simple deviation in parameter values, which introduces
insignificant performance degradation of the CUT, to monitor the power supply quiescent
current changes in the CUT and a passive RC network in the feedback path of the amplifier,
to enable the CUT to oscillate. The testability has also been enhanced in the testing procedure
using a simple fault-injection technique. It can also be generalized to the oscillation based test
structures of other CMOS analog and mixed-signal integrated circuits. In the digital domain,
DfT is well established. With the increasing complexity of the structure of logic circuits,
system-timing failures are occurring more frequently. Timing-related failures may be caused
by isolated gate delays or process-related timing problems that accumulate along logic paths
and prevent the circuit from functioning at the desired speed. The delay faults are becoming
critical in deep submicron (DSM) technologies where the interconnection delay exceeds the
gate delay. Oscillation Test methodology has successfully been extended to digital circuits,
for identifying delay and stuck-at faults. This is done by sensitizing all or at least critical
paths in the digital circuit under test and then incorporating it in a ring oscillator to test for
delay and stuck-at faults in the paths.
OSCILLATION TEST METHODOLOGY FOR MOSFET CIRCUITS
AKANKSHA GUPTA, ISHITA GUPTA, R ASHOK KUMAR, ARUN KUMAR 3
1.2 Testing Methodology
The proposed test methodology consists of first partitioning the analog mixed-signal
integrated circuit into functional building blocks such as amplifier, comparator, filter, and
data converter and then converting each building block into an oscillating circuit. In order to
implement OTM for the amplifier, it is converted into an oscillator using a simple first-order
derivation feedback circuit. The circuit’s output is connected to its input via a passive and/or
active analog circuit such that, the loop’s overall gain and phase cause oscillation. The output
oscillation frequency from the amplifier is measured and is compared with the nominal
oscillation frequency of the fault free circuit. If the oscillation frequency lies close to the
nominal frequency range, the CUT is accepted to be fault-free. The nominal frequency range
of the CUT is determined using a Monte-Carlo analysis taking into account the tolerance of
significant technology and design parameters.
i.e., If fosc ~ fnom FAULT DETECTED
otherwise FAULT UNDETECTED
OSCILLATION TEST METHODOLOGY FOR MOSFET CIRCUITS
AKANKSHA GUPTA, ISHITA GUPTA, R ASHOK KUMAR, ARUN KUMAR 4
1.3 BLOCK DIAGRAM
FIG.1(A) BLOCK DIAGRAM FOR CALCULATION OF NOMINAL
FREQUENCY
FIG.1(B) BLOCK DIAGRAM FOR CALCULATION OF FUNCTIONAL
OSCILLATION FREQUENCY
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AKANKSHA GUPTA, ISHITA GUPTA, R ASHOK KUMAR, ARUN KUMAR 5
1.4 FLOW CHART
YES NO
FIG.2 FLOW CHART
START
DESIGN OF TWO-STAGE
CMOS OPAMP
CONVERSION OF TWO-STAGE
CMOS OPAMP INTO
OSCILLATOR IN OSCILLATION
TEST METHODOLOGY
STATISTICAL ANALYSIS
APPLYING MONTE
CARLO METHOD
(fnom)
FAULT ANALYSIS USING
FIT (Fault injection transistor)
TECHNIQUE APPLYING
MONTE CARLO METHOD
(fosc)
If
fnom fosc
FAULT
DETECTED
FAULT
UNDETECTED
END
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AKANKSHA GUPTA, ISHITA GUPTA, R ASHOK KUMAR, ARUN KUMAR 6
Chapter-2
TESTING
A test for a defect is a set of conditions that would cause the defect to revert itself as a
fault if it were present. Stimulus and response are the two constitutive elements of a test. In
the case of logic networks, the stimulus is a sequence of binary values to be applied to the
input pins. The response is the set of binary values that appear at the output pins.
2.1 NEED FOR TESTING
The design and production of the majority of manufactured products usually involves
a rigorous design activity followed by detailed testing and evaluation of prototypes before
volume production is begun. Once in production, continuous quality control of components
and assembly is desirable, but comprehensive testing of each finished item is not usually
affordable. However, the more sophisticated the product, or the components used within the
product, then the more need there will be to try to ensure that the end product is fully
functional. The ability to test end products as comprehensively as possible within a given
budget or time constraint is therefore a universal problem.
Electronics, and here more specifically microelectronics, has the fundamental feature
that, in contrast to mechanical and electromechanical devices, visual inspection is of very
little use. Parametric or functional testing must be used. The range of testing involves both
the IC manufacturer and the original equipment manufacturer (OEM), in total including the
following principal activities:
i. tests by the IC manufacturer (vendor) to ensure that all the fabrication steps have been
correctly implemented during wafer manufacture (IC fabrication checks)
ii. tests to ensure that prototype ICs perform correctly in all respects (IC design checks)
iii. tests to ensure that subsequent production ICs are defect free (IC production checks)
iv. possibly tests by the OEM of incoming ICs to confirm their functionality (acceptance
tests);
v. tests by the OEM of final manufactured products (product tests).
2.2 DIFFICULTIES IN TESTING
1. Fault may occur anytime i.e, during
i. Design
ii. Process
iii. Package
iv. Field
2. Fault may occur at any place. The exact location of the fault on the chip is difficult to
predict.
3. VLSI circuit are large (More than 300 gates/chip or 20000-100000 transistors/chip)
4. I/O access is limited
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2.3 TESTING DURING VLSI LIFE CYCLE
Testing typically consists of:
Applying set of test stimuli
Inputs of circuit under test (CUT), and
Analyzing output responses
If incorrect (fail), CUT assumed to be faulty
If correct (pass), CUT assumed to be fault-free
FIG.3 TESTING DURING VLSI LIFE CYCLE
2.4 TEST PATTERN GENERATION
Test pattern generation is the design process of generating appropriate input vectors to
test a given digital design, whether it is a printed-circuit board (PCB) or an individual IC. The
generation of an acceptable reduced set of test vectors may be done in the following ways:
Manual generation
Automatic generation
Pseudorandom generation
2.4.1 Manual test pattern generation
Manual TPG is a method which the original circuit designer or OEM may adopt,
knowing in detail the functionality of the circuit or system involved. The test patterns may be
specified by considering a range of functional conditions, and listing the input test vectors
and healthy output responses involved in these situations. Alternatively, the input vectors that
will cause all the gates to switch at least once may be considered. If a working breadboard
prototype has been made, then this may be used to assist the OEM in this manual
compilation, or alternatively the CAD program used in the design may assist.
2.4.2 Automatic test pattern generation
Automatic (or algorithmic) test pattern generation, usually abbreviated to ATPG, becomes
increasingly necessary as the gate count in the circuit increases to the thousands upwards.
ATPG programs normally use a gate-level representation of the circuit, with all nodes or
paths enumerated.
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FIG.4 ATPG FLOW CHART
All ATPG programs based upon fault models assume that a single fault is present when
determining the test vectors. The usual fault model is the stuck-at model, which as we have
seen does in practice cover a considerable number of other types of faults, but not all. The
results of an ATPG program cannot, therefore, guarantee a defect-free circuit.
2.4.3 Pseudorandom test pattern generation
Deterministic ATPG algorithms provide the smallest possible test set to cover the
given fault list. The disadvantage is the complexity and cost of generating this minimum test
set.[*] On the other hand a fully exhaustive test set will incur no ATPG costs, but will usually
be too long to employ for large circuits. There is, however, an intermediate possibility which
has been used.
It is intuitively obvious that fault coverage increases with the number of input test
patterns which are applied, up to the full fault coverage; a single randomly chosen input test
vector is also likely to be a test for several faults in a complex circuit. Hence if a sequence of
random or pseudorandom input test vectors (see later) is used, it is probable that a number of
circuit faults will be covered without incurring any ATPG cost.
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AKANKSHA GUPTA, ISHITA GUPTA, R ASHOK KUMAR, ARUN KUMAR 9
2.5 DESIGN FOR TESTABILITY(DFT)
Design for testability, sometimes called design for test and almost always abbreviated
to DFT, is therefore the philosophy of considering at the design stage how the circuit or
system shall be tested, rather than leaving it as a tack-on exercise at the end of the design
phase. DFT techniques normally fall into three general categories, namely:
Ad hoc design methods
Scan path methods
Self test
2.5.1 Partitioning and ad hoc methods
Partitioning of a circuit or system and other ad hoc design methods consist largely of
a number of recommended or desirable practices which a designer should consider at the
design phase. One of the most obvious and intuitive techniques for easing the testing problem
is to partition the overall circuit or system into functional blocks, each of which may be
independently tested. It is generally accepted that test costs are proportional to the square of
the number of logic gates in a circuit and hence partitioning a circuit into, say, four equal
parts reduces the testing problems of each part by a factor of sixteen compared with the
overall circuit.
2.5.2 Scan path method
The techniques discussed in the preceding section, which employed multiplexers as
the means of improving the controllability and/or observability of internal nodes of a circuit
when under test, have the severe disadvantage of requiring many more I/Os to be provided on
the circuit to give this improved testability. Scan-path testing, sometimes referred to as scan
test is a means of overcoming this disadvantage and reducing the additional I/Os required to a
minimum irrespective of the size of the circuit being tested.
Scan-path testing of such a network involves switching all the storage elements of the
circuit from their normal mode to a test mode shift register configuration, A scan-in I/O and a
scan-out I/O allow data to be read into and read out from this reconfiguration for test
purposes, thus providing controllability and observability of internal nodes which would not
otherwise be readily accessible.
2.5.3 Self test
As has been seen, scan-path test methodologies do not eliminate the need to prepare
some set of acceptable test vectors for the circuit under test, or the need for appropriate
external hardware to apply the test stimuli and monitor the resulting response.
Turning therefore to offline self test methodologies, the concept here is to build in
appropriate means whereby the circuit under test can be switched from a normal mode of
operation to a test mode, with the required test stimuli and the resulting response both being
done on-chip without the need to generate any ATPG data based upon stuck-at fault
modelling or other means, or apply it in series or parallel using some external hardware
resource. The circuit under test becomes its own test vector generator and test response
detector. A further advantage of this concept is that on-chip tests can be done using the
normal system clock(s) and at the full speed of the normal system.
OSCILLATION TEST METHODOLOGY FOR MOSFET CIRCUITS
AKANKSHA GUPTA, ISHITA GUPTA, R ASHOK KUMAR, ARUN KUMAR 10
Chapter-3
FAULT INJECTION
3.1 INTRODUCTION
Fault injection is a phrase covering a variety of techniques for inducing faults in
systems to measure their response to those faults. In particular, it can be used in both
electronic hardware systems and software systems to measure the fault tolerance of the
system. For hardware, faults can be injected into simulations of the system, as well as into
implementation, both on a pin or external level and, recently, on an internal level for some
chips. For software, faults can be injected into simulations of software systems, such as
distributed systems, or into running software systems, at levels from the CPU registers to
memory to disk to networks. Fault injection is best used as a means for measuring the fault
tolerance or robustness of a system, especially for stress testing a system that may experience
faults too infrequently for normal testing. While the theory behind fault injection is still
being developed, the mechanisms are well understood. For an embedded system designer
attempting to measure the degree to which his design is resistant to faults, fault injection can
be a useful technique for quantifying this aspect of design.
The issues in fault injection is that of simulation versus execution. In the former, a
model of the system is developed and faults are introduced into that model. The model is
then simulated to find the effects of the fault on the operation of the system. These methods
are often slower to test, but easier to change. In the latter, the system itself is deployed, and
some mechanism found to cause faults in the system, and its execution is then observed to
determine the effects of the fault. These techniques are more useful for analyzing final
designs, but are typically more difficult to modify afterwards.
Fault injection is still a somewhat new technique, however, and there is still development
being done to see what kinds of systems this can be applied to, and which systems it is
appropriate to test in this manner. While there are some well understood mechanisms for
injecting faults into certain kinds of systems, such as distributed systems, other systems still
have basic techniques being designed, such as VLSI circuits. Often the method for inserting
faults is very application specific, rather than generalized, and therefore comparison of testing
methods is difficult. Finally, even when results have been gathered, researchers are still
uncertain or divided as to exactly what the results mean, and how they should be used.
3.2 CLASSIFICATION OF FAULT INJECTION
3.2.1 Hardware Fault Injection
Hardware fault injection is used to inject faults into hardware and examine the
effects. Typically this is performed on VLSI circuits at the transistor level, because these
circuits are complex enough to warrant characterization through fault injection rather than a
performance range, and because these are the best understood basic faults in such circuits.
Transistors are typically given stuck-at, bridging, or transient faults, and the results examined
in the operation of the circuit. Such faults may be injected in software simulations of the
circuits, or into production circuits cut from the wafer.
Hardware simulations typically occur in a high level description of the circuit. This
high level description is turned into a transistor level description of the circuit, and faults are
OSCILLATION TEST METHODOLOGY FOR MOSFET CIRCUITS
AKANKSHA GUPTA, ISHITA GUPTA, R ASHOK KUMAR, ARUN KUMAR 11
injected into the circuit. Typically these are stuck-at or bridging faults, as software
simulation is most often used to detect the response to manufacturing defects. The system is
then simulated to evaluate the response of the circuit to that particular fault. Since this is a
simulation, a new fault can then be easily injected, and the simulation re-run to gauge the
response to the new fault. This consumes time to construct the model, insert the faults, and
then simulate the circuit, but modifications in the circuit are easier to make than later in the
design cycle. This sort of testing would be used to check a circuit early in the design cycle.
These simulations are non-intrusive, since the simulation functions normally other than the
introduction of the fault.
Hardware fault injections occur in actual examples of the circuit after fabrication.
The circuit is subjected to some sort of interference to produce the fault, and the resulting
behavior is examined. So far, this has been done with transient faults, as the difficulty and
expense of introducing stuck-at and bridging faults in the circuit has not been overcome. The
circuit is attached to a testing apparatus which operates it and examines the behavior after the
fault is injected. This consumes time to prepare the circuit and test it, but such tests generally
proceed faster than simulation does. It is, rather obviously, used to test circuit just before or
in production. These simulations are non-intrusive, since they do not alter the behavior of the
circuit other than to introduce the fault. Should special circuitry be included to cause or
simulate faults in the finished circuit, these would most likely affect the timing or other
characteristics of the circuit, and therefore be intrusive.
3.2.2 Software Fault Injection
Software fault injection is used to inject faults into the operation of software and
examine the effects. This is generally used on code that has communicative or cooperative
functions so that there is enough interaction to make fault injection useful. All sorts of faults
may be injected, from register and memory faults, to dropped or replicated network packets,
to erroneous error conditions and flags. These faults may be injected into simulations of
complex systems where the interactions are understood though not the details of
implementation, or they may be injected into operating systems to examine the effects.
Software simulation are typically of high level description of a system, in which the protocols
or interactions are known, but not the details of implementation. These faults tend to be mis-
timings, missing messages, replays, or other faults in communication in a system. The
simulation is then run to discover the effects of the faults. Because of the abstract nature of
these simulations, they may be run at a faster speed that the actual system might, but would
not necessarily capture the timing aspects of the final system. This sort of testing would be
performed to verify a protocol, or to examine the resistance of an interaction to faults. This
would typically be done early in the design cycle so as to flesh out the higher level details
before attempting the task of implementation. These simulations are non-intrusive, as they
are simulated, but they may not capture the exact behavior of the system.
Software fault injections are more oriented towards implementation details, and can
address program state as well as communication and interactions. Faults are mis-timings,
missing messages, replays, corrupted memory or registers, faulty disk reads, and almost any
other state the hardware provides access to. The system is then run with the fault to examine
its behavior. These simulations tend to take longer because they encapsulate all of the
operation and detail of the system, but they will more accurately capture the timing aspects of
the system. This testing is performed to verify the system's reaction to introduced faults and
catalog the faults successfully dealt with. this is done later in the design cycle to show
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AKANKSHA GUPTA, ISHITA GUPTA, R ASHOK KUMAR, ARUN KUMAR 12
performance for a final or near-final design. These simulations can be non-intrusive,
especially if timing is not a concern, but if timing is at all involved the time required for the
injection mechanism to inject the faults can disrupt the activity of the system, and cause
timing results that are not representative of the system without the fault injection mechanism
deployed. This occurs because the injection mechanism runs on the same system as the
software being tested.
3.3 What is Fault Injection Really?
The main problem with fault injection is knowing what to do with it. Upon first
glance, it would seem to be a good tool for debugging a system, and detecting any flaws
within it. Once one examines the procedures and the information gained, however, it
becomes apparent that fault injection is good at testing known sorts of bugs or defects, but
poor at testing novel faults or defects, which are precisely the sorts of defects we would want
to discover. Therefore, what emerges is that fault injection is not really suited for debugging
and improving the system so much as it is suited for testing the fault tolerant features of the
system. A known fault in injected and the results examined to see if the system can respond
correctly despite the fault.
Along these lines, there are two proposed uses for fault injection. The first is for
verification of a system. If a system is designed to tolerate a certain class of faults, or exhibit
certain behavior in the presence of certain faults, then these faults can be directly injected into
the system to examine their effects. The system will either behave appropriately or not, and
its fault tolerance measured accordingly. For certain classes of ultra-dependable untestable
systems in which the occurrence of errors is too infrequent to effectively test the system in
the field, fault injection can be a powerful tool for accelerating the occurrence of faults in the
system and verifying that the system works properly.
The other proposed use for fault injection is less well understood, because the
problem it addresses is poorly understood. Robustness is used in regard to systems these
days almost synonymously with fault tolerance, but robustness actually embraces more than
this. There is no really good definition of robustness, but it is something along the lines of
"the capability of a system to behave correctly in unusual conditions." The difficulty lies in
creating unusual conditions so as to test the system for robustness. Fault injection has been
proposed as a method to address this problem, by including unusual conditions as well as
faults. This would provide us with a metric for measuring the robustness of a system.
There are two difficulties that must be addressed before this use of fault injection can
be fully applied. The first is the disparate nature of systems, and the ways in which they can
fail or experience faults. Unless two systems are set to accomplish the exact same task,
determining the relative robustness of the two systems is a difficult task. A good metric for
robustness would be able to resolve this difference. Secondly, it is not yet certain how our
metric should be biased. Common practice is to have the test distribution mirror the real
world distributions of occurrence of faults. If we are truly testing the system's response to
unusual situations, however, it might be better to bias the test towards the less frequently
encountered conditions. While there is agreement that fault injection can serve as a metric for
robustness, the exact mechanisms of doing so are as of yet poorly understood.
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3.4 TYPES OF FAULTS
• Parametric faults: Parametric faults are those changes that cause performance
degradation of the circuit. It is caused by statistical fluctuations in the manufacturing
process, comprise the small deviation of CUT parameters from their tolerance band.
These are due to out-of-specification parameter deviation and so depend upon the
acceptability band defined by tolerances of process parameters.
• Catastrophic faults: Catastrophic faults are all those changes that cause the circuit to
fail catastrophically. These faults include shorts, opens or large variations of a design
parameter like forward beta(β) in the BJTs and width and length of MOSFETs.
Catastrophic faults are caused by major structural deformations or extreme out-of-
range parameters and lead to failures that manifest themselves in a completely
malfunctioning circuit. Electro migration and particle contamination phenomena
occurring in the conducting and metallisation layers are the major causes of open and
bridging shorts.
3.5 BASIC FAULT MODELS
3.5.1 Stuck-at fault model
A stuck-at fault is a particular fault model used by fault simulators and automatic test
pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated circuit.
Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. For example, an
output is tied to a logical 1 state during test generation to assure that a manufacturing defect
with that type of behavior can be found with a specific test pattern. Likewise the output could
be tied to a logical 0 to model the behavior of a defective circuit that cannot switch its output
pin. Not all faults can be analyzed using the stuck-at fault model. Compensation for static
hazards, namely branching signals, can render a circuit untestable using this model. Also,
redundant circuits cannot be tested using this model, since by design there is no change in
any output as a result of a single fault.
3.5.2 Bridging fault model
In electronic engineering, a bridging fault consists of two signals that are connected
when they should not be. Depending on the logic circuitry employed, this may result in
a wired-OR or wired-AND logic function. Since there are O(n^2) potential bridging faults,
they are normally restricted to signals that are physically adjacent in the design.
Bridging to VDD or VSS is equivalent to stuck at fault model. Traditionally bridged
signals were modelled with logic AND or OR of signals. If one driver dominates the other
driver in a bridging situation, the dominant driver forces the logic to the other one, in such
case a dominant bridging fault is used. To better reflect the reality of CMOS VLSI devices,
a dominant AND or dominant OR bridging fault model is used where dominant driver keeps
its value, while the other signal value is the result of AND (or OR) of its own value with the
dominant driver.
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3.5.3 Transistor fault model
This model is used to describe faults for CMOS logic gates. At transistor level, a
transistor maybe stuck-short or stuck-open. In stuck-short, a transistor behaves as it is always
conducts (or stuck-on), and stuck-open is when a transistor never conducts current (or stuck-
off). Stuck-short will produce a short between VDD and VSS.
3.5.4 Open fault model
Here a wire is assumed broken, and one or more inputs are disconnected from the output
that should drive them. As with bridging faults, the resulting behaviour depends on the circuit
implementation.
3.5.5 Delay fault model
Where the signal eventually assumes the correct value, but more slowly (or rarely, more
quickly) than normal. a number of defects that can cause delay faults:
1) GOS defects
2) Resistive shorting defects between nodes and to the supply rails
3) Parasitic transistor leakages, defective pn junctions and incorrect or shifted threshold
voltages
4) Certain types of opens
5) Process variations can also cause devices to switch at a speed lower than the
specification
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Chapter-4
DESIGN OF A TWO-STAGE CMOS OPERATIONAL
AMPLIFIER
CMOS operational amplifier is a core element of almost all analog and mixed signal
systems. If the amplifiers are proven to be fault-free, the fault coverage would significantly
be improved. In this chapter, the testing methodology called oscillation testing used for
testing operational amplifiers is presented. Before introducing the testing methodology, the
design and the important frequency domain parameters of the operational amplifier are
presented in the next discussion.
4.1 DESIGN OF A CMOS OPERATIONAL AMPLIFIER
An ideal op-amp with a single-ended output has a differential input, infinite voltage
gain, infinite input impedance and zero output impedance. A conceptual schematic diagram
of an operational amplifier is shown in Fig.5. Op-amps and a few passive components can be
used to realize such important functions as summing and inverting amplifiers, integrators, and
buffers. The combination of these functions and comparators can result in many complex
functions, such as high-order filters, signal amplifiers, analog-to-digital (A/D) and digital-to-
analog (D/A) converters, input and output signal buffers, and many more. A typical high
performance operational amplifier is characterized by a high open loop gain, high bandwidth,
very high input impedance, low output impedance and an ability to amplify differential-mode
signals to a large extent and at the same time, severely attenuate common-mode signals.
FIG.5 IDEAL OPERATIONAL AMPLIFIER
The design of an operational amplifier consists of three functional building blocks as
shown in Fig.6. First, there is an input differential gain stage that amplifies the voltage
difference between the input terminals, independently of their average or common-mode
voltage. Most of the critical parameters of the op-amp like the input noise, common-mode
rejection ratio (CMRR) and common mode input range (CMIR) are decided by this stage.
The differential to single-ended conversion stage follows the differential amplifier and is
responsible for producing a single output, which can be referenced to ground. The differential
to single-ended conversion stage also provides the necessary bias for the second gain stage.
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Finally, additional gain is obtained in the second gain stage which is normally a
common-source gain stage that has an active load. Capacitor, CC is included between the
differential and the common-source stages to ensure stability when the amplifier is used with
feedback. An output stage can be added to provide a low output resistance and the ability to
source and sink large currents, but in this design we are not employing it since it is not
necessary in the present work. In the following subsections, the description as well as the
design methodology of each of the stages mentioned above is presented.
FIG.6 INTEGRATED OPERATIONAL AMPLIFIER
IDEAL OP-AMPS CHARACTERISTICS
An ideal op-amp is usually considered to have the following properties:
Infinite open-loop gain G = Vout / Vin
Infinite input impedance Rin, and so zero input current
Zero input offset voltage
Infinite voltage range available at the output
Infinite bandwidth with zero phase shift and infinite slew rate
Zero output impedance Rout
Zero noise
Infinite Common-mode rejection ratio (CMRR)
Infinite Power supply rejection ratio
OPERATIONS
The amplifier's differential inputs consist of a non-inverting input (+) with voltage V+ and an
inverting input (–) with voltage V−; ideally the op-amp amplifies only the difference in
voltage between the two, which is called the differential input voltage. The output voltage of
the op-amp Vout is given by the equation:
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4.1.1 A Two-Stage CMOS Amplifier Topology
A two-stage, internally compensated CMOS amplifier is used for the testing. The
circuit provides good voltage gain, a good common-mode range and good output swing.
Before the analysis of the op-amp is done, some of the basic principles behind the working of
MOS transistors are reviewed. The first stage consists of a p-channel differential pair M1-M2
with an n-channel current mirror load M3-M4 and a p-channel tail current source M5. The
second stage consists of an n-channel common-source amplifier M6 with a p-channel current-
source load M7. The high output resistances of these two transistors equate to a relatively
large gain for this stage and an overall moderate gain for the complete amplifier. Because the
op-amp inputs are connected to the gates of MOS transistors, the input resistance is
essentially infinite when the amplifier is used in internal applications. The sizes of the
transistors were designed for a bias current of 100 μA to provide for sufficient output voltage
swing, output-offset voltage, slew rate, and gain-bandwidth product.
4.1.2 Current Mirrors
Current mirrors are used extensively in MOS analog circuits both as biasing elements
and as active loads to obtain high AC voltage gain. Enhancement mode transistors remain in
saturation when the gate is tied to the drain, as the drain-to-source voltage (VDS) is greater
than the gate-to-source voltage (VGS) due to the threshold voltage (Vth) drop, i.e.,
VDS > VGS – Vth
Based on equation, constant current sources are obtained through current mirrors
designed by passing a reference current through a diode-connected (gate tied to drain)
transistor. Figures 7(a) and 7(b) show the p-MOS and n-MOS current mirrors design. A p-
MOS mirror serves as a current source while the n-MOS acts as a current sink. The voltage
developed across the diode-connected transistor is applied to the gate and source of the
second transistor, which provides a constant output current. Since both the transistors have
the same gate to source voltage, the currents when both transistors are in the saturation region
of operation, are governed by the following equation assuming matched transistors. The
current ratio IOUT/IREF is determined by the aspect ratios of the transistors. For the p-MOS
current mirror, we can write,
Iout = (W7 /L7)
Iref (W8 /L
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FIG.7(a) P-MOS CURRENT MIRROR
FIG.7(b) N-MOS CURRENT MIRROR
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4.1.3 Active Resistors
There are two active resistors used in the design. Firstly, the reference current that is
applied to the current mirror is obtained by means of an active resistor. The resistor here is
obtained by simply connecting the gate of a MOSFET to its drain as shown in Fig 9(a). This
connection forces the MOSFET to operate in saturation in accordance with the equation,
IDS = {β (VGS-Vth) 2}/2
where β is the transconductance parameter, Vth is the threshold voltage and VGS is the gate-
source voltage. Since the gate is connected to the drain, current IDS is now controlled
directly by VDS and therefore the channel transconductance becomes the channel
conductance.
The second active resistor shown in Fig 8(b) has been used to realize the nulling
resistance to reduce the effects of the right hand plane zero in the transfer function. The gate
of this transistor M11 is biased at VDD. Its small signal output resistance is obtained from
FIG.8 ACTIVE RESISTORS (a) GATE CONNECTED TO DRAIN (b)
GATE CONNECTED TO VDD
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CHAPTER-5
TEST MECHANISMS
5(A) OSCILLATION TEST METHODOLOGY
5(A).1 INTRODUCTION
This test method is based on partitioning a complex analog circuit into functional
building blocks, such as amplifier, operational amplifier (OA), comparator, Schmitt trigger,
filter, voltage reference, oscillator, phase locked-loop (PLL), etc., or a combination of these
blocks. During test mode, each building block is converted to a circuit which oscillates. The
oscillation frequency of each building block can be expressed as a function of either its
components or its important parameters. The building blocks which inherently generate a
frequency, such as oscillators, do not need to be rearranged, and their output frequency is
directly evaluated. The test is performed by evaluating the oscillation frequency.
FIG.9 CMOS AMPLIFIER
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The observability of a faulty component (or parameter) is defined as the sensitivity of
the oscillation frequency with respect to the variations of the component (or the parameter).
A fault is said to be detectable if it causes a reasonable deviation of the oscillation frequency
from its tolerance band. The tolerance band of for each CUT is determined based on a Monte
Carlo analysis of the converted CUT taking into account the nominal tolerance of all
important technology and design parameters. To increase the observability of a defect in a
component (or a fault in a parameter), the sensitivity of the oscillation frequency with respect
to that component (or parameter) should be increased. In other words, during the process of
converting the CUT to an oscillator, the oscillator architecture must be chosen so as to ensure
the maximum possible CUT component contribution in determining the oscillation
frequency. If necessary, more than one oscillator may be derived from a CUT to increase
fault coverage. Existing faults in the CUT related to components (or parameters) which are
involved in the oscillator structure manifest themselves as a deviation of the oscillation
frequency. Therefore, the deviation of the oscillation frequency from its nominal value may
be employed to confirm a fault. The equivalent rms noise of the CUT is normally much
smaller than the amplitude of the oscillation signal and therefore cannot affect its frequency.
If the equivalent rms noise is considerable, it may only cause a small jitter in the oscillation
signal. In practice, many oscillation cycles are used to estimate the oscillation frequency, and
consequently the jitter is averaged and, due to the random nature of noise, is cancelled.
However, if the oscillation signal amplitude is as small as the CUT equivalent rms noise,
which is far from the case in practice, the oscillation frequency will be seriously affected by
the noise.
5(A).2 FILTER-TO-OSCILLATOR CONVERSION TECHNIQUES
FIG.10 CONVERSION OF AMPLIFIER TO OSCILLATOR
5(A).2.1 USING TRANSFER FUNCTION
A brief survey of techniques we have found to be efficient in converting an active
filter to an oscillator is presented in this section. For each type of active filter, various
techniques can be easily found to transform it to an oscillator. Naturally, each second- or
higher-order system has the potential for oscillation. This ability can be used to convert the
filter under test to an oscillator by establishing the oscillation condition (Barkhausen
criterion) in its transfer function. For example, second order active filters can be converted to
oscillators by making their quality factor very high during test mode, which is equivalent to
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shifting its poles on the imaginary axis. A more general technique is to add a feedback loop to
the filter under test and then adjust the feedback element to produce sustained oscillations.
The feedback loop may be positive, negative, or a combination of both. To simplify the
mathematical presentation, in the following we consider the conversion of a filter under test
using a positive feedback loop. However, the feedback element may incorporate the effect of
negative or mixed feedbacks. For example, a positive feedback loop with a feedback element
having a negative sign results in a negative feedback. The transfer function of the new system
with a positive feedback is given by
where represents the original transfer function of the filter and is the transfer function of the
feedback element.
The oscillation frequency and the oscillation condition are obtained from
5(A).2.2 BARKHAUSEN CRITERION
This condition is known as the Barkhausen criterion. The Barkhausen criterion states that at
the frequency of oscillation the signal must traverse the loop with no attenuation and no
phase shift. For positive feedback, the phase shift must be zero, but for negative feedback, the
phase shift must be 180 to cancel the feedback sign and produce a total phase shift of zero.
As an example to clarify the Barkhausen criterion, we consider the case of a band-
pass system which is composed of a first-order low-pass and high-pass system cascaded
together. The output of the system is directly connected to its input to establish positive
feedback. The low-pass system has a pole at its cut off frequency and therefore its phase goes
from zero to 90 as goes from zero to infinity. The high-pass system has a zero at the origin
and a pole at its cut off frequency; hence its phase goes from 90 to zero as goes from zero to
infinity. At a specified frequency, the phase lead and lag effects cancel each other out and the
overall phase shift will be zero. If the loop gain at that frequency is slightly greater than
unity, the system produces sustained oscillations at that frequency.
In fact, in a band-pass system with its output connected to the input, existing noise is band-
pass filtered and amplified in the loop. The frequency components which pass through the
band-pass system are reapplied to the system by means of the positive feedback and the same
procedure is repeated, resulting in an oscillating signal constituted from the frequency
components which pass through the band-pass system. The amplitude of the oscillations is
limited by the nonlinear effects of the system. The oscillation frequency is determined by the,
bandwidth and the gain of the system. It should be noted that the presence of harmonic terms
in the oscillation frequency due to the limited and nonlinear characteristics of the bandpass
system causes a phase shift To compensate for this phase shift, the oscillation frequency is
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shifted by an amount of to supply a phase shift of thus maintaining a zero phase shift around
the feedback loop.
The new oscillation frequency is given by
where is the nominal oscillation frequency without considering the nonlinear effects, and
represents the amplitude of the nth harmonic. It is obvious that if the band-pass system is
selectively tuned to a central frequency and the overall loop-gain is close to unity, the output
signal will be a pure sinusoid oscillating at the central frequency. Low-pass filters can be
cascaded with a simple high-pass RC filter to construct a BPF. Similarly, cascading a low-
pass RC circuit with a high-pass filter results in a BPF. Existing low-pass and high-pass
filters on the chip may be cascaded together to obtain a BPF. The input of a notch filter may
be subtracted from its output to construct a BPF.
FIG.11 CMOS OSCILLATOR
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5(B) MONTE CARLO ANALYSIS
5(B).1 INTRODUCTION
The Monte Carlo analysis is used for simulations with a given error on different
components. This test is very useful for visualizing how the circuit will run with imperfect
components as are used in reality.
The Monte Carlo analysis allows the user to input two things:
First: The percent error of a given component in the schematic can be defined. This is the
purpose of the Monte Carlo Analysis; to apply an error to components. If the finished product
will have resistors with a 5% error, the simulation can include this deviation.
Second: The type of error can be defined as either Gauss, or Uniform. The gauss mode of
simulation is more realistic than the uniform mode. The Gauss mode uses a bell curve
approach as it randomly pick values in the range of error specified but with the majority of
the values near the resistor value. The Uniform mode of deviation randomly selects values
within the range specified oblivious of what the actual value of the resistor is. This mode of
deviation is more suited for a situation where the value of the resistor is not known precisely.
5(B).2 Mechanism
The nominal frequency range of the CUT is determined using a Monte-Carlo analysis
taking into account the tolerance of significant technology and design parameters. The
oscillation frequency of the oscillatory operational amplifier is measured and is compared
with the nominal oscillation frequency of the fault free circuit. If the oscillation frequency
lies close to the nominal frequency range, the amplifier is accepted to be fault-free. The
observability of a fault in a component (or a parameter) can be defined as the sensitivity of
the oscillation frequency with respect to the variations of the component (or the parameter).
In order to increase the observability of a defect in a component (or the fault in a parameter),
the oscillator architecture is chosen such that the amplifier’s frequency varying components
contribution to the oscillation frequency is maximized.
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5(B).3 How To Implement The Monte Carlo Analysis
Figure.12 is the example used for visual explanations.
FIG.12 MONTE CARLO CIRCUIT EXAMPLE
The resistor is the easiest component to use the analysis on. In the example, three resistors
will be given a a 5% error and the transistor Q1 will be given a 3% error.
In the existing code for the circuit add .MC command