OPERATION CONTROL OF MULTILEVEL INVERTERS FOR INDUCTION MOTORS Asst. Prof. Hamdy A. Ashour Prof. Yasser G. Dessouky Eng. Samia A. Mahmoud Arab Academy for Science and Technology, Department of Electrical and Computer Control Engineering Miami, P.O. Box: 1029, Alexandria, EGYPT, [email protected]Abstract This paper introduces theoretical and experimental analysis of 3-ph induction motor operated from 12 semiconductor switches connected in the form of neutral point clamped multilevel inverter. The general objective of a multi-level inverter is to synthesize a near sinusoidal voltage from several levels of DC voltages as a staircase (discreet) shaping waveform. A brief comparison of multilevel inverter has been introduced. Simulation models of the NPC inverters with different number of switches have been carried out using Simulink under MATLAB. Methods to increase number of levels (steps), hence reducing filter requirements and total harmonic distortion by increasing number of switches or controlling the firing patterns of the switches are suggested and analyzed. Controlling the switching pattern of the three- phase multi-level inverters to eliminate certain harmonic order in stator voltage of the three-phase induction motor is explained and analyzed. Motor speed response together with voltage and current waveforms for each configuration are obtained and discussed. Experimental setup has been designed, implemented and tested for practical validation. I. INTRODUCTION Electric machines have been considered as the main workhorse of industry for many years. AC machines are rugged, less expensive with lower maintenance requirements due to the absence of commutation problems but they exhibit highly coupled, nonlinear, multi-variable structures, as opposed to separately excited DC machines. There has been intensive research on the development of AC drive technology and as a consequence, the cost and performance of AC drives have been improved considerably [1]–[4]. The concept of multilevel inverters have been introduced to perform a power conversion in multiple voltage steps to obtain improved power quality, lower switching losses, better electromagnetic capability and higher voltage ratings [5]-[8]. Methods of operation control and performance enhancement of multilevel inverters have been investigated [9]-[12]. The availability of such inverters for power system and standard electrical machine drives for industrial applications has been illustrated [13]-[20]. Through this paper, a brief comparison between multilevel inverter configurations is discussed, control operation of the 3-ph NPC inverter for driving the 3-ph induction motor has been modeled and studied, methods of increasing number of voltage levels and elimination of certain harmonic orders to improve motor performance are demonstrated, and experimental setup has been implemented for practical validation. II. MULTILEVEL INVERTERS The multilevel voltage source inverters provide a unique structure of power electronics devices allows synthesizing a desired voltage from several steps of DC voltages as depicted in figure 1a. For a large power rating, a multi-stepped inverter can be utilized with a series-parallel connection of devices. However this arrangement requires matching, and some amount of voltage or current derating of the devices with complex and not easily available design. A possible solution for such higher power ratings is an arrangement of identical 1-ph inverters fed from single dc supply while the output is shaped through series connection of center-tapped transformers with different turns ration [9]-[10] or by a parallel connection of 3-ph inverters through center-tapped reactors in the output [2]. Other arrangements of multilevel inverters eliminating the need for the output transformers can be seen in figures 1b, 1c and 1d. These arrangements of power electronics devices convert the DC supply to an AC supply by proper selection of conducting devices (switching pattern), and the output is a multi-stepped (discrete) sinusoidal waveform with reduced filter requirements. The features of the three configurations can be summarized as follows [3]:- A. Diode-clamped multilevel inverter A diode-clamped multilevel inverter (DCMLI), and also may be name as neutral point clamped (NPC), is shown in figure 1b where one leg requires (m-1) DC sources, 2(m-1) switching devices with free wheeling diodes and (m-1)(m-2) clamping diodes. This implies that a multilevel inverter has a (m) output phase-leg voltage and a (2m-1) level output line voltage. Although each switching device is only required to block a voltage level of Vdc/(m-1), the clamping diodes need to have a reverse voltage blocking rating VD of: dc D V m k m V 1 1 (1) Where m is the number of phase-leg voltage levels; k goes from 1 to (m-2) and Vdc is the total DC link voltage. When (m) is sufficiently high, the number of diodes makes the system impractical to implement, which in fact limits the possible number of levels with such configuration. B. Flying-capacitors multilevel inverter Figure 1c shows one leg of multi-level inverter based on a flying-capacitors multilevel inverter (FCMLI). Assuming that each capacitor has the same voltage rating, series connection of the capacitors indicates the voltage level between the clamping points. The inner-loop balancing capacitors for phase- leg ‘a’ are independent from those for phase-leg ‘b’. The
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
OPERATION CONTROL OF MULTILEVEL INVERTERS FOR INDUCTION MOTORS
Asst. Prof. Hamdy A. Ashour Prof. Yasser G. Dessouky Eng. Samia A. Mahmoud
Arab Academy for Science and Technology, Department of Electrical and Computer Control Engineering
voltage level for the flying-capacitors inverter is similar to that of the diode-clamped type of inverter. That is, the phase
voltage Va0 of a multi-level inverter has ‘m’ levels, and the line voltage Vab has (2m-1) levels. Assuming that each
capacitor has the same voltage rating as the switching device, the DC bus needs (m-1) capacitors for a multi-level
inverter. The number of capacitors required for each phase is:
m
j
C jmN1
)( (2)
The switching devices have unequal turn-on time. Like the diode-clamped inverter, the line voltage consists of the
positive phase-leg voltage of terminal ‘a’ and the negative phase-leg voltage of terminal ‘b’. The inverter requires a large
number of storage capacitors. A multilevel inverter requires a total of (m-1)(m-2)/2 auxiliary capacitors per phase leg in
addition to (m-1) main DC bus capacitors in case of individual DC batteries are not available. On the contrary, a
multilevel diode-clamp inverter may require only (m-1) DC bus capacitors of the same voltage rating. It should be noted
that the issue of maintaining the charging balance of the capacitor adds complexity to the system requirements.
C. Cascaded multilevel inverter
A cascaded multilevel inverter as shown in figure 2d consists of a series of H-bridge (single-phase, full-bridge) inverter
units. The general function of this multilevel inverter is to synthesize a desired voltage from several separate DC sources
(SDCSs), which may be obtained from batteries, fuel cells, or solar cells. Each SDCS is connected to an H-bridge
inverter. The AC terminal voltages of different level inverters are connected in series. Unlike the diode-clamp or flying-
capacitors inverter, the cascaded inverter does not require any voltage-clamping diodes or voltage-balancing capacitors.
The phase output voltage is synthesized by the sum of inverter outputs, Van = Va1 + V a2 + --- + V aNS. The required
number NS of isolated dc sources, hence number of H-bridges, to get the m output phase voltage levels is:
2/)1( mNS (3)
It should be noted that each switching device always conducts for 1805 (or half-cycle), regardless of the pulse width of
the quasi-square wave of each bridge, making the switching device current stresses equal while identical repeated design
of such H-bridges optimizes the layout and packaging of such inverter configuration.
A comparison of components requirements per leg for each configuration can be summarized as in table 1.
III. SIMULATION AND ANALYSIS
A) Operation analysis
In this paper, the neutral-point-clamped (NPC) multilevel inverter is proposed to be utilized for operation of a 3-ph
induction motor. The three-phase neutral-point-clamped (NPC) inverter using 12 switches is shown in figure 2a. In this
circuit the DC bus voltage is split into two levels. The middle point ‘o’ is defined as the neutral point. The output voltage
Vao has up to three states (levels), (Vdc /2), (0) and (-Vdc /2). For voltage level Vdc /2 , the switches S1a and S2a are the
path of positive current, while D1a and D2a are the path of negative current, as shown in figure 2b. For voltage level 0,
the switches S2a and DC1 are the path of positive current, while S3a and DC2 are the path of negative current, as shown
in figure 2c. For voltage level -Vdc /2, the switches S3a and S4a are the path of positive current, while D3a, D4a are the
path of negative current, as shown in figure 2c. The two diodes DC1 and DC2 clamp the switches voltage to the DC bus
voltage. When both S1a and S2a turn on, the voltage across points ‘a’ and ‘G’ is Vdc (i.e.VaG = Vdc ). In this case, DC2
balance output voltage charging between S3a and S4a.The output voltage Vao is AC and VaG is DC, the difference
between Vao and VaG is Vdc /2. The conduction angle of switch Sa1 is reduced from 180o to an angle of (180o – 2α), and
the number of levels would also change. By changing in switching angles or the firing pattern α, the number of level in
the inverter can be increased, (this will be shown in section C).
B) Modeling of 3-ph (NPC) inverters
For comparison analysis, three different configuration models of the 3-ph NPC multilevel inverters have been built using
the Simulink under Matlab software program including:-
i- 3-ph using 12 switches
ii- 3-ph using 24 switches
iii- 3-ph using 36 switches
An example of such models is shown in figure 3 for the 3-ph (NPC) inverter with 12 switches, which consists of a load
bus, a supply bus, three legs (a, b, c), each leg has four switches, and measurement blocks. Simulation analysis is carried
out based on such models and results will be demonstrated through the following sections.
C) Increasing number of levels
Multi-level inverters include an array of power semiconductors and voltage sources. The output generated is voltage with
stepped wave forms. The term multi-level starts with the three-level inverter, and by increasing the number of levels, the
output voltage has more steps generating a staircase wave form which has a nearly sinusoidal wave shape. Number of
levels in the output voltage can be increased by the following two methods:-
i) Increasing number of devices
The operation of three-phase (NPC) inverters using 12-switch, 24-switgh and 36-switch has been simulated and
investigated. A comparison between the output phase voltage waveforms has been performed keeping the dc voltage
sources constant for all cases. From the analysis of simulation results shown in the figure 4, and when the number of
switches per leg is increased, followings can be concluded:-
-The output voltage wave form is becoming near to a sinusoidal waveforms.
-The total harmonic distortion (THD) becomes lower.
- The peak reverse voltage of the switch is lower.
-The rating of voltage and current sharing by each switch is lowered.
-According to the phase to neutral voltage, the 12-switch inverter may give 7 levels, and 24-switch may give 9 levels
while 36-switch may give 11 levels.
- 12-switche inverter has only α1, 24-switch has α1 and α2 while 36-switch has α1, α2 and α3 control firing delay angles.
- Number of levels of each inverter can be decided by controlling the (α) pattern which has more degree of freedom by
increasing number of switches (this will be illustrated in the next section).
- Adding more complexity and increasing the overall cost.
ii) Controlling the firing pattern (α) Figure 5 shows gate signals and different voltage waveforms of the simulated 3-ph 12 switch NPC inverter, where left
column is for α = 0 wile right column is for α = 20. y changing in switching angles or the firing pattern α (the shift angle
from the origin during positive half cycle from ‘0’ to ‘π’, and during negative half cycle from ‘π’ to ‘2 π’ the number of
levels in the output voltage can be increased. Considering that ‘i’ is the number of switching angles, the stepped phase
voltage waveform synthesized by a (2i +1) level inverter, where α1 to αi must satisfy α1 < α2 < …..< αi < π /2. To
explain how the staircase voltage is synthesized, the line to line waveform across the load terminal, where the potentials
of terminals ‘a’ and ‘c’ are positive if (S1a & S2a) and (S1c & S2c) are on, and the potential of terminal ‘b’ is negative if
(S3b & S4b) are on. Hence, the line to line voltages have 3 levels, and can be computed as follows: