op-amp

Circuit Schematic

The figure above is a typical two-stage CMOS operational amplifier.

The first stage has a p-channel differential input pair with a n-

channel current mirror active load.

Devices Length Width Multiplier

Mp1 1m 2m 16

Mp2 1m 2m 16

Mn3 1m 2m 4

Mn4 1m 2m 4

Mp5 1m 2m 32

Mp6 1m 2m 64

Mn7 1m 2m 16

Mp8 1m 2m 8

Mp9 1m 2m 8

Mn10 1m 2m 4

Mn11 1m 2m 4

Mn12 1m 2m 4

Mn13 1m 2m 4

Mp14 1m 2m 16

Mn15 1m 2m 8

Mn16 1m 2m 8

MCr 1m 2m 16

MCc 2m 2m 56

Tesbench

Gain, Gain BW & Phase Margin Slewrate

Floor Plan

Stick Diagram

Metal 1 PMOS Booster Mp6 Mp8 & Mp9

Metal 2

Metal 3

Metal 4

Polysilicon

Power Rail

Via

Differential Piar Mp1 & Mp2

Current Bias Mp5

Mp14 NMOS Booster Mn7 Compensation Resistor

Mn15 Mn16 Current Mirror Mn3 & Mn4

NMOS Current Mirror Mn10 & Mn11 NMOS Current Mirror Mn12 & Mn13

Layout View

The figure shows a layout of a Two-Stage Operational Amplifier. The

first gain stage is a differential-input single-ended output stage

which is constructed by Mp5, Mp1, Mp2 Mn3, Mn4. The second-stage is a

common-source gain and constructed by Mp6 and Mn7 known as our

boosters to amplify the signal.

Simulation and Verification

Design Rule Check:

Layout Versus Schematic:

Layout Parasitic Extraction:

Pad and Core Layout View

Pre and Post Simulation Results

RESULTS PRESIM POSTSIM

GAIN 84.3dB 84.6dB

RESULTS PRESIM POSTSIM

GAIN BW 11.8MHz 8.24MHz

PHASE MARGIN 60 60

PRESIM

POSTSIM

POSTSIM PRESIM

RESULTS PRESIM POSTSIM

SLEWRATE 2.1 V/s 1.26 V/s

POSTSIM

PRESIM

Pre and Post Simulation of FF, TT, and SS

RESULTS FF TT SS

Gain BW 14.8MHz 8.21MHz 4.84MHz

Phase Margin 61 60 60

RESULTS FF TT SS

Gain 76.1dB 84.6dB 78.9dB

FF

TT

SS

FF

TT

SS

RESULTS FF TT SS

Slew Rate 2.14 V/s 1.26 V/s 1.42 V/s

TT

FF

SS

FF

TT

SS

Conclusion

Basic layout rules and procedures are very important to speed up

the process of layouting. Minimum rule, metals and vias, capacitor and

resistor types are all essential in the process of Operational

Amplifier Layout.

Routing between devices are recommended to be thick to avoid

electromigration in such a way that the current density is matched

with the thickness of the metal. 45 degrees routing is encouraged and

is a good layout practice. As much as possible, routing must be done

with the shortest distance especially in direct routing with global

nets. T Routes are discouraged to avoid eddy currents to occur in

corners which will result to current unable to flow properly.

Guard ring of 5 to 10 array of contacts is encouraged in dealing

with operational amplifiers layout. This is for better noise immunity

and optimum performance.

ECE 127

Introduction to Digital

VLSI Design

Two Stage Operational Amplifier

Guinomla, Harris W.