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Advanced InformationDatasheet
OV7725 Color CMOS VGA (640x480) CAMERACHIPTM Sensor
Omni ision®
with OmniPixel2TM Technology
General Description The OV7725 CAMERACHIP™ image sensor is a lowvoltage CMOS device that provides the full functionality ofa single-chip VGA camera and image processor in a smallfootprint package. The OV7725 provides full-frame,sub-sampled or windowed 8-bit/10-bit images in a widerange of formats, controlled through the Serial CameraControl Bus (SCCB) interface.
This device has an image array capable of operating at upto 60 frames per second (fps) in VGA with complete usercontrol over image quality, formatting and output datatransfer. All required image processing functions,including exposure control, gamma, white balance, colorsaturation, hue control and more, are also programmablethrough the SCCB interface. In addition, OmniVisionsensors use proprietary sensor technology to improveimage quality by reducing or eliminating commonlighting/electrical sources of image contamination, suchas fixed pattern noise, smearing, blooming, etc., toproduce a clean, fully stable color image.
Features • High sensitivity for low-light operation• Standard SCCB interface• Output support for Raw RGB, RGB (GRB 4:2:2,
RGB565/555/444) and YCbCr (4:2:2) formats• Supports image sizes: VGA, QVGA, and any size
scaling down from CIF to 40x30• VarioPixel® method for sub-sampling• Automatic image control functions including:
Automatic Exposure Control (AEC), Automatic Gain Control (AGC), Automatic White Balance (AWB), Automatic Band Filter (ABF), and Automatic Black-Level Calibration (ABLC)
• Image quality controls including color saturation, hue, gamma, sharpness (edge enhancement), and anti-blooming
• ISP includes noise reduction and defect correction• Lens shading correction• Saturation level auto adjust (UV adjust)• Edge enhancement level auto adjust• De-noise level auto adjust• Frame synchronization capability
Applications • Cellular and picture phones• Toys• PC Multimedia• Digital still cameras
Key Specifications
Figure 1 OV7725 Pinout (Top View)
Array Size 640 x 480
Power SupplyDigital Core 1.8VDC + 10%
Analog 3.0V to 3.6VI/O 1.7V to 3.3V
PowerRequirements
Active 120 mW typical(60 fps VGA, YUV)
Standby < 20 µATemperature Range -20°C to +70°C
Output Format 8-bit• YUV/YCbCr 4:2:2• RGB565/555/444• GRB 4:2:2• Raw RGB Data
10-bit • Raw RGB DataLens Size 1/4"
Lens Chief Ray Angle 25° non linearMax Image Transfer Rate 60 fps for VGA
Sensitivity 3.8 V/(Lux • sec)S/N Ratio 50 dB
Dynamic Range 60 dBScan Mode Progressive
Electronic Exposure Up to 510:1 (for selected fps)Pixel Size 6.0 µm x 6.0 µm
Dark Current 40 mV/sWell Capacity 26 Ke-
Fixed Pattern Noise < 0.03% of VPEAK-TO-PEAKImage Area 3984 µm x 2952 µm
Package Dimensions 5345 µm x 5265 µm
A1
ADVDD
A2
RSTB
A3
VREFH
OV7725
A4
FSIN
A5
SCL
B1
ADGND
B2
VREFN
B4
AGND
B3
AVDD
B5
SDA
C1
PWDN
D1
D5
E1
D7
E2
D1
E5
DOVDD
F1
D9
F2
D3
F3
XCLK
F4
DOGND
F5
D2
A6
D0
B6
HREF
C6
VSYNC
D6
D4
E6
D6
F6
D8
E3
DVDD
E4
PCLK
7725CSP_DS_001
the OmniVision logo are registered trademarks of OmniVision Technologies, Inc.OmniPixel2 and CameraChip are trademarks of OmniVision Technologies, Inc.
These specifications are subject to change without notice.
OV7725 Color CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision
Functional Description
Figure 2 shows the functional block diagram of the OV7725 image sensor. The OV7725 includes:• Image Sensor Array (total array of 656 x 488 pixels, with active pixels 640 x 480 in YUV mode)• Analog Signal Processor• A/D Converters• Test Pattern Generator• Digital Signal Processor (DSP)• Image Scaler• Timing Generator• Digital Video Port• SCCB Interface
Figure 2 Functional Block Diagram
columnsense amp
row
sel
ect
imagearray
HR
EF
PCLK
VSY
NC
SCL
RST
B
FSIN
PWD
N
clock
exposure/gain detect
test patterngenerator
FIFODSP*
bufferbuffer
imagescaler
analogprocessing
video timinggenerator
DSP* (lens shading correction, de-noise, white/black pixel correction, auto white balance, etc.)note 1
exposure/gaincontrol
SCCBinterface
XC
LK
SDA
registers
A/D
G
R
BD[9:0]
videoport
7725CSP_DS_002
2 Proprietary to OmniVision Technologies, Inc. Version 1.4, December 17, 2007
Functional DescriptionOmni ision
Image Sensor Array
The OV7725 sensor has an image array of 664 x 490pixels for a total of 325,360 pixels, of which 640 x 480pixels are active (307,200 pixels). Figure 3 shows across-section of the image sensor array.
Figure 3 Image Sensor Array
Timing Generator
In general, the timing generator controls the followingfunctions:• Array control and frame generation• Internal timing signal generation and distribution• Frame rate timing• Automatic Exposure Control (AEC)• External timing outputs (VSYNC, HREF/HSYNC, and
PCLK)
Analog Signal Processor
This block performs all analog image functions including:• Automatic Gain Control (AGC)• Automatic White Balance (AWB)
A/D Converters
After the Analog Processing block, the bayer pattern Rawsignal is fed to a 10-bit analog-to-digital (A/D) convertershared by G and BR channels. This A/D converteroperates at speeds up to 12 MHz and is fully synchronousto the pixel rate (actual conversion rate is related to theframe rate).
In addition to the A/D conversion, this block also has thefollowing functions:• Digital Black-Level Calibration (BLC)• Optional U/V channel delay• Additional A/D range controls
blue green
microlens
glass
microlensmicrolens
red
7725CSP_DS_003
Version 1.4, December 17, 2007 P
In general, the combination of the A/D Range Multiplierand A/D Range Control sets the A/D range and maximumvalue to allow the user to adjust the final image brightnessas a function of the individual application.
Test Pattern Generator
The Test Pattern Generator features the following:• 8-bar color bar pattern• Shift "1" in output pin
Digital Signal Processor (DSP)
This block controls the interpolation from Raw data toRGB and some image quality control.• Edge enhancement (a two-dimensional high pass
filter)• Color space converter (can change Raw data to RGB
or YUV/YCbCr)• RGB matrix to eliminate color cross talk• Hue and saturation control• Programmable gamma control• Transfer 10-bit data to 8-bit
Image Scaler
This block controls all output and data formatting requiredprior to sending the image out. This block scalesYUV/RGB output from VGA to CIF and almost any sizeunder CIF.
Digital Video Port
Register bits COM2[1:0] increase IOL/IOH drive currentand can be adjusted as a function of the customer’sloading.
SCCB Interface
The Serial Camera Control Bus (SCCB) interface controlsthe CAMERACHIP sensor operation. Refer to OmniVisionTechnologies Serial Camera Control Bus (SCCB)Specification for detailed usage of the serial control port.
roprietary to OmniVision Technologies, Inc. 3
OV7725 Color CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision
Pin Description
Table 1 Pin Description
Pin Number Name Pin Type Function/Description
A1 ADVDD Power ADC power supply
A2 RSTB Input System reset input, active low
A3 VREFH Reference Reference voltage - connect to ground using a 0.1 µF capacitor
A4 FSIN Input (0)b Frame synchronize input
A5 SCL Input SCCB serial interface clock input
A6 D0a
a. D[9:0] for 10-bit Raw RGB data (MSB: D9; LSB: D0)
Output Data output bit[0]
B1 ADGND Power ADC ground
B2 VREFN Reference Reference voltage - connect to ground using a 0.1 µF capacitor
B3 AVDD Power Analog power supply
B4 AGND Power Analog ground
B5 SDA I/O SCCB serial interface data I/O
B6 HREF Output HREF output
C1 PWDN Input (0)b
b. Input (0) represents an internal pull-down resistor and should be grounded when not used.
Power Down Mode Selection0: Normal mode1: Power down mode
C6 VSYNC Output Vertical sync output
D1 D5 Output Data output bit[5]
D6 D4 Output Data output bit[4]
E1 D7 Output Data output bit[7]
E2 D1 Output Data output bit[1]
E3 DVDD Power Power supply (1.8 VDC) for digital logic core
E4 PCLK Output Pixel clock output
E5 DOVDD Power Digital power supply for I/O (1.7V ~ 3.3V)
E6 D6 Output Data output bit[6]
F1 D9c
c. D[9:2] for 8-bit YUV or RGB565/RGB555 (MSB: D9; LSB: D2)
Output Data output bit[9]
F2 D3 Output Data output bit[3]
F3 XCLK Input System clock input
F4 DOGND Power Digital ground
F5 D2 Output Data output bit[2]
F6 D8 Output Data output bit[8]
4 Proprietary to OmniVision Technologies, Inc. Version 1.4, December 17, 2007
Electrical CharacteristicsOmni ision
Electrical Characteristics
NOTE: Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and mayresult in permanent device damage.
Table 2 Operating Conditions
Parameter Min Max
Operating temperature -20°C +70°C
Storage temperaturea
a. Exceeding the stresses listed may permanently damage the device. This is a stress rating only and functional operationof the sensor at these and any other condition above those indicated in this specification is not implied. Exposure toabsolute maximum rating conditions for any extended period may affect reliability.
-40°C +125°C
Table 3 Absolute Maximum Ratings
Ambient Storage Temperature -40ºC to +95ºC
Supply Voltages (with respect to Ground)
VDD-A 4.5 V
VDD-C 3 V
VDD-IO 4.5 V
All Input/Output Voltages (with respect to Ground) -0.3V to VDD-IO+0.5V
Lead-free Temperature, Surface-mount process 245ºC
Version 1.4, December 17, 2007 Proprietary to OmniVision Technologies, Inc. 5
OV7725 Color CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision
Table 4 DC Characteristics (-20°C < TA < 70°C)
Symbol Parameter Condition Min Typ Max Unit
VDD-A DC supply voltage – analog – 3.0 3.3 3.6 V
VDD-C DC supply voltage – digital core See Note a
a. VDD-IO should not be lower than 2.45V when using the internal regulator for VDD-C (1.8V). When not using the internalregulator, VDD-C requires external 1.8V power that must not be higher than VDD-IO.
1.62 1.8 1.98 V
VDD-IO DC supply voltage – I/O See Note a 1.7 – 3.3 V
IDDA Active (operating) current See Note b
b. At 25ºC, VDD-A = 3.3V, VDD-C = 1.8V, VDD-IO = 3.3V IDDA = ∑{IDD-C + IDD-A}, fCLK = 24MHz at 30 fps YUV output, no I/O loading
10 + 19c
c. IDD-C = 10mA, IDD-A = 19mA, without loading
mA
IDDS-SCCB Standby currentSee Note d
d. At 25ºC, VDD-A = 3.3V, VDD-C = 1.8V, VDD-IO = 3.3V IDDS-SCCB refers to a SCCB-initiated Standby, while IDDS-PWDN refers to a PWDN pin-initiated Standby
1 mA
IDDS-PWDN Standby current 10 20 µA
VIH Input voltage HIGH CMOS 0.7 x VDD-IO V
VIL Input voltage LOW 0.2 x VDD-IO V
VOH Output voltage HIGH CMOS 0.9 x VDD-IO V
VOL Output voltage LOW 0.1 x VDD-IO V
IOH Output current HIGH See Note e
e. Standard Output Loading = 25pF, 1.2KΩ
8 mA
IOL Output current LOW 15 mA
IL Input/Output leakage GND to VDD-IO ± 1 µA
6 Proprietary to OmniVision Technologies, Inc. Version 1.4, December 17, 2007
Electrical CharacteristicsOmni ision
Table 5 Functional and AC Characteristics (-20°C < TA < 70°C)
Symbol Parameter Min Typ Max Unit
Functional Characteristics
A/D Differential non-linearity + 1/2 LSB
A/D Integral non-linearity + 1 LSB
AGC Range 30 dB
Red/Blue adjustment range 12 dB
Inputs (PWDN, CLK, RESET#)
fCLK Input clock frequency 10 24 48 MHz
tCLK Input clock period 21 42 100 ns
tCLK:DC Clock duty cycle 45 50 55 %
tS:RESET Setting time after software/hardware reset 1 ms
tS:REG Settling time for register change (10 frames required) 300 ms
SCCB Timing (see Figure 4)
fSCL Clock frequency 400 KHz
tLOW Clock low period 1.3 µs
tHIGH Clock high period 600 ns
tAA SCL low to data out valid 100 900 ns
tBUF Bus free time before new START 1.3 µs
tHD:STA START condition hold time 600 ns
tSU:STA START condition setup time 600 ns
tHD:DAT Data in hold time 0 µs
tSU:DAT Data in setup time 100 ns
tSU:STO STOP condition setup time 600 ns
tR, tF SCCB rise/fall times 300 ns
tDH Data out hold time 50 ns
Outputs (VSYNC, HREF, PCLK, and D[9:0] (see Figure 5, Figure 6, Figure 7, and Figure 8)
Version 1.4, December 17, 2007 Proprietary to OmniVision Technologies, Inc. 7
OV7725 Color CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision
Timing Specifications
Figure 4 SCCB Timing Diagram
Figure 5 Horizontal Timing
SDA (OUT)
tAA
tDH
SCL
tF tRtHIGH
tLOW tSU:DAT
SDA (IN)
tHD:DAT
tSU:STO
tSU:STA
tHD:STA
tBUF
7725CSP_DS_004
D[9:0]
HREF (row data)
last byte last bytezero first byte
PCLK
tSU
tHD
tPCLK
tPHL tPHL
tPDV
7725CSP_DS_005
8 Proprietary to OmniVision Technologies, Inc. Version 1.4, December 17, 2007
Timing SpecificationsOmni ision
Figure 6 VGA Frame Timing
Figure 7 QVGA Frame Timing
Figure 8 CIF Frame Timing
D[9:0]
HREF
HSYNC
VSYNC
note 1 for raw data, tP = tPCLK
note 2 for YUV/RGB, tP = 2 x tPCLK
510 x tLINE
4 x tLINE 20 tLINE
144 tP
P0 - P639
640 tP
64 tP
row 0
invalid data invalid data
row 1 row 2 row 479
tLINE = 784 tP 6 tLINE
480 x tLINE
76 tP 4 tP
7725CSP_DS_006
D[9:0]
HREF
HSYNC
VSYNC
note 1 for raw data, tP = tPCLK
note 2 for YUV/RGB, tP = 2 x tPCLK
278 x tLINE
4 x tLINE 24 tLINE
256 tP
P0 - P319
320 tP
64 tP
row 0
invalid data invalid data
row 1 row 2 row 239
tLINE = 576 tP 10 tLINE
240 x tLINE
183 tP 9 tP
7725CSP_DS_007
VGA HREF(see figure 6,
VGA frame timing)
CIF HREF(3 from 5)
VSYNC
7725CSP_DS_008
Version 1.4, December 17, 2007 Proprietary to OmniVision Technologies, Inc. 9
OV7725 Color CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision
Figure 9 RGB 565 Output Timing Diagram
Figure 10 RGB 555 Output Timing Diagram
D[9:2]
HREF (row data)
last byte last bytezero first byte
PCLK
tSU
tHD
tPCLK
tPHL tPHL
tPDV
D[9]
first byte second byte
R4
D[8] .
D[7] .
D[6] .
D[5] R0
D[4] G5
D[3] .
D[2] G3
D[9] G2
D[8] .
D[7] G0
D[6] B4
D[5] .
D[4] .
D[3] .
D[2] B07725CSP_DS_009
D[9:2]
HREF (row data)
last byte last bytezero first byte
PCLK
tSU
tHD
tPCLK
tPHL tPHL
tPDV
D[9]
first byte second byte
X
D[8] R4
D[7] .
D[6] .
D[5] .
D[4] R0
D[3] G4
D[2] G3
D[9] G2
D[8] .
D[7] G0
D[6] B4
D[5] .
D[4] .
D[3] .
D[2] B07725CSP_DS_010
10 Proprietary to OmniVision Technologies, Inc. Version 1.4, December 17, 2007
Timing SpecificationsOmni ision
Figure 11 RGB 444 Output Timing Diagram
D[9:2]
HREF (row data)
last byte last bytezero first byte
PCLK
tSU
tHD
tPCLK
tPHL tPHL
tPDV
D[9]
first byte second byte
X
D[8] .
D[7] .
D[6] X
D[5] R3
D[4] .
D[3] .
D[2] R0
D[9] G3
D[8] .
D[7] .
D[6] G0
D[5] B3
D[4] .
D[3] .
D[2] B0 7725CSP_DS_011
Version 1.4, December 17, 2007 Proprietary to OmniVision Technologies, Inc. 11
OV7725 Color CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision
Register Set
Table 6 provides a list and description of the Device Control registers contained in the OV7725. For all register Enable/Disablebits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 0x42 for write and 0x43 for read.
Table 6 Device Control Register List (Sheet 1 of 14)
Address(Hex)
RegisterName
Default(Hex) R/W Description
00 GAIN 00 RWAGC – Gain control gain settingGain = (GAIN[7] + 1) × (GAIN[6] + 1) × (GAIN[5] + 1) × (GAIN[4] + 1)
× (GAIN[3:0] / 16 + 1)
01 BLUE 80 RW
AWB – Blue channel gain settingBlue Gain = BLUE / 0x40 when AWBCtrl1[2] = 1Blue Gain = BLUE / 0x80 when AWBCtrl1[2] = 0
Note: This register should be > 1x.
02 RED 80 RW
AWB – Red channel gain settingBlue Gain = RED / 0x40 when AWBCtrl1[2] = 1Blue Gain = RED / 0x80 when AWBCtrl1[2] = 0
Note: This register should be > 1x.
03 GREEN 80 RW
AWB – Green channel gain settingBlue Gain = GREEN / 0x40 when AWBCtrl1[2] = 1Blue Gain = GREEN / 0x80 when AWBCtrl1[2] = 0
Note: This register should be > 1x.
04 RSVD XX – Reserved
05 BAVG 00 RB Average LevelAutomatically updated based on chip output format
06 GAVG 00 RG Average LevelAutomatically updated based on chip output format
07 RAVG 00 RR Average LevelAutomatically updated based on chip output format
08 AECH 00 RWExposure Value – AEC MSBs
Bit[7:0]: AEC[15:8] (see register AEC for AEC[7:0]}Automatically updated when AEC is enabled
09 COM2 00 RW
Common Control 2Bit[7:5]: ReservedBit[4]: Soft sleep modeBit[3:2]: ReservedBit[1:0]: Output drive capability
00: 1x01: 2x10: 3x11: 4x
0A PID 77 R Product ID Number MSB (Read only)
0B VER 21 R Product ID Number LSB (Read only)
12 Proprietary to OmniVision Technologies, Inc. Version 1.4, December 17, 2007
Register SetOmni ision
0C COM3 10 RW
Common Control 3Bit[7]: ReservedBit[6]: Horizontal mirror image ON/OFF selectionBit[5]: Swap B/R output sequence in RGB output modeBit[4]: Swap Y/UV output sequence in YUV output mode (see
register DSP_Ctrl3[7] (0x66))Bit[3]: Swap output MSB/LSBBit[2]: Tri-state option for output clock including PCLK, HREF,
and VSYNC at power-down period0: Tri-state at this period1: No tri-state at this period
Bit[1]: Tri-state option for output data at power-down period0: Tri-state at this period1: No tri-state at this period
Bit[0]: Sensor color bar test pattern output enable
Common Control 5Bit[7]: Auto frame rate control ON/OFF selection (night mode)Bit[6]: Auto frame rate control speed selection
0: Normal1: Fast
Bit[5:4]: Auto frame rate max rate control00: No reduction of frame rate01: Max reduction to 1/2 frame rate10: Max reduction to 1/4 frame rate11: Max reduction to 1/8 frame rate
Bit[3:2]: Auto frame rate active point control00: Not allowed01: Add frame when AGC reaches 4x gain10: Add frame when AGC reaches 8x gain11: Add frame when AGC reaches 16x gain
Bit[1:0]: Reserved
0F COM6 A9 RW
Common Control 6Bit[7:1]: ReservedBit[0]: Auto window setting ON/OFF selection when format
changes
Table 6 Device Control Register List (Sheet 2 of 14)
Address(Hex)
RegisterName
Default(Hex) R/W Description
Version 1.4, December 17, 2007 Proprietary to OmniVision Technologies, Inc. 13
OV7725 Color CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision
10 AEC 00 RW
Exposure ValueBit[7:0]: AEC[7:0] (see register AECH for AEC[15:8])
Image Start and Size ControlBit[7]: Mirror image edge alignment - should set to 1 in mirror
modeBit[6]: Vertical HREF window start control LSBBit[5:4]: Horizontal HREF window start control LSBsBit[3]: Data output bit shift test pattern ON/OFF controlBit[2]: Vertical sensor size LSBBit[1:0]: Horizontal sensor size 2 LSBs
33 DM_LNL 00 RW Low 8 Bits of the Number of Dummy Rows
34 DM_LNH 00 RW High 8 Bits of the Number of Dummy Rows
35 ADoff_B 80 RW AD Offset Compensation Value for B Channel
36 ADoff_R 80 RW AD Offset Compensation Value for R Channel
37 ADoff_Gb 80 RW AD Offset Compensation Value for Gb Channel
Table 6 Device Control Register List (Sheet 6 of 14)
Address(Hex)
RegisterName
Default(Hex) R/W Description
Version 1.4, December 17, 2007 Proprietary to OmniVision Technologies, Inc. 17
OV7725 Color CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision
38 ADoff_Gr 80 RW AD Offset Compensation Value for Gr Channel
39 Off_B 80 RW B Channel Offset Compensation Value
3A Off_R 80 RW R Channel Offset Compensation Value
3B Off_Gb 80 RW Gb Channel Offset Compensation Value
3C Off_Gr 80 RW Gr Channel Offset Compensation Value
3D COM12 80 RWCommon Control 12
Bit[7:6]: ReservedBit[5:0]: DC offset for analog process
3E COM13 E2 RW
Common Control 13Bit[7]: BLC enableBit[6]: ADC channel BLC ON/OFF controlBit[5]: Analog processing channel BLC ON/OFF controlBit[4:3]: ReservedBit[2]: ABLC gain trigger enableBit[1:0]: Reserved
3F COM14 1F RW
Edge Enhancement AdjustmentBit[7:4]: ReservedBit[3:2]: AD offset compensation option
x0: Use R/Gr channel value for B/Gb01: Use B/Gb channel value for R/Gr11: Use B/Gb/R/Gr channel value independently
Bit[1:0]: Analog processing offset compensation optionx0: Use R/Gr channel value for B/Gb01: Use B/Gb channel value for R/Gr11: Use B/Gb/R/Gr channel value independently
40 RSVD XX – Reserved
41 COM16 00 RWCommon Control 16
Bit[7:0]: Reserved
42 TGT_B 80 RWBLC Blue Channel Target ValueRegister value = 0x80 + Black level target value
43 TGT_R 80 RWBLC Red Channel Target ValueRegister value = 0x80 + Black level target value
44 TGT_Gb 80 RWBLC Gb Channel Target ValueRegister value = 0x80 + Black level target value
45 TGT_Gr 80 RWBLC Gr Channel Target ValueRegister value = 0x80 + Black level target value
Table 6 Device Control Register List (Sheet 7 of 14)
Address(Hex)
RegisterName
Default(Hex) R/W Description
18 Proprietary to OmniVision Technologies, Inc. Version 1.4, December 17, 2007
Register SetOmni ision
46 LC_CTR 00 RW
Lens Correction ControlBit[7:3]: ReservedBit[2]: Lens correction control select
0: R, G, and B channel compensation coefficient is set by registers LC_COEF (0x49)
1: R, G, and B channel compensation coefficient is set by registers LC_COEFB (0x4B), LC_COEF (0x49), and LC_COEFR (0x4C), respectively
Bit[1]: ReservedBit[0]: Lens correction enable
0: Disable1: Enable
47 LC_XC 00 RW
X Coordinate of Lens Correction Center Relative to Array CenterBit[7]: Sign bit
0: Positive1: Negative
Bit[6:0]: X coordinate of lens correction center relative to array center
48 LC_YC 00 RW
Y Coordinate of Lens Correction Center Relative to Array CenterBit[7]: Sign bit
0: Positive1: Negative
Bit[6:0]: Y coordinate of lens correction center relative to array center
49 LC_COEF 50 RWLens Correction CoefficientG channel compensation coefficient when LC_CTR[2] (0x46) is 1R, G, and B channel compensation coefficient when LC_CTR[2] is 0
4A LC_RADI 30 RW Lens Correction Radius – radius of the circular section where no compensation applies
4B LC_COEFB 50 RW Lens Correction B Channel Compensation Coefficient(effective only when LC_CTR[2] is high)
4C LC_COEFR 50 RW Lens Correction R Channel Compensation Coefficient(effective only when LC_CTR[2] is high)
Table 6 Device Control Register List (Sheet 8 of 14)
Address(Hex)
RegisterName
Default(Hex) R/W Description
Version 1.4, December 17, 2007 Proprietary to OmniVision Technologies, Inc. 19
OV7725 Color CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision
4D FixGain 00 RW
Analog Fix Gain AmplifierBit[7:6]: Gb channel fixed gain
00: 1x01: 1.25x10: 1.5x11: 1.75x
Bit[5:4]: Gr channel fixed gain00: 1x01: 1.25x10: 1.5x11: 1.75x
Bit[3:2]: B channel fixed gain00: 1x01: 1.25x10: 1.5x11: 1.75x
Bit[1:0]: R channel fixed gain00: 1x01: 1.25x10: 1.5x11: 1.75x
4E RSVD XX – Reserved
4F AREF1 10 RW
Sensor Reference Current ControlBit[7:4]: ReservedBit[3]: Internal regulator bypass selection
0: Enable1: Bypass
Bit[2:0]: Reserved
50-53 RSVD XX – Reserved
54 AREF6 7A RW
Analog Reference ControlBit[7]: Internal power supply control for power down mode -
should be set to 0 when internal regulator is used0: Enable1: Bypass
Bit[6:0]: Reserved
55-5F RSVD XX – Reserved
60 UFix 00 RW U Channel Fixed Value Output
61 VFix 05 RW V Channel Fixed Value Output
62 AWBb_blk FF RW AWB Option for Advanced AWB
63 AWB_Ctrl0 F0 RW
AWB Control Byte 0Bit[7]: AWB gain enableBit[6]: AWB calculate enableBit[5:0]: Reserved
Table 6 Device Control Register List (Sheet 9 of 14)
Address(Hex)
RegisterName
Default(Hex) R/W Description
20 Proprietary to OmniVision Technologies, Inc. Version 1.4, December 17, 2007
Register SetOmni ision
64 DSP_Ctrl1 BF RW
DSP Control Byte 1Bit[7]: FIFO enable/disable selectionBit[6]: UV adjust function ON/OFF selectionBit[5]: SDE enableBit[4]: Color matrix ON/OFF selectionBit[3]: Interpolation ON/OFF selectionBit[2]: Gamma function ON/OFF selectionBit[1]: Black defect pixel auto correction ON/OFFBit[0]: White defect pixel auto correction ON/OFF
65 DSP_Ctrl2 00 RW
DSP Control Byte 2Bit[7:4]: ReservedBit[3]: Vertical DCW enableBit[2]: Horizontal DCW enableBit[1]: Vertical zoom out enableBit[0]: Horizontal zoom out enable
66 DSP_Ctrl3 10 RW
DSP Control Byte 3Bit[7]: UV swap (works with register COM3[4] (0x0C))
Matrix ControlBit[7]: Matrix double ON/OFF selectionBit[6]: ReservedBit[5]: Sign bit for MTX6Bit[4]: Sign bit for MTX5Bit[3]: Sign bit for MTX4Bit[2]: Sign bit for MTX3Bit[1]: Sign bit for MTX2Bit[0]: Sign bit for MTX1
9B BRIGHT 00 RW Brightness
Table 6 Device Control Register List (Sheet 12 of 14)
Address(Hex)
RegisterName
Default(Hex) R/W Description
Version 1.4, December 17, 2007 Proprietary to OmniVision Technologies, Inc. 23
OV7725 Color CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision
9C CNST 40 RW Contrast Normalized by 0x20
9D RSVD XX – Reserved
9E UVADJ0 11 RWAuto UV Adjust Control 0
Bit[7:4]: Auto UV adjust offset control 4 LSBsBit[3:0]: Auto UV adjust threshold control
9F UVADJ1 02 RW
Auto UV Adjust Control 1Bit[7:3]: Auto UV adjust valueBit[2]: ReservedBit[1]: Auto UV adjust stop controlBit[0]: Auto UV adjust offset control MSB
A0 SCAL0 00 RW
DCW Ratio ControlBit[7:4]: ReservedBit[3:2]: Vertical down sampling select
00: Bypass01: 1/2 vertical down sampling10: 1/4 vertical down sampling11: 1/8 vertical down sampling
Bit[1:0]: Horizontal down sampling select00: Bypass01: 1/2 horizontal down sampling10: 1/4 horizontal down sampling11: 1/8 horizontal down sampling
A1 SCAL1 40 RWHorizontal Zoom Out ControlHorizontal zoom ratio = 0x40 / SCAL1
A2 SCAL2 40 RWVertical Zoom Out ControlVertical zoom ratio = 0x40 / SCAL2
A3-A5 RSVD XX – Reserved
A6 SDE 00 RW
Special Digital Effect (SDE) ControlBit[7]: ReservedBit[6]: Negative image enableBit[5]: Gray scale image enableBit[4]: V fixed value enableBit[3]: U fixed value enableBit[2]: Contrast/Brightness enableBit[1]: Saturation enableBit[0]: Hue enable
Table 6 Device Control Register List (Sheet 13 of 14)
Address(Hex)
RegisterName
Default(Hex) R/W Description
24 Proprietary to OmniVision Technologies, Inc. Version 1.4, December 17, 2007
Register SetOmni ision
AA HUESIN 80 RW |Sine value| × 0x80
AB SIGN 06 RW
Sign Bit for Hue and BrightnessBit[7:4]: ReservedBit[3]: Brightness sign bitBit[2]: ReservedBit[1]: Sign bit for HueSin (in Cr’ equation)Bit[0]: Sign bit for HueSin (in Cb’ equation)
Contrast/Brightness Control:Y = (Y0 - Yavg) × CNST / 0x20 + Yavg + SIGN[3] × BRIGHTwhere Yavg value is the average image luminance and is automatically calculated by the sensor.
AC DSPAuto FF RW
DSP Auto Function ON/OFF ControlBit[7]: AWB auto threshold controlBit[6]: De-noise auto threshold control
0: Manual mode - de-noise strength is set by register DNSTh (0x8E)
1: Automatic mode - de-noise strength is adjusted automatically and saved in register DNSTh (0x8E)
Bit[5]: Sharpness (edge enhancement) auto strength control0: Manual mode - sharpness is set by register
EDGE0[4:0] (0x8F)1: Automatic mode - sharpness is adjusted
automatically and saved in register EDGE0[4:0] (0x8F)
Bit[4]: UV adjust auto slope controlBit[3]: Auto scaling factor control (register SCAL0 (0xA0))Bit[2]: Auto scaling factor control (registers SCAL1 (0xA1 and
SCAL2 (0xA2))Bit[1:0]: Reserved
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.
Table 6 Device Control Register List (Sheet 14 of 14)
Address(Hex)
RegisterName
Default(Hex) R/W Description
Version 1.4, December 17, 2007 Proprietary to OmniVision Technologies, Inc. 25
OV7725 Color CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision
Package Specifications
The OV7725 uses a 28-ball Chip Scale Package 2 (CSP2). Refer to Figure 12 for package information, Table 7 for packagedimensions and Figure 13 for the array center on the chip.
Figure 12 OV7725-CSP2 Package Specifications
Note: For OVT devices that are lead-free, all part marking letters are lower case. Underlining the last digit of the lot number indicates CSP2 is used.
Table 7 OV7725-CSP2 Package Dimensions
Parameter Symbol Minimum Nominal Maximum Unit
Package body dimension X A 5320 5345 5370 µm
Package body dimension Y B 5240 5265 5290 µm
Package height C 845 905 965 µm
Ball height C1 150 180 210 µm
Package body thickness C2 680 725 770 µm
Cover glass thickness C3 375 400 425 µm
Airgap between cover glass and sensor C4 30 45 60 µm
Ball diameter D 320 350 380 µm
Total pin count N 28
Pin count X-axis N1 6
Pin count Y-axis N2 6
Pins pitch X-axis J1 800 µm
Pins pitch Y-axis J2 750 µm
Edge-to-pin center distance analog X S1 643 673 703 µm
Edge-to-pin center distance analog Y S2 728 758 788 µm
1234565 64321
ABCDEF
A
A
BCDEF
J1S1
center of BGA (die) =center of the package
B J2
C2
C1
glass die
CC4
C3
S2 350
bottom view(bumps up)
top view(bumps down)
side view
wxyzabcd
note 1 part marking code:w - OVT product versionx - year part was assembledy - month part was assembledz - wafer numberabcd - last four digits of lot number
chip center
optical center
7725CSP_DS_012
26 Proprietary to OmniVision Technologies, Inc. Version 1.4, December 17, 2007
Package SpecificationsOmni ision
Sensor Array Center
Figure 13 OV7725 Sensor Array Center
3984 μm
top view
note1 this drawing is not to scale and is for reference only.
note2 as most optical assemblies invert and mirror the image, the chip istypically mounted with pins A1 to A6 oriented down on the PCB.
2952 μm
sensorarray
OV7725
package center (0 μm, 0 μm)
array center (88.5 μm, 333.6 μm)
A1 A2 A3 A4 A5 A6
7725CSP_DS_013
scan origin (2080.5 μm, 1809.6 μm)
Version 1.4, December 17, 2007 Proprietary to OmniVision Technologies, Inc. 27
OV7725 Color CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision
Chief Ray Angle
Figure 14 OV7725 Chief Ray Angle
0.0 0.5 1.0 1.5 2.0 2.50.0
5.0
10.0
15.0
20.0
25.0
CRA
7725CSP_DS_014
28 Proprietary to OmniVision Technologies, Inc. Version 1.4, December 17, 2007
Package SpecificationsOmni ision
IR Reflow Ramp Rate Requirements
OV7725 Lead-Free Packaged Devices
Figure 15 IR Reflow Ramp Rate Requirements
Note: For OVT devices that are lead-free, all part marking letters are lower case
Table 8 Reflow Conditions
Condition Exposure
Average ramp-up rate (30°C to 217°C) Less than 3°C per second
> 100°C Between 330 - 600 seconds
> 150°C At least 210 seconds
> 217°C At least 30 seconds (30 ~ 120 seconds)
Peak temperature 245°C
Cool-down rate (peak to 50°C) Less than 6°C per second
Time from 30°C to 245°C No greater than 390 seconds
time (sec)
tem
per
atu
re (
°C)
-22 -2 18
38
58
78
98
11
8
13
8
15
8
17
8
35
8
33
8
31
8
29
8
27
8
25
8
23
8
21
8
19
8
36
9
0.0
300.0
280.0
220.0
240.0
260.0
200.0
180.0
140.0
160.0
120.0
100.0
80.0
60.0
40.0
20.0
Z1 Z2 Z3 Z4 Z5 Z6 Z7 end
7725CSP_DS_015
Version 1.4, December 17, 2007 Proprietary to OmniVision Technologies, Inc. 29
OV7725 Color CMOS VGA OmniPixel2™ CAMERACHIP™ Sensor Omni ision
Note:
• All information shown herein is current as of the revision and publication date. Please refer to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all documentation.
• OmniVision Technologies, Inc. reserves the right to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders).
• Reproduction of information in OmniVision product documentation and specifications is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible or liable for any information reproduced.
• This document is provided with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision Technologies, Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this document. No license, expressed or implied, by estoppels or otherwise, to any intellectual property rights is granted herein.
• ‘OmniVision’, ’VarioPixel’ and the OmniVision logo are registered trademarks of OmniVision Technologies, Inc. ’OmniPixel2’ and ’CameraChip’ are trademarks of OmniVision Technologies, Inc. All other trade, product or service names referenced in this release may be trademarks or registered trademarks of their respective holders. Third-party brands, names, and trademarks are the property of their respective owners.
For further information, please feel free to contact OmniVision at [email protected].
OmniVision Technologies, Inc.1341 Orleans DriveSunnyvale, CA USA(408) 542-3000
30 Proprietary to OmniVision Technologies, Inc. Version 1.4, December 17, 2007
DESCRIPTION OF CHANGESThe following changes were made to version 1.1:
• In Table 6 on page 11, deleted “(see GREEN[7:6] (0x03) for AGC [9:8])” from register description
• In Table 6 on page 11, changed name, default value, R/W status and description of register 0x04 to “RSVD”, “XX”, “–”, and “Reserved”, respectively
• In Table 6 on page 11, changed default value of register VER (0x0B) from “20” to “21”• In Table 6 on page 12, changed default value of register COM3 (0x0C) from “00” to “10”• In Table 6 on page 12, changed default value of register COM4 (0x0D) from “00” to “41”• In Table 6 on page 13, changed description of register bits COM7[5:4] (0x12) from:
• In Table 6 on page 14, changed description of register bits COM9[6:4] (0x14) from:Bit[6:4]: Automatic Gain Ceiling - maximum AGC value
000: 2x001: 4x010: 8x011: 16x100: 32x101 64x110: 128x111: Not allowed
to:Bit[6:4]: Automatic Gain Ceiling - maximum AGC value
000: 2x001: 4x010: 8x011: 16x100: 32x101 Not allowed110: Not allowed111: Not allowed
• In Table 6 on page 14, changed name, default value, and R/W status of register 0x16 from “RSVD”, “XX”, and “–” to “REG16”, “00”, and “RW”, respectively
Omni TMisionDESCRIPTION OF CHANGES (CONTINUED)
• In Table 6 on page 14, changed description of register 0x16 from “Reserved” to:Register 16
Bit[7]: Bit shift test pattern optionsBit[6:0]: Reserved
• In Table 6 on page 14, changed description of register 0x17 from “Horizontal Sensor Size” to “Horizontal Frame (HREF column) Start 8 MSBs (2 LSBs are at HREF[5:4])”
• In Table 6 on page 14, changed description of register 0x18 from “Horizontal Frame (HREF column) end high 8-bit (low 2 bits are at HREF[1:0])” to “Horizontal Sensor Size (2 LSBs are at HREF[1:0])”
• In Table 6 on page 14, changed description of register 0x19 from “Vertical Frame (row) start high 8-bit (low 1 bit is at HREF[6])” to “Vertical Frame (row) Start 8 MSBs (1 LSB is at HREF[6])”
• In Table 6 on page 14, changed description of register 0x1A from “Vertical Sensor Size” to “Vertical Sensor Size (1 LSB is at HREF[2])”
• In Table 6 on page 15, changed default value of register COM11 (0x20) from “04” to “10”• In Table 6 on page 15, changed name, default value, and R/W of register 0x28 from
“RSVD”, “XX”, and “–” to “REG28”, “00”, and “RW”, respectively• In Table 6 on page 15, changed description of register 0x28 from “Reserved” to:
Register 28Bit[7:1]: ReservedBit[0]: Selection on the number of dummy rows, N
• In Table 6 on page 16, changed default value of register HREF (0x32) from “80” to “00”• In Table 6 on page 16, changed description of register DM_LNL (0x33) from “Dummy
Line Low 8 Bits” to “Dummy Row Low 8 Bits”• In Table 6 on page 16, changed description of register DM_LNH (0x34) from “Dummy
Line High 8 Bits” to “Dummy Row High 8 Bits”• In Table 6 on page 16, changed default value of register COM13 (0x3E) from “F3” to
“E2”• In Table 6 on page 16, changed description of register COM13 (0x3E) from:
Common Control 13Bit[7]: Analog processing channel BLC ON/OFF controlBit[6]: ADC channel BLC ON/OFF controlBit[5:0]: Reserved
to:Common Control 13
Bit[7]: BLC enableBit[6]: ADC channel BLC ON/OFF controlBit[5]: Analog processing channel BLC ON/OFF controlBit[4:3]: ReservedBit[2]: ABLC gain trigger enableBit[1:0]: Reserved
Omni TMisionDESCRIPTION OF CHANGES (CONTINUED)
• In Table 6 on page 17, changed names of registers 0x46, 0x47, 0x48, 0x49, 0x4A, and 0x4B from “LCC0”, “LCC1”, “LCC2”, “LCC3”, “LCC4”, and “LCC5” to “LC_CTR”, “LC_XC”, “LC_YC”, “LC_COEF”, “LC_RADI”, and “LC_COEFB”
• In Table 6 on page 17, changed description of register 0x47 from “Lens Correction Option 1 – X Coordinate of Lens Correction Center Relative to Array Center” to:X Coordinate of Lens Correction Center Relative to Array Center
Bit[7]: Sign bit0: Positive1: Negative
Bit[6:0]: X coordinate of lens correction center relative to array center• In Table 6 on page 17, changed description of register 0x48 from “Lens Correction Option
2 – Y Coordinate of Lens Correction Center Relative to Array Center” to:Y Coordinate of Lens Correction Center Relative to Array Center
Bit[7]: Sign bit0: Positive1: Negative
Bit[6:0]: Y coordinate of lens correction center relative to array center• In Table 6 on page 17, changed description of register 0x49 from “Lens Correction Option
3” to “Lens Correction Coefficient”• In Table 6 on page 17, changed description of register 0x4A from “Lens Correction
Option 4 – radius ...” to “Lens Correction Radius – radius ...”• In Table 6 on page 17, changed description of register 0x4B from “Lens Correction Option
5 (effective ...” to “Lens Correction B Channel Compensation Coefficient (effective ...”• In Table 6 on page 18, changed name of register 0x4C from “LCC6” to “LC_COEFR”• In Table 6 on page 18, changed description of register 0x4C from “Lens Correction Option
6 (effective ...” to “Lens Correction R Channel Compensation Coefficient (effective ...”• In Table 6 on page 18, changed default value of register AREF0 (0x4E) from “F0” to “EF”• In Table 6 on page 18, changed default value of register AREF2 (0x50) from “30” to “60”• In Table 6 on page 18, changed default value of register AREF6 (0x54) from “3A” to
“7A”• In Table 6 on page 19, changed description of register bit DSP_Ctrl1[5] (0x64) from
“YUV444 to 422 UV channel option selection” to “SDE enable”• In Table 6 on page 19, changed description of register bits DSP_Ctrl2[3:0] (0x65) from:
Bit[3:0]: Scaling controlto:Bit[3]: Vertical DCW enableBit[2]: Horizontal DCW enableBit[1]: Vertical zoom out enableBit[0]: Horizontal zoom out enable
Omni TMisionDESCRIPTION OF CHANGES (CONTINUED)
• In Table 6 on page 19, changed description of register DSP_Ctrl4 (0x67) from:DSP Control Byte 4to:DSP Control Byte 4
Bit[7:3]: ReservedBit[2]: AEC selection
0: Before gamma1: After gamma
Bit[1:0]: Output selection00: YUV or RGB01: YUV or RGB10: RAW811: RAW10
• In Table 6 on page 20, changed description of register AWBCtrl1 (0x69) from:AWB Control 1to:AWB Control 1
Bit[7:4]: ReservedBit[3]: G gain enable
0: AWB adjusts R and G gain1: AWB adjusts R, G, and B gain
Bit[2]: Max color gain0: Max color gain is 2x1: Max color gain is 4x
Bit[1]: ReservedBit[0]: AWB mode select
0: Advanced AWB mode1: Normal AWB mode
• In Table 6 on page 21, changed description of register EDGE0 (0x8F) from:Edge Enhancement Control 0
Bit[7:5]: ReservedBit[4:0]: Edge enhancement strength control
toSharpness (Edge Enhancement) Control 0
Bit[7:5]: ReservedBit[4:0]: Sharpness (edge enhancement) strength control
• In Table 6 on page 21, changed description of register EDGE1 (0x90) from:Edge Enhancement Control 1
Bit[7:4]: ReservedBit[3:0]: Edge enhancement threshold control
• In Table 6 on page 21, changed description of register 0x92 from “Edge Enhancement Strength Low Point Control” to “Sharpness (Edge Enhancement) Strength Upper Limit”
Omni TMisionDESCRIPTION OF CHANGES (CONTINUED)
• In Table 6 on page 21, changed description of register 0x93 from “Edge Enhancement Strength High Point Control” to “Sharpness (Edge Enhancement) Strength Lower Limit”
• In Table 6 on page 22, added “gain × 0x20” to description of register CNST (0x9C)• In Table 6 on page 22, changed name, default value, R/W status and description of register
0x9D to “RSVD”, “XX”, “–”, and “Reserved”, respectively• In Table 6 on page 22, changed description of register SCAL0 (0xA0) from “Scaling
Control 0” to:DCW Ratio Control
Bit[7:4]: ReservedBit[3:2]: Vertical down sampling select
00: Bypass01: 1/2 vertical down sampling10: 1/4 vertical down sampling11: 1/8 vertical down sampling
Bit[1:0]: Horizontal down sampling select00: Bypass01: 1/2 horizontal down sampling10: 1/4 horizontal down sampling11: 1/8 horizontal down sampling
• In Table 6 on page 22, changed description of register SCAL1 (0xA1) from “Scaling Control 1 – for horizontal scaling control” to:Horizontal Zoom Out Control
• In Table 6 on page 22, changed description of register SCAL2 (0xA2) from “Scaling Control 2 – for vertical scaling control” to:Vertical Zoom Out Control
• In Table 6 on page 23, changed description of register SDE (0xA6) from “Special Digital Effect Control” to:Special Digital Effect Control
Bit[7]: ReservedBit[6]: Negative image enableBit[5]: Gray scale image enableBit[4]: V fixed value enableBit[3]: U fixed value enableBit[2]: Contrast/Brightness enableBit[1]: Saturation enableBit[0]: Hue enable
• In Table 6 on page 23, added “gain × 0x40” to description of registers USAT (0xA7) and VSAT (0xA8)
Horizontal zoom ratio = 0x40
SCAL1[7:0]
Vertical zoom ratio = 0x40
SCAL2[7:0]
Omni TMisionDESCRIPTION OF CHANGES (CONTINUED)
• In Table 6 on page 23, changed name of register 0xA9 from “HUE0” to “HUECOS”• In Table 6 on page 23, changed name of register 0xAA from “HUE1” to “HUESIN”• In Table 6 on page 23, changed description of register 0xA9 from “Hue Control 0” to
“Cosine value × 0x80”• In Table 6 on page 23, changed description of register 0xAA from “Hue Control 1” to
“Sine value × 0x80”• In Table 6 on page 23, changed description of register SIGN (0xAB) from:
Sign Bit for Hue and ContrastBit[7:4]: ReservedBit[3:2]: Contrast sign bitBit[1:0]: Hue sign bit
to:Sign Bit for Hue and Brightness
Bit[7:4]: ReservedBit[3]: Brightness sign bitBit[2]: ReservedBit[1]: Sign bit for HueSin (in Cr’ equation)Bit[0]: Sign bit for HueSin (in Cb’ equation)
• In Table 6 on page 23, changed description of register bit DSPAuto[5] (0xAC) from “Edge enhancement auto strength control” to “Sharpness (edge enhancement) auto strength control”
• In Figure 12 on page 24, changed underlined ‘w’ in the drawing and in the notes
DESCRIPTION OF CHANGESThe following changes were made to version 1.2:
• Under Key Specifications on page 1, changed specification for Analog Power Supply from “3.0V to 3.3V” to “3.0V to 3.6V” and deleted footnote a from I/O Power Supply specification
• Under Image Sensor Array section on page 3, changed first sentence from “... array of 656 x 488 pixels for a total of 320,128 pixels ...” to “... array of 664 x 490 pixels for a total of 325,360 pixels ...”
• In Table 1 on page 4, changed Pad Type for pad 27 from “Input” to “Input (0)a” and added “and should be grounded when not used” to footnote a.
• In Table 4 on page 6, changed Min specification for DC supply voltage – I/O from “2.5” to “1.7”
• In Table 4 on page 6, added “See Note a” to Condition of DC supply voltage – digital core parameter and to Condition of DC supply voltage – I/O parameter
• In Table 4 on page 6, added footnote a, “VDD-IO should not be lower than 2.45V when using the internal regulator for VDD-C (1.8V). When not using the internal regulator,VDD-C requires external 1.8V power that must not be higher than VDD-IO.”
• In Table 4 on page 6, changed Typ value for Active (operating) current (IDDA) from“10 + 8c” to “10 + 19c”
• In Table 4 on page 6, changed footnote b from “IDDA = ∑{IDD-IO + IDD-C + IDD-A}, ...” to “IDDA = ∑{IDD-C + IDD-A}, ...”
• In Table 4 on page 6, changed footnote c from “IDD-C = 10mA, IDD-A = 8mA, without loading” to “IDD-C = 10mA, IDD-A = 19mA, without loading”
• In Table 4 on page 6, changed Max value for Input voltage LOW (VIL) from“0.3 x VDD-IO” to “0.2 x VDD-IO”
• On page 9, changed four callouts in Figure 6 and five callouts in Figure 7• In Table 6 on page 12, made extensive changes to descriptions of registers 0x00 (GAIN),
0x01 (BLUE), 0x02 (RED), and 0x03 (GREEN)• In Table 6 on page 12, changed description of registers BAVG (0x05), GAVG (0x06), and
RAVG (0x07) from “U/B Average Level”, “Y/Gb Average Level”, and V/R Average Level” to “B Average Level”, “G Average Level”, and “R Average Level”, respectively
• In Table 6 on page 12, changed description of register AECH (0x08) from “Automatically updated based on chip output format” to “Automatically updated when AEC is enabled”
Omni TMisionDESCRIPTION OF CHANGES (CONTINUED)
• In Table 6 on page 13, added “(see register DSP_Ctrl3[7] (0x66))” to description of register bit COM3[4] (0x0C)
• In Table 6 on page 13, changed description of register bit COM3[2] (0x0C) from “Tri-state option for output clock at power-down period” to “Tri-state option for output clock including PCLK, HREF, and VSYNC at power-down period”
• In Table 6 on page 13, added the following to description of register bit COM5[6] (0x0E):0: Normal1: Fast
• In Table 6 on page 13, changed the description of register bit COM5[0] (0x0E) to Reserved
• In Table 6 on page 14, made extensive changes to descriptions of registers 0x10 (AEC) and 0x11 (CLKRC)
• In Table 6 on page 15, made extensive changes to description of register 0x13 (COM8)• In Table 6 on page 16, changed description of register bit COM10[2] (0x15) to Reserved• In Table 6 on page 16, added “should be set to 1 for bit shift test pattern” to description of
register bit REG16[7] (0x16)• In Table 6 on page 16, made extensive changes to descriptions of registers 0x17
(HSTART), 0x18 (HSIZE), 0x19 (VSTRT), and 0x1A (VSIZE)• In Table 6 on page 17, deleted “, N” from description of register bit REG28[0] (0x28)• In Table 6 on page 17, made extensive changes to descriptions of registers 0x29
(HOutSize) and 0x2C (VOutSize)• In Table 6 on page 17, added “should set to 1 in mirror mode” to description of register bit
HREF[7] (0x32)• In Table 6 on page 17, changed description of register DM_LNL (0x33) to “Low 8 Bits of
the Number of Dummy Rows”• In Table 6 on page 17, changed description of register DM_LNH (0x34) to “High 8 Bits of
the Number of Dummy Rows”• In Table 6 on page 18, deleted “Analog Process” from description of registers Off_B
(0x39), Off_R (0x3A), Off_Gb (0x3B), and Off_Gr (0x3C)• In Table 6 on page 18, deleted “compensation” from description of register bits
COM12[5:0] (0x3D)• In Table 6 on page 18, changed name, default value, R/W type, and description of register
0x40 to RSVD, XX, –, and Reserved, respectively• In Table 6 on page 18, changed description of register bits COM16[1:0] (0x41) to
“Reserved”• In Table 6 on page 18, made extensive changes to descriptions of registers 0x42 (TGT_B),
0x43 (TGT_R), 0x44 (TGT_Gb), and 0x45 (TGT_Gr)• In Table 6 on page 20, made extensive changes to description of register 0x4D (FixGain)
Omni TMisionDESCRIPTION OF CHANGES (CONTINUED)
• In Table 6 on page 20, changed name, default value, R/W type, and description of register 0x4E to RSVD, XX, –, and Reserved, respectively
• In Table 6 on page 20, changed description of register bits AREF1[7:4] and AREF1[1:0] 0x4F to Reserved
• In Table 6 on page 20, changed description of register bit AREF[3] from “Internal regulator ON/OFF selection” to “Internal regulator bypass selection” and added description for ‘0’ and ‘1’
• In Table 6 on page 20, changed name, default value, R/W type, and description of registers 0x50 to 0x53 to RSVD, XX, –, and Reserved, respectively
• In Table 6 on page 20, changed description of register AREF6 (0x54) to:Analog Reference Control
Bit[7]: Internal power supply control for power down mode - should be set to 0 when internal regulator is used0: Enable1: Bypass
Bit[6:0]: Reserved• In Table 6 on page 20, changed name, default value, R/W type, and description of register
0x55 to RSVD, XX, –, and Reserved, respectively• In Table 6 on page 20, changed description of register bits AWB_Ctrl0[4:0] (0x63) to
Reserved• In Table 6 on page 21, changed description of register bits DSP_Ctrl1[1:0] (0x64) to:
Bit[1]: Black defect pixel auto correction ON/OFFBit[0]: White defect pixel auto correction ON/OFF
• In Table 6 on page 21, made extensive changes to description of register 0x66 (DSP_Ctrl3)
• In Table 6 on page 21, changed description of register bit DSP_Ctrl4[2] (0x67) from “AEC selection” to “AEC reference point selection”
• In Table 6 on page 21, changed description of register bit AWBCtrl1[3] (0x69) to:Bit[3]: G gain enable
0: AWB adjusts R and G gain only1: AWB adjusts R, G, and B gain
• In Table 6 on page 23, changed description of register bits EDGE1[3:0] (0x90) from “Sharpness (edge enhancement) threshold detection” to “Threshold for edge detection”
• In Table 6 on page 23, changed description of register DNSOff (0x91) to “Lower Limit of De-noise Threshold - effective in auto mode only”
• In Table 6 on page 23, deleted “Control” from the description of register BRIGHT (0x9B)• In Table 6 on page 24, changed description of register CNST (0x9C) to “Contrast
Normalized by 0x20”• In Table 6 on page 24, made extensive changes to description of register 0xA1 (SCAL1)
Omni TMisionDESCRIPTION OF CHANGES (CONTINUED)
• In Table 6 on page 20, changed name, default value, R/W type, and description of registers 0xA3 and 0xA4 to RSVD, XX, –, and Reserved, respectively
• In Table 6 on pages 24 and 25, made extensive changes to description of register 0xA2 (SCAL1), 0xA7 (USAT), 0xA8 (VSAT), 0xAA (HUESIN), and 0xAB (SIGN)
• In Table 6 on page 24, added “(SDE)” to description of register SDE (0xA6)• In Table 6 on page 26, made extensive changes to description of register 0xAC (DSPAuto)
DESCRIPTION OF CHANGESThe following changes were made to version 1.31:
• Under Key Specifications on page 1, changed Sensitivity from “3.0 V/(Lux • sec)” to“3.8 V/(Lux • sec)”
• In Table 6 on page 12, changed R/W for registers 0x05, 0x06, and 0x07 from “RW” to “R”• In Table 6 on page 12, changed default value for register 0x03 from “00” to “80”• In Table 6 on page 12, changed default value for register 0x09 from “01” to “00”• In Table 6 on page 13, changed default value for register 0x0E from “01” to “79”• In Table 6 on page 13, changed default value for register 0x0F from “43” to “A9”• In Table 6 on page 14, changed default value for register 0x10 from “40” to “00”• In Table 6 on page 14, changed default value for register 0x11 from “80” to “00”• In Table 6 on page 15, changed default value for register 0x13 from “8F” to “CF”• In Table 6 on page 15, changed default value for register 0x14 from “4A” to “40”• In Table 6 on page 16, changed default value for register 0x17 from “23 (VGA)” to
“26 (VGA)”• In Table 6 on page 17, changed default value for register 0x24 from “75” to “58”• In Table 6 on page 17, changed default value for register 0x25 from “63” to “48”• In Table 6 on page 17, changed default value for register 0x26 from “D4” to “C3”• In Table 6 on page 17, changed R/W for register 0x2F from “RW” to “R”• In Table 6 on page 18, changed default value for register 0x41 from “08” to “00”• In Table 6 on page 20, changed default value for register 0x60 from “80” to “00”• In Table 6 on page 20, changed default value for register 0x61 from “80” to “05”• In Table 6 on page 21, changed default value for register 0x64 from “1F” to “BF”• In Table 6 on page 22, changed default value for register 0x76 from “FF” to “00”• In Table 6 on page 22, changed default value for register 0x77 from “FF” to “10”