OBSTACLE AVOIDING ROBOT ABSTRACT AIM: The main objective of this project is to develop an embedded system, which will automatically stop when an obstacle is detected using ultrasonic sensor. IMPLEMENTATION: This project is implemented 8051 based At89s52 developed board interfaced with Ultrasonic sensor, H-Bridge driver motors. BLOCK DIAGRAM: MICROCONTROLLER AT89S52 RPS L293D INFRARED SENSOR CRYSTAL ROBOTIC PLATFORM ULTRASONIC SENSOR
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OBSTACLE AVOIDING ROBOT
ABSTRACT
AIM:
The main objective of this project is to develop an embedded system, which will
automatically stop when an obstacle is detected using ultrasonic sensor.
IMPLEMENTATION:
This project is implemented 8051 based At89s52 developed board interfaced with
Ultrasonic sensor, H-Bridge driver motors.
BLOCK DIAGRAM:
POWER SUPPLY:
MICROCONTROLLER AT89S52
RPSL293D
INFRARED SENSOR
CRYSTAL ROBOTICPLATFORM
ULTRASONIC SENSOR
DESCRIPTION:
A robot can talk, walk, run and do anything as per logic embedded in it even
though the robot can do the above things. It seems a useless thing if it is uncontrollable.
Here controlling a robot is main task has to consider while designing any robot.
In this project an ultrasonic sensor is used to detect any obstruction and in turn
signals to the microcontroller and same displays on the LCD. An ultrasonic sensor is a
dual communication means transmitting and receiving. According to received data
vehicle will stop automatically.
Since robotic platform is equipped with two motors for the drive, controlling the
motors, i.e. When making a right turn, the right wheel can be stopped i.e. Power to the dc
motor is switched off. The left wheel is driven i.e. Left dc motor is on. This causes the
system to take a right turn. Similarly for left turn.
The detector circuitry consists of two ultrasonic integrated detection. The detector
houses the transmitter as well as receiver. The detectors are positioned accurately either
side. Once the detector recognizes any obstruction, the microcontroller signals the vehicle
to stop.
The system uses a compact circuitry built around flash version of at89s52
microcontroller with a non-volatile memory capable of retaining the password data for
over ten years. Programs are developed in embedded c using ride compiler. Isp is used to
dump the code into the microcontroller.
Step DownTransformer
BridgeRectifier
FilterCircuit Regulator
section
SOFTWARE:
Embedded ‘C’
RIDE to write code
ISP to burn the chip
HARDWARE:
At89s52 based our own developed board
Power Supply
Ultrasonic Sensor
H-Bridge driver motors
LCD
ADVANTAGES: Low cost, automated operation, Low Power consumption.
REFERENCES
1. The 8051 micro controller and embedded systems by Mazidi.
manufacturing cost. The need to juggle all these requirements makes embedded system
programming very challenging and is the reason why embedded system designers need to
understand computer architecture.
Overview of an Embedded System Architecture
Every Embedded system consists of a custom-built hardware built around a central
processing unit. This hardware also contains memory chips onto which the software is
loaded.
The operating system runs above the hardware and the application software runs above
the operating system. The same architecture is applicable to any computer including
desktop computer. However these are significant differences. It is not compulsory to have
an operating system in every embedded system. For small applications such as remote
control units, air conditioners, toys etc.
Applications of Embedded Systems
APPLICATION SOFTWAREOPERATING SYSTEM
H/W
Some of the most common embedded systems used in everyday life are
Small embedded controllers: 8-bit CPUs dominate, simple or no operating system (e.g., thermostats)
Control systems: Often use DSP chip for control computations (e.g., automotive engine control)
Distributed embedded control: Mixture of large and small nodes on a real-time Embedded networks (e.g., cars, elevators, factory automation)System on chip: ASIC design tailored to application area
(e.g., consumer electronics, set-top boxes)Network equipment: Emphasis on data movement/packet flow
(e.g., pacemakers, automatic trains)Signal processing: Often use DSP chips for vision, audio, or other signal Processing (e.g., face recognition)Robotics: Uses various types of embedded computing (especially Vision and control) (e.g., autonomous vehicles)Computer peripherals: Disk drives, keyboards, laser printers, etc.Wireless systems: Wireless network-connected “sensor networks” and “Motes” to gather and report informationEmbedded PCs: Palmtop and small form factor PCs embedded into EquipmentCommand and control: Often huge military systems and “systems of systems” (e.g., a fleet of warships with interconnected Computers)
Home Appliances, intercom, telephones, security systems, garage door openers,
answering machines, fax machines, home computers, TVs, cable TV tuner, VCR,
camcorder, remote controls, video games, cellular phones, musical instruments, sewing
AT89S52 Architecture consists of these specific features:
8 bit CPU with registers A (Accumulator) and B
16 bit Program Counter(PC) and Data Pointer (DPTR)
8 bit Program Status Word (PSW)
8 bit Stack Pointer (SP)
Internal ROM of 8k
Internal RAM of 128 bytes
Four Register banks each containing eight registers
Sixteen bytes, which may be addressed at the bit level
Eighty bytes of general purpose data memory
32 I/O pins arranged as four 8-bit ports: P0,P1,P2,P3
Two 16-bit Timers/Counters: T0 and T1
Full duplex serial data Receiver/Transmitter : SBUF
Control Registers: TCON, TMOD, SCON, SMOD, PCON, IP and IE.
Two external and three internal interrupt sources.
Oscillator and Clock circuits.
Pin Description
Pin ( 32 – 39 ) Port 0: Port 0 is an 8-bit open drain bidirectional port. As an open drain
output port, it can sink eight LS TTL loads. Port 0 pins that have 1s written to them float,
and in that state will function as high impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external memory. In this application it
uses strong internal pull ups when emitting 1s. Port 0 emits code bytes during program
verification. In this application, external pull ups are required.
Pin ( 1- 8 ) Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull ups. Port 1
pins that have 1s written to them are pulled high by the internal pull ups, and in that state
can be used as inputs. As inputs, port 1 pins that are externally being pulled low will
source current because of the internal pull ups.
Alternate Functions of Port 1 used for In system Programmable
P.5 MOSI --------- Instruction Input
P.6 MISO ---------- Data Output
P.7 SCK ----------- Clk in
Pin ( 21 – 28 ) Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull ups.
Port 2 emits the high-order address byte during accesses to external memory that use 16-
bit addresses. In this application, it uses the strong internal pull ups when emitting 1s.
Pin (10 – 17) Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull ups. It
also serves the functions of various special features of the 80C51 Family as follows:
Port Pin Alternate Function
P3.0- RxD (serial input port)
P3.1 -TxD (serial output port)
P3.2 -INT0 (external interrupt 0)
P3.3- INT1 (external interrupt 1)
P3.4 -T0 (timer 0 external input)
P3.5 -T1 (timer 1 external input)
P3.6 -WR (external data memory write strobe)
P3.7 -RD (external data memory read strobe)
Pin 40 VCC: -Supply voltage
Pin 20 VSS: -Circuit ground potential
Pin 29 PSEN: Program Store Enable is the read strobe to external Program Memory.
When the device is executing out of external Program Memory, PSEN is activated twice
each machine cycle (except that two PSEN activations are skipped during accesses to
external Data Memory). PSEN is not activated when the device is executing out of
internal Program Memory.
Pin 30 ALE/PROG: Address Latch Enable output pulse for latching the low byte of the
address during accesses to external memory. ALE is emitted at a constant rate of 1/6 of
the oscillator frequency, for external timing or clocking purposes, even when there are no
accesses to external memory. (However, one ALE pulse is skipped during each access to
external Data Memory.) This pin is also the program pulse input (PROG) during EPROM
programming.
Pin 31 EA/VPP: When EA is held high the CPU executes out of internal Program
Memory. Holding EA low forces the CPU to execute out of external memory regardless
of the Program Counter value. In the 80C31, EA must be externally wired low. In the
EPROM devices, this pin also receives the programming supply voltage (VPP) during
EPROM programming.
Pin 18 XTAL1: Input to the inverting oscillator amplifier.
Pin 19 XTAL2: Output from the inverting oscillator amplifier.
REGISTERS
8051 is a collection of 8 and 16 bit registers and 8 bit memory locations. These registers
and memory locations can be made to operate using the software instructions. The
program instructions control the registers and digital data paths that are contained inside
the 8051, as well as memory locations that are located outside the 8051.
Register are used to store information temporarily, while the information could be a byte
of data to be processed, or an address pointing to the data to be fetched. The vast majority
of 8051 register are 8-bit registers.
Generally there are two types of registers. They are General purpose Registers (GPR’s)
and Special Function Registers (SFR’s)
General Purpose Register
The 8 bits of a register are shown from MSB D7 to the LSB D0. With an 8-bit data type, any data larger than 8 bits must be broken into 8-bit chunks before it is processed.
The most widely used registers A (Accumulator) For all arithmetic and logic instructions B, R0, R1, R2, R3, R4, R5, R6, R7 DPTR (data pointer), and PC (program counter)
16 – bit General Purpose Register are Data Pointer (DPTR) and Program Counter (PC)
The program counter points to the address of the next instruction to be executed. DPTR.
As the name suggests, is used to point the data. It is used by a number of commands
which allows the microcontroller to access external memory. When the microcontroller
access external memory it will access at the address indicated by DPTR.
There are 128 bytes of RAM in the 8051
The 128 bytes are divided into three different groups as follows:
1) A total of 32 bytes from locations 00 to 1F hex are set aside for register banks and the
stack
2) A total of 16 bytes from locations 20H to 2FH are set aside for bit-addressable
read/write memory
3) A total of 80 bytes from locations 30H to 7FH are used for read and write storage,
called scratch pad
Special Function Registers
The program status word (PSW)PSW register, also referred to as the flag register, is an 8 bit register Only 6 bits are used
These four are CY (carry), AC (auxiliary carry), P (parity), and OV (overflow)
They are called conditional flags, meaning that they indicate some conditions that
resulted after an instruction was executed. The PSW3 and PSW4 are designed as RS0 and
RS1, and are used to change the bank. The two unused bits are user-definable
–
2.4 Timer/Counters
The Atmel 80C51 Microcontrollers implement two general purpose, 16-bit timers/
counters. They can be used either as timers to generate a time delay or as a counter to
count events happening outside the microcontroller. The microcontroller has two 16-bit
wide timers. They are identified as Timer 0 and Timer 1, and can be independently
configured to operate in a variety of modes as a timer or as an event counter. When
operating as a timer, the timer/counter runs for a programmed length of time, then issues
an interrupt request. When operating as a counter, the timer/counter counts negative
transitions on an external pin. After a preset number of counts, the counter issues an
interrupt request. Register pairs (TH0, TL0), (TH1, TL1), and (TH2, TL2) are the 16-bit
counting registers for Timer/Counters 0, 1, and 2, respectively.
Timer 0 Register
The 16-bit register of Timer 0 is accessed as low byte and high byte. The low byte
register is called TL0 (Timer 0 low byte) and high byte register is referred to as TH0
(Timer 0 high byte). These registers can be accessed like any other register, such as
A,B,R0,R1,R2,etc.
Timer 1 Register
Timer 1 is also 16-bits, and its 16-bit register is split into two bytes, referred to as TL1
( Timer 1 low byte ) and TH1 ( Timer 1 high byte ). These registers are accessible in the
same way as the registers of timer 0.
TMOD Register (timer mode)
TMOD: Timer/Counter Mode Control Register.
Not Bit Addressable.
Timer 1 Timer 0
GATE When TRx (in TCON) is set and GATE=1, Timer/CounterX will
run only while INTx pin is high (hardware control). When
GATE=0, Timer/Counter will run only while TRx=1 (software
control).
C/T Timer or Counter selector. Cleared for Timer operation (input from
internal system clock). Set for Counter operation (input from TX
input pin).
M1 Mode selector bit.
M0 Mode selector bit.
M1 M0 Mode Operating Mode
0 0 0 13-bit Timer (8048 compatible) (TH1)
0 1 1 16-bit Timer/Counter
1 0 2 8-bit Auto-Reload Timer/Counter (TL1). Reloaded from TH1 at overflow.
1 1 3 timer 1 halted. Retains count.
1 1 3 (Timer 1) Timer/Counter 1 stopped.
TCON: Timer/Counter Control Register
Bit Addressable.
TF1 Timer1 overflow flag. Set by hardware when the Timer/Counter 1
overflows. Cleared by hardware as processor vectors to the interrupt
service routine.
TR1 Timer 1 run control bit. Set/cleared by software to turn Timer/Counter 1
ON/OFF.
TF0 Timer0 overflow flag. Set by hardware when the Timer/Counter 0
overflows. Cleared by hardware as processor vectors to the service
routine.
THE LOWER 4 BITS
THE UPPER FOUR BITS ARE USED TO
TR0 Timer 0 run control bit. Set/cleared by software to turn Timer/Counter 0
ON/OFF.
IE1 External Interrupt 1 edge flag. Set by hardware when External terrupt
edge is detected. Cleared by hardware when interrupt is processed.
IT1 Interrupt 1 type control bit. Set/cleared by software to specify falling
edge/low level triggered External Interrupt.
IE0 External Interrupt 0 edge flag. Set by hardware when External Interrupt
edge is detected. Cleared by hardware when interrupt is processed.
IT0 Interrupt 0-type control bit. Set/cleared by software to specify falling
edge/low level triggered External Interrupt.
2.5 SERIAL COMMUNICATION
The 8051 serial port is full duplex. In other words, it can transmit and receive data at the
same time. Unlike any other register in the 8051, SBUF is in fact two distinct registers - the
write-only register and the read-only register. Transmitted data is sent out from the write-
only register while received data is stored in the read-only register. There are two separate
data lines, one for transmission (TXD) and one for reception (RXD). Therefore, the serial
port can be transmitting data down the TXD line while it is at the same time receiving data
on the RXD line. The TXD line is pin 11 of the microcontroller (P3.1) while the RXD line
is on pin 10 (P3.0)
Serial data communication uses two methods, asynchronous and synchronous. The
synchronous method transfers a block of data (characters) at a time, while the asynchronous
method transfers a single byte at a time. It is possible to write software to use either of these
methods, but the programs can be tedious and long. For this reason, there are special IC chips
made by many manufacturers for serial data communications. These chips can be commonly
referred to as UART (Universal Asynchronous Receiver-transmitter) and USART
( Universal Synchronous Asynchronous Receiver-Transmitter). The 8051 chip has a built-in
UART.
Asynchronous Serial Communication and Data Framing
Start Bits and Stop Bits
In the asynchronous method is character is placed between start and stop bits, this is called
data framing. In asynchronous communication, at least two extra bits are transmitted with the
data word; a start bit and a stop bit. Therefore, if the transmitter is using an 8-bit system, the
actual number of bits transmitted per word is ten. In most protocols the start bit is a logic 0
while the stop bit is logic 1. Therefore, when no data is being sent the data line is
continuously HIGH. The receiver waits for a 1 to 0 transition. In other words, it awaits a
transition from the stop bit (no data) to the start bit (logic 0). Once this transition occurs the
receiver knows a data byte will follow. Since it knows the data rate (because it is defined in
the protocol) it uses the same clock as frequency as that used by the transmitter and reads the
correct number of bits and stores them in a register. For example, if the protocol determines
the word size as eight bits, once the receiver sees a start bit it reads the next eight bits and
places them in a buffer. Once the data word has been read the receiver checks to see if the
next bit is a stop bit, signifying the end of the data. If the next bit is not a logic 1 then
something went wrong with the transmission and the receiver dumps the data. If the stop bit
was received the receiver waits for the next data word, ie; it waits for a 1 to 0 transition.
Baud Rates in the 8051
GOES OUT FIRST
XTAL OSCILLATOR
÷ 12 ÷ 32BY UART
MACHINE CYCLE FREQUENCY
28800 HZ
TO TIMER 1 TO SET THE BAUD RATE
921.6 KHZ
11.0592 MHZ
TIMER 1
XTAL = 11.0592 MHz:
The frequency of system clock = 11.0592 MHz / 12 = 921.6 kHz
The frequency sent to timer 1 = 921.6 kHz/ 32 = 28,800 Hz
(a) 28,800 / 3 = 9600 where -3 = FD (hex) is loaded into TH1
(b) 28,800 / 12 = 2400 where -12 = F4 (hex) is loaded into TH1
(c) 28,800 / 24 = 1200 where -24 = E8 (hex) is loaded into TH1
SBUF
SBUF is an 8-bit register used solely for serial communication in the 8051. For a byte of
data to be transferred via the TxD line, it must be placed in the SBUF register. Similarly,
SBUF holds the byte of data when it is received by the 8051’s RxD line. SBUF can be
accessed like any other register in the 8051.
The moment a byte is written into SBUF, it is framed with the start and stop bits and
transferred serially via the TxD pin. Similarly, when the bits are received serially via
RxD, the 8051 deframes it by eliminating the stop and start bits, making a byte out of the
data received, and then placing it in the SBUF.
DATA TRANSMISSION: -
Transmission of serial data bits begins anytime data is written to sbuf. " TI "
(SCON) set to 1 when data has been transmitted and signifies that " SBUF " is empty and
that another data byte can be sent.
DATA RECEPTION: -
Reception of serial data will begin if the receive enable bit (REN) in SCON is set
to ' 1 ' for all modes. For mode ' 0 ' only RI must be cleared to 0. Receiver interrupt flag '
RI ' (in SCON) is set after data has been received in all modes. Setting of ' REN ' bit is a
direct program control that limits the reception of unexpected data.
SCON ( Serial Control ) Register
SM0 SM1 SM2 REN TB8 RB8 TI RI
Mode 0: Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 the oscillator frequency.
Mode 1: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0),
8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special
Function Register SCON. The baud rate is variable.
Mode 2: 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th
data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity
bit (P, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8
in Special Function Register SCON, while the stop bit is ignored. The baud rate is
programmable to either 1/32 or 1/64 the oscillator frequency.
Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0),
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable.
In all four modes, transmission is initiated by any instruction that uses SBUF as a
destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN =
1. Reception is initiated in the other modes by the incoming start bit if REN = 1.
SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or
3, if SM2 is set to 1, then Rl will not be activated if the received 9th data bit (RB8) is 0.
In Mode 1, if SM2=1 then RI will not be activated if a valid stop bit was not received. In
Mode 0, SM2 should be 0.
REN Enables serial reception. Set by software to enable reception. Clear by software to
disable reception.
TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software
as desired.
RB8 In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is
the stop bit that was received. In Mode 0, RB8 is not used.
TI (Transmit Interrupt)
This is an extremely important flag bit in the SCON register. When the 8051 finishes the
transfer of the 8-bit character it raises the TI flag to indicate that it is ready to transfer
another byte. The TI bit is raised at the beginning of the stop bit.
RI ( Receive Interrupt)
This is an extremely important flag bit in the SCON register. When the 8051 receives
data serially via RxD, it gets rid of the start and stop bits and places the byte in the SBUF
register. Then it raises the RI flag bit to indicate that a byte has been received and chould
be picked up before it is lost.
INTERRUPTS
An interrupt is a special feature which allows the 8051 to provide the illusion of "multi-
tasking," although in reality the 8051 is only doing one thing at a time. The word
"interrupt" can often be substituted with the word "event."
An interrupt is triggered whenever a corresponding event occurs. When the event occurs,
the 8051 temporarily puts "on hold" the normal execution of the program and executes a
special section of code referred to as an interrupt handler. The interrupt handler performs
whatever special functions are required to handle the event and then returns control to the
8051 at which point program execution continues as if it had never been interrupted.
Interrupt Service Routine
For every interrupt, there must be an interrupt service routine (ISR). Or interrupt handler.
When an interrupt is invoked, the microcontroller runs the interrupt service routine. For
every interrupt, there is a fixed location in memory that holds the address of its ISR. The
group of memory locations set aside to hold the addresses of the ISRs is called interrupt
vector table.
Six Interrupts in 8051
1. Reset : When the reset pin is activated, the 8051 jumps to address location 00002. Two interrupts are set aside for the timers: one for the Timer 0 and one for
Timer1.
3. Two interrupts are set aside for hardware external interrupts : one for INT0 and one for INT1
4. Serial communication has a single interrupt that belongs to both receive and transmit.
Enabling Interrupt (IE) Register
All interrupt are disabled after reset
We can enable and disable them bye IE
EA -- ET2 ES ET1 EX1 ET0 EX0
EA IE.7 If EA=0, disables all interrupts, no interrupt is acknowledged
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.
-- IE.6 Not implemented, reserved for future use.
ET2 IE.5 Enables or disables Timer2 overflow or capture interrupt
(8052 only)
ES IE.4 Enables or disables the serial port interrupt.
ET1 IE.3 Enables or disables Timer 1 overflow interrupt.
EX1 IE.2 Enables or disables external interrupt 1.
ET0 IE.1 Enables or disables Timer 0 overflow interrupt.
EX0 IE.0 Enables or disables external interrupt 0.