Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines Arash Saifhashemi Peter A. Beerel University of Southern California USC Asynchronous CAD/VLSI Group (async.usc.edu) (Thanks to a grant from Intel and NSF) Patmos 2012, Sep 2012, Newcastle upon Tyne
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Observability Conditions and Automatic Operand- Isolation in High-Throughput Asynchronous Pipelines Arash Saifhashemi Peter A. Beerel University of Southern.
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Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous
PipelinesArash Saifhashemi
Peter A. Beerel
University of Southern California
USC Asynchronous CAD/VLSI Group (async.usc.edu)
(Thanks to a grant from Intel and NSF)
Patmos 2012, Sep 2012, Newcastle upon Tyne
Asynchronous Circuit Design - Today
Applications
• 3D Network on chips (STMicroelectronics)
• Ethernet Switches (Intel SRD)
• Ultra high-speed FPGAs (Achronix)
• Process variation
• Low-power chip design (Encryption – Tiempo, …)
Basic challenges: Automation
Proteus design flow (USC)
• Uses commercial synchronous CAD tools
• Starting at a high-level specification written in SVC (SystemVerilogCSP)