Objective Questions Module 1: Introduction 1. Which of the following is an analog quantity? (a) Light (b) Temperature (c) Sound (d) all of these 2. Which of the following is a digital quantity? (a) Electrical conductivity (b) Electric field (c) Magnetic field (d) Switch 3. A device that transforms analog signal into digital is (a) Sampler (b) Converter (c) Decoder (d) Encoder 4. Which is the theorem that provides an important guidelines as to how much digital data is needed to accurately port ray a given analog signal (a) Nyquist- Shannon sampling (b) Boolean Algebra (c) Huntington Postulates (d) Bode 5. Digital signals are (a) Discrete (b) continuous (c) periodic (d) None of these 6. Which of the following represent an analog quantity? (a) Number of atoms in a matter (b) Altitude of an aircraft (c) Number of trees (d) Number of words 7. Which of the following can furnish digital signal (a) Sine wave (b) Square wave (c) Triangular wave (d) Slow changing of a POT 8. Which of the following is a digital quantity (a) Current flowing from an electrical outlet (b) Temperature of a room (c) Sand grain on the beach (d) Automobile fuel gauge. 9. In positive logic, the high voltage level of a digital signal is (a) 1 (b) 0 (c) -1 (d) either 1 or 0 Page 1 of 20
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Objective Questions
Module 1: Introduction
1. Which of the following is an analog quantity?
(a) Light (b) Temperature (c) Sound (d) all of these
2. Which of the following is a digital quantity?
(a) Electrical conductivity (b) Electric field (c) Magnetic field (d) Switch
3. A device that transforms analog signal into digital is
(a) Sampler (b) Converter (c) Decoder (d) Encoder
4. Which is the theorem that provides an important guidelines as to how much digital
data is needed to accurately port ray a given analog signal
66. Petrick’s method is used to determine __________ expressions.
(a) Boolean (b) Redundant (c) Irredundant (d) None of these
67. ________ must also appear in all the irredundant disjunctive normal formulae of the
function
(a) Essential Prime Implicants (b) All Prime Implicants
(c) Both (a) & (b) (d) None of these
68. The type of expression that can be minimized using K-map is
(a) Exclusive OR
(b) Product-of-sums
(c) Sum-of-products
(d) Those with overbars literals
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69. The NOT ALLOWED condition in SR flip flop with only NAND gates occurs when: a) S=0, R=0
b) S=0, R=1
c) S=1, R=1
d) S=1, R=0
70. The next state of D flip-flop truth table Qn+1 shown is: Truth Table Choose the Answer
D Qn Qn+1
0 0 ?
0 1 ?
1 0 ?
1 1 ?
71. The next state of JK flip-flop truth table Qn+1 shown is:
Truth Table Choose the Answer
72. For which of the following flip flop the output is clearly defined for all combinations
of two input?
a) D flip flop
b) JK flip flop
c) Clocked SR flip flop
d) None of these
(a) (b) (c) (d)
0 1 0 1
0 1 1 0
1 0 1 1
1 1 0 0
J K Qn Qn+1
0 0 0 ?
0 1 0 ?
0 0 0 ?
1 1 0 ?
(a) (b) (c) (d)
0 0 0 1
1 0 1 0
1 1 1 1
0 1 1 0
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73. Upon clock transition, at which of the following input condition do the JK flip flop be
in set state?
a) J=0, K=0
b) J=0, K=1
c) J=1, K=0
d) J=1, K=1
74. Upon clock transition, at which of the following input condition do the output of the clocked
JK flip flop toggles?
a) J=0, K=0
b) J=0, K=1
c) J=1, K=0
d) J=1, K=1
75. The output Q of the Master Slave JK flip flop sets at positive clock transition when:
a) J=1, K=0
b) J=0, K=1
c) J=0, K=0
d) J=1, K=1
76. The Q output of JK flip flop will be high when:
A) Preset=1, Clear=0
B) Preset =0, Clear =1
C) Preset =0, Clear =0
D) Preset =1, Clear =1
77. One of the applications of SR flip flop is:
a) Astable oscillator
b) Binary storage register
c) transition pulse generator
d) All of these
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78. Which of the following statement is correct for a gated D latch?
a) Only one of the inputs can be HIGH at a time.
b) The output toggles if one of the inputs is held HIGH
c) The output complement follows the input when enabled.
d) The output Q follows the input D when the enable is HIGH
79. In a positive edge-triggered S-R flip-flop, the change in outputs occurs when:
a) The clock pulse is LOW.
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
80. The symbol on SR flip-flop device shown in figure indicate that:
a) Triggering takes place on the negative-going edge of the CLK pulse
b) Triggering takes place on the positive-going edge of the CLK pulse
c) Triggering can take place anytime during the HIGH level
of the CLK waveform
d) Triggering can take place anytime during the LOW level
of the CLK waveform
81. One shortcoming of SR flip flop is:
a) It has only a single output.
b) It has an invalid state.
c) It has no enable input.
d) It has no clock input.
82. Latches that are constructed with NOR and NAND gates tend to remain in the latched
condition because of:
a) Low input voltages.
b) High gate impedance
c) Asynchronous operation
d) Cross coupling configuration
CLK
S Q
R Q
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83. A gated S-R latch and its associated waveforms are shown in figure. Suggest the
suitable answer?
a) The Q output is always low; the circuit is defective.
b) The Q output should be the complement of the Q output; the S and R terminals
are reversed.
c) The Q should be following the R inpsut; the R input is defective.
d) There is nothing wrong with the circuit.
Module 8: Transistor-Transistor Logic (TTL)
84. The switching speed of TTL is a) Similar as that of CMOS b) Slower than CMOS c) One-half as that of CMOS d) One-third as that of CMOS
85. A TTL IC operating from a 5-volt supply will consume
a) less power than a CMOS IC
b) more power than a CMOS IC
c) the same power as a CMOS IC
d) Zero power
86. The active switching element used in all TTL circuits is the
(a) BJT (b) UJT (c) MOSFET (d) FET
CLK
S Q
R Q
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87. Emitter coupled logic is also called as (a) Power Steering Logic
(b) Current Steering Logic
(c) Voltage Steering Logic
(d) None of these
88. Which of the following statement best describes the characteristics of ECL gate
(a) Logic levels are positive, +0.9V for a logic 1 and +1.7V for a logic 0
(b) Logic levels are negative, –0.9V for a logic 1 and –1.7V for a logic 0
(c) Logic levels are positive, +0.9V for a logic 1 and –1.7V for a logic 0
(d) Logic levels are negative, –0.9V for a logic 1 and +1.7V for a logic 0
Module 9: CMOS Logic 89. The configuration of CMOS IC is in the form of
a) SOIC configuration
b) DIP configuration
c) SOIC and DIP configurations
d) None of the above
90. The drawback of CMOS over TTL is that CMOS is a) Highly expensive
b) Slow
c) Sensitive to electrostatic discharge
d) Not widely available
91. The full forms of the abbreviations TTL & CMOS in reference to the logic families are a) Triple Transistor logic and Chip Metal Oxide Semiconductor
b) Tristate Transistor Logic and Chip Metal Oxide Semiconductor
c) Transistor Transistor Logic and Complementary Metal Oxide Semiconductor
d) Transistor Transistor Logic and Complementary Metal Oxide Silicon
92. The transistor element used in CMOS logic is a) FET b) BJT c) MOSFET d) UJT
93. The fan – out of CMOS is a) Very Low because it draws almost zero current b) Very High because it draws almost zero current c) Very Low because it draws heavy current d) Very High because it draws heavy current
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Module 10: Memories
94. The memory storage device used in a static RAM is a) Resistor
b) Capacitor
c) Diode
d) Flip-Flop
95. The timing parameters that decide the operating speed of a RAM are
a) tRC and tWC
b) tCO and tACS
c) tAA and tOD
d) tACC and tRC
96. Read-Only Memory is best described by one of the following statement:
a) Volatile, and used to store information that changes during system operation
b) Volatile, and used to store information that does not change during system
operation
c) Non-volatile, and used to store information that does not change during system
operation
d) Non-volatile, and used to store information that changes during system operation
97. To construct a 32K × 8 memory system, number of 2K × 8 ROM chips required are a) 2 b) 4 c) 8 d) 16
98. For the circuit given below, which of the following is correct?
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a) Decimal number 10 is being written to the memory at address location 110.
b) Decimal 13 is being written into memory location 141.
c) The Read/Write line is LOW; therefore, decimal 5 is being stored at memory
location 141.
d) Since the EN terminal is 0; the chip has not been enabled, hence, nothing will be
written to the chip.
99. Volatile memory is
a) The memory that loses stored information when electrical power is removed.
b) The memory that retains stored information when electrical power is removed.
c) The magnetic memory.
d) The nonmagnetic memory.
100. Memory device that have smallest bit size and largest bit size are respectively
a) Static RAMs and Mask ROMs.
b) Mask ROMs and Static RAMs.
c) EEPROMs and Flash.
d) DRAM and PROM.
101. One of the chief advantage of using address multiplexing with DRAM memory is
a) User-programmable, reprogrammable.
b) Reduced requirement for constant refreshing of the memory contents.
c) Reduced memory access time.
d) Reduced pin count and decrease in package size.
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ANSWER KEY OF OBJECTIVE QUESTIONS
1. d 2. d 3. a 4. a 5. d 6. b 7. c 8. a 9. a 10. b 11. a 12. a 13. a 14. d 15. a 16. d 17. a 18. a 19. b 20. c 21. a 22. d 23. b 24. d 25. d 26. b 27. a 28. c 29. d 30. b 31. a 32. a 33. a 34. d 35. a 36. b 37. a 38. a 39. d 40. a 41. a
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42. d 43. b 44. d 45. b 46. a 47. b 48. c 49. c 50. c 51. c 52. b 53. c 54. b 55. a 56. a 57. b 58. c 59. b 60. b 61. b 62. a 63. d 64. c 65. a 66. c 67. a 68. c 69. c 70. a 71. b 72. b 73. c 74. d 75. a 76. b 77. b 78. d 79. c 80. a 81. b 82. d 83. a 84. a 85. b
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86. a 87. b 88. b 89. c 90. c 91. c 92. c 93. b 94. d 95. a 96. c 97. d 98. b 99. a 100. c 101.d