The PSP compact MOSFET model An update Gert-Jan Smit , Andries Scholten, D.B.M. Klaassen — NXP Semiconductors Ronald van Langevelde — Philips Research Europe Gennady Gildenblat, Weimin Wu, Xin Li, Amit Jha, Hailing Wang* — Arizona State University; *now at IBM MOS-AK, Montreux, September 22, 2006
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and reverse)– diode reverse breakdown– noise (1/f, thermal, induced gate and
shot noise)– non-quasi-static effects– gate and bulk resistances– STI stress effect
See also MOS-AK 2005
MOS-AK, Montreux, September 22, 2006
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Update PSP 102.0
Changes PSP 100.0 102.0– Binning– Improved Gummel symmetry (modified CLM-model and VB-clamping)– Replaced lateral gradient factor– More flexible geometry scaling– Improved mobility model (CS, FETA, scaling)– Improved forward bulk-bias behavior– BSIM-like instance parameters for JUNCAP2 (AS, AD, PS, PD)– Several minor improvements, bug fixes, and maintenance– October 2006: PSP 102.1 includes first C-implementation of NQS-model
Partly based on useful feedback by Jazz, Infineon, Freescale, STm, RFMD, Analog Devices, …
MOS-AK, Montreux, September 22, 2006
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Outline
History & overview
DC verification on 65nm technology
Symmetry and distortion
Non-quasi static effects
Summary & references
MOS-AK, Montreux, September 22, 2006
9
Long channel (65nm technology)
Drain current and output conductance
W/L = 10/1µm, VGS = 0…1V
0.0 0.2 0.4 0.6 0.8 1.0 0.0
0.2
0.4
0.6
0.8
1.0
V DS (V)
I D (
mA
)
0.0 0.2 0.4 0.6 0.8 1.0 10 -910 -8
10 -7
10 -6
10 -5
10 -4
10 -3
10 -2
V DS (V)
g DS
(A/V
)
measurementPSP
MOS-AK, Montreux, September 22, 2006
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Short channel (65nm technology)
Drain current and output conductance
W/L = 10/0.04µm (poly length = 40nm), VGS = 0…1V
0.0 0.2 0.4 0.6 0.8 1.0 0
2
4
6
8
V DS (V)
I D (
mA
)
0.0 0.2 0.4 0.6 0.8 1.0 10 -7
10 -6
10 -5
10 -4
10 -3
10 -2
10 -1
V DS (V)
g DS
(A/V
)
measurementPSP
MOS-AK, Montreux, September 22, 2006
11
Gate current (65nm technology)
Gate current
W/L = 10/1µm, VDS = 0…1V
PSP model has been verified to successfully describe various 90nm, 65nm and 45nm processes
-1.0 -0.5 0.0 0.5 1.0 10 -10
10 -9
10 -8
10 -7
10 -6
V GS (V)
I G (
A)
measurementPSP
MOS-AK, Montreux, September 22, 2006
12
R2R-circuit
Benchmark test for quality of integral along channel
Ideal long channel model
10 -1 10 0 10 1 10 2 0.00
0.05
0.10
0.15
I fs ( µ A)
rel.
erro
r (%
)
1
2
36
fs
fs12error rel.I
IInn −⋅=
−
∫ ⋅⋅−=DB
SB
dinvDS
V
V
VqL
WI µ
MOS-AK, Montreux, September 22, 2006
13
Outline
History & overview
DC verification on 65nm technology
Symmetry and distortion
Non-quasi static effects
Summary & references
MOS-AK, Montreux, September 22, 2006
14
Gummel symmetry (i)
CMOS devices are symmetric w.r.t. source/drain
Imposed on the model by applying source/drain interchange
Guaranteeing a smooth connection at VDS=0 is nontrivial