NV-Memory Elements with Gate-All-Around Transistors - SRC · SRC/NSF/A*STAR Memory Forum, Oct. 20-21, 2009. Outline • Motivation – Si-Nanowire/-Pillar Platform – Application

NV-Memory Elements with Gate-All-Around

Transistors

Patrick Lo Guo-Qiang

Institute of Microelectronics, A*STAR, Singapore

SRC/NSF/A*STAR Memory Forum, Oct. 20-21, 2009

Outline•

Motivation–

Si-Nanowire/-Pillar Platform –

Application

–

Channel Control, Density, Performance

•

Integration Feasibility•

Examples of NV-Memory Devices

Nanowire/Pillar Technology Platform & Applications

CMOS Devices Beyond 22nm

Integrated OEIC Sensor Array

μ−Chip-NW-TEG, TEC

Technology Platform

Drain

Are

a =

4F2

Gate

Source

2F

2F

Drain

Are

a =

4F2

Gate

Source

2F

2F

Are

a =

4F2

Gate

Source

2F

2F

Vertical SGT, A new paradigm

2 NW NMOS

OUTPUTINPUT

VDD

GND

6 NW PMOS

2 NW NMOS

OUTPUTINPUT

VDD

GND

6 NW PMOS

Low-Power Logic & High- Density NVM

Biosensor Array with μ-fluidic channels

Integrated Energy Harvesting & Storage

Gate-All-Around: a Candidate for Sub-22 nm Nodes Electrostatics Analysis at LG

= 10 nm (EOT= 2 nm)

60

70

80

90

100

110

120

130

140

150

0 5 10 15Silicon thickness (nm)

SS (m

V/de

c)

SOI (tbox=100 nm)SOI (tbox=20 nm)SOI (tbox=2 nm)DGCNW

tbox

0

100

200

300

400

0 5 10 15Silicon thickness (nm)

DIB

L (m

V/V)

SOI (tbox=100 nm)SOI (tbox=20 nm)SOI (tbox=2 nm)DGCNW

tbox

Only GAA nanowire fulfills the requirement of gate electrostatics with the condition that channel dimension ≤

LG

(LG

/TSi

~1).

Devices can be scaled to sub-10 nm technology nodes!

E. Gnani et al.; ESSDERC 2006

(GAA NW)(GAA NW)

Lg /Tsi ~5 Lg /Tsi ~2

Lg /Tsi ~1

5

Effective Scaling of Gate Dielectric

,)(ox

oxox t

planarC ε=

⎟⎟⎠

⎞⎜⎜⎝

⎛+

=

si

oxsi

oxox

ttt

GAAC21ln

2

)( ε

tsi

gate

tox

•

Tox|Electrical can be <Tox|Physical ; •

Reduction in EOT is possible by thinning the Si-body dimension.

2 4 6 8 100

2

4

6

8

10

CNW

3 nm5 nm10nm

Planar

EOT(

nm)

Tox(nm)

High E-Field in Tunnel Layer

3x enhancement in E-field

--x reduction in barrier width

Field Enhancement is achieved with Nano-Structure(Collaboration: UOB)

More Fundamental Limitation and ImplicationVertical Stacked

n-, p-MOSFETPlanar, e.g., n-MOS

Area = 8F2 Area = 4F2

DrainSource

Gate

2F

4F

Drain

Gate

Source

2F

2F

F:

Feature sizeFUNDAMENTAL BENEFIT with VERTICAL SCHEME: •

Device area: Shrunk by ~50% from Planar

If consider n- and p-MOSFET together for circuit, •

Circuit area: Shrunk by >70%

• Speed: Improve by ~6.1x faster

• Power: Reduce by ~3.3x lower

DrainGateSource

2F

4F

Area = 8F2

Horizontal Laid, e.g., n-MOSFET

High-Performance & High-Density NVM

Performance via Nano-Structure

Ver

tical

Mul

ti-C

ell I

nteg

ratio

n on

[Gate-All-Around;nm-scale wire]

[VerticallyStacked Cells]

NV-Memory Device Performance (Horizontal)

O/N/O=5nm/5nm/7nm

NW diameter~5nm Si-Nano-Crystals on Si3

N4

: 7.5 ×109 cm-2

10-7 10-6 10-5 10-4 10-3-3-2-1012345

(c)NW ERS: -11V

NW PGR: 11V

Ref. PGR: 11V

Ref. ERS: -11V

ΔVTH

(V)

Time (s)

Wire-NVM

Planar, FiN-NVM

10-7 10-6 10-5 10-4 10-3

-4

-2

0

2

4

Time (s)

Δ V

th (V

)

Solid: Program, Vp=10V

Open: Erase, Ve= -10V

TLE SONOS SONOS

Wire Diameter Impact

0 5 10 15 200.0

0.5

1.0

1.5

5 nm 8 nm

Si

E-Fi

eld

(1e7

V/c

m)

Position (nm)

Planar

GAA NW

O N O

Field can be simply increased with narrower-diameter to Improve the P/E performance

10-7 10-6 10-5 10-4 10-3 10-2-5-4-3-2-101234

Open: Erase, Ve=-10V

Δ V

th (V

)Time (s)

circle dia=5 nmtriangle dia=8 nm

Solid: Program Vp=9V

(Collaboration: UOB)

Impact of High-κ

Storage PVD TaN

ALD Al2

O3

TEOS SiO2

ALD HfO2Nanowire5 nm

7 nm

10 nm

200 nm

10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101

-2

-1

0

1

2

3

4

5

6

7

8 NW-TAHOS ERS: VG= -10V ERS: VG= -11V ERS: VG= -12V

PGM: VG=10V PGM: VG=11V PGM: VG=12V PGM: VG=13V

Thr

esho

ld V

olta

ge V

th [V

]

Pulse width [second]

10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101

PGM: VG=10V PGM: VG=11V PGM: VG=12V PGM: VG=13V

Pulse width [second]

ERS: VG= -10V ERS: VG= -11V ERS: VG= -12V

NW-SONOS

-1 0 1 2 3 410-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

SS=94mV/dec, DIBL=46mV/V

Vd=0.05V

Vd=1.2V

Gate voltage Vg (V)

I d (A

)

TaN/Al2O3/HfO2/SiO2/Si

Vertical Pillar based SONOS NVM

gate

nano

wire

gate50 nm

S

D

chan

nel

SONOS

SONOS

gate

nano

wire

gate50 nm

S

D

chan

nel

SONOS

SONOS

Bottom

Top

[Toh

oku

Uni

v./T

ED

’05]

Objective:-

Develop scalable high-density and high performance memory devices

Approaches:-

Multi-cells implementation on single Pillar Vertically

-

P/E field-enhancement via Surrounded Gate on nano-pillar

Multi-bit Programmable SONOS NVM on Pillar

1 2 3 4 5 6 7 80

20

40

60

80

100

ERS

'11''01''00' '10'

PGM 10V

Vt (V)

PGM 12V PGM 15V

Cum

ulat

ive

Occ

urre

nce

(%)

•

P/E speed Improvement with reduced diameter (50 20nm),•

Well distributed Programming Vt

: 2-bit storage/Cell Possible,•

Good retention and Endurance.

10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100

-3-2-10123456

Dia=50nm Dia=45nm Dia=20nm

ERS (Vg=-15V 1ms)

VT S

hift

(V)

Time (s)

PGM (Vg=15V 1ms)LG

=0.2 µm