NTD/xNTD Signal Processing

NTD/xNTD Signal Processing

Presented by: John BuntonSignal Processing team: Joseph Pathikulangara, Jayasri Joseph,

Ludi de Souza and John BuntonPlus collaboration MIT, SKA South Africa

23 November 2005

www.ict.csiro.auTasks

Full NTD/xNTD beamformer (same for both) About 1 Tbit/s input Will take time, but want something useable now

Prototype beamformer Reduced bandwidth and number of inputs

NTD correlator Only one baseline Do it in the beamformer

And eventually xNTD correlator Not needed for some time Initial design done Probably parallel development with SKAMP, LFD, ???

www.ict.csiro.auPrototype beamformer

Reduced specification 24 MHz bandwidth, 24 inputs (expandable to 48) Single channel FX correlator

Hardware based on MIMO test bed 4-input ADC board available but not populated

Needed six place mother board Board to board data

28 pairs each 560Mbits/s

2 pairs for our beamformer Motherboard up to

112 pairs plus USB Hardware Complete SFDR >70dB

www.ict.csiro.auFirmware for Prototype Beamformer

All units identical Real to complex

conversion Ring beamformer

12bit coefficients

Selectable input to 1k filterbank

Muxes in ring to allow selection of single input to filterbank or sum of 2 to 24 inputs.

Input to correlator from previous unit.

Upgradeable to 4 or more beams and at least 3 correlations

A/DReal to

Complex X +

Gain

A/DReal to

Complex X +

Gain

A/DReal to

Complex X +

Gain

A/DReal to

Complex X +

Gain

Filterbank

X

a

0

b

0

Accumulator(Doublebuffered)

Beam sum tonext module

Filterbank tonext module

Filterbank fromprevious module

Beam sum fromprevious module

To USBinterface

c

www.ict.csiro.auSoftware for Prototype Beamformer

USB interface to PC Selectable integration time down to 40ms PC GUI collects data and displays it dynamically Firmware and Software for operation as RFI

measurement system complete

Spectrum in Lab

0

10

20

30

40

50

60

0 5 10 15 20 25

Frequency MHz

Po

we

r d

B

www.ict.csiro.auNTD/xNTD Beamformer

96 dual pol. inputs each 660MS/s and 8bits 1 Terabit/s

Output 33 dual pol. beams. 163Gbits/s

32 channelPolyphase

Output 15x23MHzcomplex

32 channelPolyphase

Output 15x23MHzcomplex

~660 MS/s Real

~660 MS/s Real

Inputs from 96dual polarisation

feeds(192 signals)

Beamformer33x2 beam

23 MHz

Beamformer33x2 beam

23 MHz

33x2 beams309MHz309 MS/s

(4R,4I) complex163 Gbits/s

to centralcorrelator andbeamformer

20.6MHz4k ChannelPolyphase

20.6MHz4k ChannelPolyphase

CrossConnectOutputs23MHz

allsignals toeach BF

www.ict.csiro.auCross connects

Too much data to do beamformer on single board (1Terabit/s data)

Too much data to do beamformer in single card cage

How do we interconnect?

Two technologies – one connector RJ45 LVDS– 4 pairs each 800MS/s=3.2Gbit/cable

• Limited by clock jitter

Rocket I/0 over 2.5Gbits/s per pair = 10Gbit/cable (10GBASE-CX4)

With Rocket I/O fit six 23 MHz bands per pair – 120 cables (4 pairs per cable)

Development board to be built to test data transport will include LVDS and Rocket I/O over RJ45 and optical

Plus short interconnects on backplane

www.ict.csiro.auKISS your troubles goodbye

With the interconnect problem solved (a necessity) we are free to partition the hardware in any way we want

Plan to follow the KISS principle: Keep It Simple – Stupid Each module with have a defined function Module design will have a linear data flow (if possible) The designs will attempt to minimise interconnect (correlation cell) Boards must be easy to route – easy to adopt next gen. FPGA

Adaptability of the design depends on programmability of FPGA Eg Second Filterbank could select 4MHz to give 1kHz resolution

Ability to reroute data (in FPGA) Eg Same data to two beamformers to get 66 beams half bandwidth

Ability to reroute RJ45 cables Add extra modules

For more flexibility add a commercial router (add 33% to cost)

www.ict.csiro.auxNTD Beamformer

Break it up into two sections

Input ADCs plus oversampling polyphase filterbank Prototype being tested

6U board with 8 channels – full system needs 24 boards

23MHz beamformer and 20.6MHz second stage filterbank (TBD)

32 channelPolyphase

Output 15x23MHzcomplex

32 channelPolyphase

Output 15x23MHzcomplex

~660 MS/s Real

~660 MS/s Real

Inputs from 96dual polarisation

feeds(192 signals)

Beamformer33x2 beam

23 MHz

Beamformer33x2 beam

23 MHz

33x2 beams309MHz309 MS/s

(4R,4I) complex163 Gbits/s

to centralcorrelator andbeamformer

20.6MHz4k ChannelPolyphase

20.6MHz4k ChannelPolyphase

CrossConnectOutputs23MHz

allsignals toeach BF

www.ict.csiro.auFirst stage Filterbank

Divide and conquer 32 point first stage filterbanks generate ~23MHz bands (also does real

to complex conversion) Will discard outer two bands gives 15 useable bands

Oversampling filterbank to allow access to all frequencies Oversampling by 8/7 (320MS/s 8 point version working)

Will discard redundant channels at output of second filterbank

Channel N

Channel N+1

Channel Edge

Aliasing

Critically Sampled

Channel N

Channel N+1

Aliasing

Channel Edge

Channel Edge

Oversampled

www.ict.csiro.auBeamformer and Second Filterbank

All antenna data on single beamformer board

15 boards each with 192 inputs, 23MHz bands

All beams on single board, Single FPGA to do beamforming if each beam is sum of 20 single polarisation signals.

Only 20 weights per beam 660 weights for each board

Could need dual polarisation to get purity, or more inputs to increase A/Tsys up to 4 FPGAs

Single FPGA to do final filterbank but it is memory intensive

Need DRAM to buffer data into filterbanks

Will include time multiplexed correlators for calibration

Design to be finalised when specification known

www.ict.csiro.auxNTD Correlator

2 beams per fibre – process eight antennas on a single Router/Buffer board

Single beam correlator two pairs of FPGAs (Virtex SX35) for correlation

One input FPGA per pair (Virtex FX) and one Long Term Acc. Five boards total for two beams

Correlator for single beamRocket I/O Links

8 antenna2 beam

Router andBuffer

8 antenna2 beam

Router andBuffer

8 antenna2 beam

Router andBuffer

Beam 1 HFRouter and data

serialiserXC4VFX20

Beam 1 LFRouter and data

serialiserXC4VFX20

HF CorrelatorBeam 1

2 x XC4VSX35

LF CorrelatorBeam 1

2 x XC4VSX35

Correlator Board

LTA

DDR2

DDR2 DDR2

LTA

DDR2

DDR2 DDR2

www.ict.csiro.auRouter and Buffer

I/O to correlator chip a bottleneck

Have ~60,000 frequency channels

Correlator board processes one channel at a time Output data rate very high

Buffer data on input board and process 256 time samples per frequency channel at a time

Rocket I/O Links

8 antenna2 beam

Router andBuffer

8 antenna2 beam

Router andBuffer

8 antenna2 beam

Router andBuffer

Beam 1 HFRouter and data

serialiserXC4VFX20

Beam 1 LFRouter and data

serialiserXC4VFX20

HF CorrelatorBeam 1

2 x XC4VSX35

LF CorrelatorBeam 1

2 x XC4VSX35

Correlator Board

LTA

DDR2

DDR2 DDR2

LTA

DDR2

DDR2 DDR2

www.ict.csiro.auLFD Correlator

8 stations16 tiles

Router/ Buffer

8 stations16 tiles

Router/ Buffer

8 stations16 tiles

Router/ Buffer

8 stations16 tiles

Router/ Buffer

pairs of outputseach 1.33 MHz

Router anddata

serialiser

Router anddata

serialiser

Router anddata

serialiser

Router anddata

serialiser

Correlator

Correlator

Correlator

Correlator

Router anddata

serialiser

Router anddata

serialiser

Correlator

Correlator

LTA

DDR2

DDR2 DDR2

LTA

DDR2

DDR2 DDR2

LTA

DDR2

DDR2 DDR2

LTA

DDR2

DDR2 DDR2

LTA

DDR2

DDR2 DDR2

LTA

DDR2

DDR2 DDR2

IntermediateRouter4 MHz

www.ict.csiro.auCorrelation Cell

Standard systolic array design over 208 LVDS inputs

Solution – Correlation Cell

Provide storage for two sets of data 16 values each

Sixteen times reduction in I/O per multiplier

xNTD uses groups of 4 cells

Input reduced to 96 LVDS for xNTD

Dual PortMemory

Complex multiplierResources one 18-bit multipliers

Dual 4+4 bit inputs - 9+9 bit output

Single Dual Port Memory - 2 x 256 36-bit words

+

Data loading

Two 4+4 bitoutputs

18+18 bit outputs

Dual PortMemory

MUX MUX

Latch Latch

8-bit shift register

Serial input data

36-bit sh

ift reg

ister

Serial output data

8-bit shift register

www.ict.csiro.auPossible pulsar de-disperser

Break into 8 MHz bands

Continuous convolution of bands (120ns time resolution)

Dispersion up to 480 us

Multiple DMs per V4SX35 de-disperser

Folding as well de-disperserband 1

de-disperserband 2

de-disperserband 16

Analysis filterbank256 point

8/7 or 16/15oversampling

2GS/s

127 bands 8 MHz

8 bands perconection

De-disperser has8k FFT (4k + zero pad)

phase correction8k IFFT

Generates 8k blocksEquivalent to continuous convolution

8 MHz de-dispersed

bands

www.ict.csiro.auQuestions ?

www.ict.csiro.auContacts

John BuntonSenior Principle Research ScientistICT CentreTel: +61 2 9372 4420Email: john,[email protected]

For more information, see www.csiro.au or contact: