November 27, 2002 RMU-CPU Interface - Version 1.8 RMU - CPU Interface.

November 27, 2002RMU-CPU Interface - Version 1.8

RMU - CPU Interface


Release 1.3 Changes

• Added overrun bit to the status word

• needed a second command status word

• Added a 1 Hz signal (1PPS) to phase lock the RMU to the 1 Hz timing pulse from the spacecraft

• Added enable/inhibit for the 1PPS function

• Added tw(min) for CPU strobes = 250 ns

• Added definition of science packet


Release 1.4 Changes

• Changed test pattern definitions

• Resized Little Pulse storage for 15 pulses


Release 1.5 Changes

• Changed definition of bits for Most Significant Byte for Start, Big Pulse and Little Pulse

• Added Status/Mode Word 3 (programmable fine time circuit reference value - bit definition TBD)


Release 1.6 Changes

• Changed definition of bits for all timestamps (Start, Big Pulse and Little Pulse)

• Added 4th byte for Start Pulse


Release 1.7 Changes

• Added Status Word 3

• Redefined bits in Status Word 2


Release 1.8 Changes

• Finalized defs in Status Words 1, 2 and 3


RMU - CPU SIGNALS

RMU

CPU

RUPT

• FPGAs = SX-S; All drivers low slew, always enabled.• Receivers are set to 5V CMOS switching thresholds.• Receiving side provides bus hold, 10 k resistor.• RMU may be powered off with CPU powered on.• Parity is odd.

RMU_DATA[7:0]

CPU_DATA[7:0]

CPU_ADDR[3:0]

CPU_RD

CPU_WR

CPU_SPARE1CPU_SPARE0

RMU_SPARE0

RMU_SPARE1

RMU_PARITY

1PPS


RMU Address Map0000 READ SCIENCE DATA (FIXED BLOCK, SIZE TBD)0001 READ/WRITE RANGE GATE START LOW BYTE0010 READ/WRITE RANGE GATE START MIDDLE BYTE0011 READ/WRITE RANGE GATE START HIGH BYTE0100 RESERVED0101 READ/WRITE RANGE GATE END LOW BYTE0110 READ/WRITE RANGE GATE END MIDDLE BYTE0111 READ/WRITE RANGE GATE END HIGH BYTE1000 READ STATUS/WRITE MODE WORD 11001 READ STATUS/WRITE MODE WORD 21010 READ SCIENCE DATA TRANSFER COUNTER1011 READ STATUS/WRITE MODE WORD 31100 WRITE: SOFTWARE RESET1101 RESERVED1110 RESERVED1111 RESERVED


MODE/STATUS WORD 1BIT O: SPAREBIT[2:1] : RATE SELECT 00 1 HZ 01 6 HZ 10 8 HZ (POWER-ON DEFAULT) 11 10 HZBIT 3: REAL/SYNTHETIC DATA 0 REAL DATA(POWER-ON DEFAULT) 1 TEST DATABIT[6:4] : DATA BUILT-IN-TEST PATTERN 000 REAL DATA (POWER-ON DEFAULT) OTHERS TEST DATA PATTERNS DETAILS ON FOLLOWING PAGEBIT 7: BYTE/NIBBLE MODE 0 BYTE TRANSFERS (POWER-ON DEFAULT) 1 NIBBLE TRANSFERS, EACH NIBBLE REPEATED TWICE, ON DATA LINES, 7:4, 3:0


MODE/STATUS WORD 1 (cont'd)Built-in Test Control

BIT 3: REAL/SYNTHETIC DATA 0 REAL DATA(POWER-ON DEFAULT) 1 TEST DATA

BIT[6:4] : DATA BUILT-IN-TEST PATTERN 000 REAL DATA (POWER-ON DEFAULT) 001 00/FF for even/odd-numbered bytes 010 CHECKERBOARD (AA) 011 ~CHECKERBOARD (55) 100 COUNTER 101 ~COUNTER 110 FF/00 for even/odd-numbered bytes 110 REAL DATA


MODE/STATUS WORD 2

BIT O: CPU CYCLE SLIP (A K A. BABBLE BIT) 0 NO CYCLE SLIP (“GOOD”) 1 CYCLE SLIP (“BAD”)

BIT 1: 1PPS ENABLE 0 1PPS INHIBITED (POWER-ON DEFAULT) 1 1PPS ENABLED

BIT 2: SPAREBIT 3: SPAREBIT 4: SPAREBIT 5: CLOCK SELECTBIT 6: CLOCK SELECTBIT 7: CLOCK SELECT


MODE/STATUS WORD 2 (cont'd)

BIT [7:5] : CLOCK SELECT OPTIONS 000 => INTERNAL (40% DUTY CYCLE) X01 => OSC B X10 => OSC A 111 => INTERNAL (50% DUTY CYCLE)


MODE/STATUS WORD 3BIT O: CAL ENABLE 1BIT 1: CAL ENABLE 0BIT 2: CAL SELECT 1BIT 3: CAL SELECT 0BIT 4: CYCLE RESET TOF ENABLE 1BIT 5: CYCLE RESET TOF ENABLE 0BIT 6: SPAREBIT 7: SPARE

CAL ENABLE 1 CAL ENABLE 0

0 0 REAL DATA 0 1 REAL DATA 1 0 REAL DATA 1 1 TOF-A CALIBRATION DATA (TX TRAIL, LITTLE PULSES ONLY

CAL SELECT 1 CAL SELECT 0

0 0 0 NS CALIBRATION PULSES 0 1 200 NS CALIBRATION PULSES 1 0 400 NS CALIBRATION PULSES 1 1 200 NS CALIBRATION PULSES

THE TOF-A'S ARE ALWAYS RESETON APPLICATION OF: HARDWARE POWER-ON RESET SOFTWARE POWER-ON RESET

IF BOTH BITS 4 AND 5 ARE HIGH, THEN THE TOF-A'S WILL ALSO BE RESET EVERY CYCLE RESET, WHICH PULSES AFTER TIMEZERO AND BEFORE LASERFIRE.


MODE/STATUS WORD 3 (cont'd)

BIT [1:0]: CAL ENABLE 00 REAL DATA 01 REAL DATA 10 REAL DATA 11 CAL DATABIT [3:2]: CAL SELECT 00 01 10 11 BIT [5:4]: CYCLE RESET 00 01 10 11


Science Data Packet Definition (1)






Science Data Packet Definition (4)• Each timestamp value for all pulses (Start, Big and Little ) will

consist of three fields– Fine Time: Bits [9..0]

– Coarse Time:• Start Pulse: Bits [30..10]• Big Pulse: Bits [30..10]• Little Pulse: Bits [27..10]

– Miscellaneous (IDs, etc.): as specified for each type of Pulse

• Each bin is “worth”: – For Fine Time 200/512 ns

– for Coarse Time 200 ns

• To “reconstruct” actual time from Coarse and Fine Time fields, convert each value to “ns” according to the above, then subtract Fine Time from Coarse Time (see next page)



• Example: Start Pulse Data = “10000000000000100000000000001010”– black: Pulse ID

– red/bold: Coarse Time Field

– green/italic: Fine Time Field

• Actual timestamp is calculated as 128*200 - 10*(200/512) = 25596.09375(ns)


Miscellaneous

• Range gate start and stop values will also have power-on defaults. They are TBD.

• A software reset will force values to their power-on default state.

• RUPT pulse width is 6.4 µs.

• Following each write (except for software reset) the software will immediately read back the octet written and verify that it is correct.


1PPS Characteristics

• tW = TBD

• Phase relationship to the 5MHz at the RMU - TBD

• Single string

• If not present, the RMU will free run

• Bit 1 in MODE word 2 can disable the 1PPS signal.


PIN ASSIGNMENTS RMU CPU

RMU_DATA7 ?RMU_DATA6 ?RMU_DATA5 ?RMU_DATA4 ?RMU_DATA3 ?RMU_DATA2 ?RMU_DATA1 ?RMU_DATA0 ?RMU_PARITY ?RMU_SPARE0 ?RMU_SPARE1 ?RUPT ?

RMU CPUCPU_DATA7 ?CPU_DATA6 ?CPU_DATA5 ?CPU_DATA4 ?CPU_DATA3 ?CPU_DATA2 ?CPU_DATA1 ?CPU_DATA0 ?CPU_ADDR3 ?CPU_ADDR2 ?CPU_ADDR1 ?CPU_ADDR0 ?CPU_RD ?CPU_WR ?1PPS ?RMU_SPARE0 ?RMU_SPARE1 ?

GROUNDS, ETC.


CYCLE TIMING• CPU_RD and CPU_WR

– Both active high strobes– tWmin = 250 ns (both high and low)

• CPU_ADDR– tsu to trailing edge of strobe = 250 ns

– th from trailing edge of strobe = 250 ns

• CPU_DATA– tsu to trailing edge of CPU_WR = 250 ns

– th from trailing edge of CPU_WR = 250 ns

• RMU_DATA– tsu to trailing edge of CPU_RD = 100 ns

– th from trailing edge of CPU_RD = 100 ns

November 27, 2002 RMU-CPU Interface - Version 1.8 RMU - CPU Interface.

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