Novel Wire Density Driven Full-Chip Routing for CMP ...eda.ee.ntu.edu.tw/~yellowfish/iccad07/iccad07.pdf · as mask synthesis, writing, and inspection verification. Especially, these

Novel Wire Density Driven Full-Chip Routing forCMP Variation Control ∗

Huang-Yu Chen†, Szu-Jui Chou†, Sheng-Lung Wang§, and Yao-Wen Chang†‡†Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan

‡Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan§Synopsys, Inc, Taipei, Taiwan

Abstract— As nanometer technology advances, the post-CMPdielectric thickness variation control becomes crucial for man-ufacturing closure. To improve CMP quality, dummy featurefilling is typically performed by foundries after the routingstage. However, filling dummy features may greatly degradethe interconnect performance and lead to explosion of maskdata. It is thus desirable to consider wire-density uniformityduring routing to minimize the side effects from aggressive post-layout dummy filling. In this paper, we present a new full-chipgrid-based routing system considering wire density for reticleplanarization enhancement. To fully consider wire distribution,the router applies a novel two-pass, top-down planarity-drivenrouting framework, which employs a new density critical areaanalysis based on Voronoi diagrams and incorporates an inter-mediate stage of density-driven layer/track assignment based onincremental Delaunay triangulation. Experimental results showthat our methods can achieve more balanced wire distributionthan state-of-the-art works.

I. INTRODUCTION

As IC process geometries shrink to 65nm and below, one importantyield loss of interconnects comes from the chemical-mechanical pol-ishing (CMP) step in the copper metallization (Damascene) process.Because of the difference in hardness between copper and dielectricmaterials, the CMP planarizing process might generate topographyirregularities. A non-uniform feature density distribution on eachlayer causes CMP to over polish or under polish, generating metaldishing and dielectric erosion [22]. These thickness variations have tobe carefully controlled, since the variation in one interconnect level isprogressively transferred to subsequent levels during manufacturing,and finally the compounding variation can be significant on an upperlevel, which is often called the multi-layer accumulative effect [23].

Two key problems arise from the post-CMP thickness variation:(1) the layout surface fluctuates inside or outside the depth offocus (DOF) of the photolithography system, such that the exposedpatterns do not appear acceptably sharp and open/short defects mayeven occur, and (2) these irregular variations greatly change theelectrical characteristics of interconnects, especially for resistance andcapacitance, degrading the accuracy of timing analysis and worseningthe electromigration. As a result, in order to improve chip thicknessuniformity, TSMC recommends performing virtual CMP (VCMP)analysis to identify the metal and dielectric thickness variation hotspotbefore chip fabrication for 65nm manufacturing processes (see TSMCReference Flows 7.0) [24].

——————————————————————————————∗This work was supported in part by UMC and NSC of Taiwan under GrantNo’s. NSC 96-2752-E-002-008-PAE, NSC 96-2628-E-002-248-MY3, NSC96-2628-E-002-249-MY3, and NSC 96-2221-E-002-245.

In order to improve the CMP quality, modern foundries oftenimpose recommended layout density rules and fill dummy featuresinto layouts to restrict the variations on each layer. Dummy featuresmay either be connected to power/ground (tied fills) or left floating(floating fills) [19]. The tied fill has predictable but higher capaci-tance, while the floating fill has lower but unpredictable one due tothe floating nature. Traditionally, electrical impacts of dummy fillscan be negligible, and dummy features are inserted during the postrouting stage. Filling algorithms have been proposed to satisfy densitybounds and reduce the density variation [16], [25]. However, asreported in [26], these filled dummy features may incur troublesomeproblems at 65nm and successive technology nodes. The tied fillmay induce crosstalk for its high coupling capacitances to nearbyinterconnects and would place a heavy burden for P/G (power/ground)network. On the other hand, the floating capacitance of floatingfills is usually uncertain, and thus the induced coupling capacitancemight unpredictably harm the timing-optimized results in the previousdesign stages. Moreover, dummy fills also sheerly increase the datavolume of mask, lengthening the time of mask-making processes suchas mask synthesis, writing, and inspection verification. Especially,these filled features would significantly increase the input data inthe following time-consuming reticle enhancement techniques, suchas OPC (optical proximity correction) and PSM (phase shift mask).Therefore, much research focuses on impact-limited dummy featurefilling algorithms [7], [18].

In the nanometer technology, routing has become a decisive factorfor determining chip manufacturability, since it presides over mostof the layout geometries in the back-end design process. In orderto tackle these manufacturing challenges, routing techniques musthandle the increasing complexity. The routing approaches applyingthe bottom-up coarsening and top-down uncoarsening techniqueshave demonstrated the superior capability of handling large-scalerouting problems, such as the Λ-shaped multilevel [3], [4], [12],the V-shaped multilevel [5], and the two-pass bottom-up [6] routingframeworks.

Recently, routing considering wire distribution has attracted muchattention in the literature. The earlier studies for CMP processes haveindicated that the post-CMP dielectric thickness is highly correlatedto the layout pattern density, because during the polishing step,interlevel dielectric (ILD) removal rates are varied with the patterndensity [23]. Further, the layout pattern (consisting of wires anddummy features) density can be systematically determined by thewire density distribution, as reported in [9]. Therefore, managingwire density at the routing stage has great potential for alleviatingthe aggressive dummy feature filling induced problems.

Li et al. [20] presented the first routing system in the literatureaddressing the CMP induced variation. By setting the desired densityin the cost function of global routing, the routing results have

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more balanced interconnect distribution. Cho et al. [9] proposed apioneering work to consider CMP variation during global routing.They empirically developed a predictive CMP density model andshowed that the number of inserted dummy features can be predictedby the wire density. Therefore, they proposed a minimum-pin densityglobal routing algorithm to reduce the maximum wire density ineach global tile. However, both approaches only consider the wiredensity inside a routing tile. Since the topographic variation is a long-range effect, focusing density value inside each routing tile may incurlarger inter-tile density difference and result in more irregular post-CMP thickness. (See Fig. 1 (a).) Therefore, optimizing wire-densityuniformity inside a routing tile is obviously not a right metric anda common pitfall for CMP control. For better CMP control, it ismore desirable to minimize the global variation of wire density, i.e.,the density gradient. As the example shown in Fig. 1, if the densitylower and upper bounds are 20% and 80% respectively, then the threeadjacent routing tiles in Fig. 1 (b) all satisfy these rules. However,Fig. 1 (c) is a better choice for CMP control because it has theminimum wire-density gradient.

30% 30%

(a) (b) (c)

50% 40%40%

tile1 tile2 tile3

tile1 tile2

Post-CMP Thickness

50% 30%20%

tile1 tile2 tile3

Fig. 1. Density variation among neighboring subregions impacts topography.(a) Different wire distribution in a subregion exists even under the samedensity. Large density variation among neighboring subregions leads to post-CMP thickness irregularities. (b) Three adjacent routing tiles satisfy densityrules but result in unbalanced wire distribution. (c) A better result forminimizing the density gradient among tiles.

In this paper, we present a new full-chip grid-based routing system,named TTR (Two-pass Top-down grid-based Router), consideringwire-distribution uniformity for density variation minimization. Tofully consider wire distribution, the router is based on a novel two-pass, top-down planarization-driven routing framework. (See Fig. 2for an illustration.) Different from the aforementioned works, TTRhas the following distinguished features:

• A new routing framework of performing density prediction inthe prerouting stage, followed by planarization-aware globalrouting at the first uncoarsening stage, an intermediate stage ofdensity-driven layer/track assignment, and then detailed routingat the second uncoarsening stage.

• An efficient density critical area analysis (CAA) algorithmbased on Voronoi diagrams is performed off-line in the pre-routing stage, which considers both topological information ofpins and wire connection to complement the density analysis.As shown in Section IV, the Voronoi-diagram based CAAalgorithm leads to 3–5% faster overall routing process due toeasier density control for later detailed routing. Further, it cansubstantially improve the resulting wire-density uniformity.

• A planarization-aware global router is employed to consider thedensity lower and upper bounds while minimizing the densitygradient among global tiles.

• A layer assigner for panel-density minimization and a density-driven track assignment algorithm based on the incrementalDelaunay triangulation are performed before detailed routing

to preserve more flexibility for wire density arrangement.

Compared with the density-driven routing system [20], experimen-tal results show that TTR can achieve 43% reduction on the maximumnumber of nets crossing in tiles and obtain at least 35% smallerstandard deviations of wire distribution.

The rest of this paper is organized as follows. Section II describesthe routing model and the routing framework. Section III presents ourdensity-driven routing algorithms. Experimental results are reportedin Section IV, and conclusions are given in Section V.

II. ROUTING MODEL

We first explain the routing model. As illustrated in Fig. 2, Gk

corresponds to the routing graph of level k. Each level contains anumber of global cells (GCs), and the GCs belonging to differentlevels have different sizes. We denote GCk as the GC of level k.

The first top-down routing pass is for global routing, which startsuncoarsening from the coarsest level to the finest level (level 0). Ateach level k, our global router finds routing paths for the local nets(those nets that entirely sit inside GCk but not inside GCk−1). Afterall the global routings of level k are performed, we divide one GCk

into four smaller GCk−1 and at the same time perform resourceestimation for use at level k-1. Uncoarsening continues until the sizeof GCk at a level is below a threshold.

The second top-down routing pass is for detailed routing. As thefirst pass, it processes uncoarsening from the coarsest level to thefinest level. At each level, a detailed router is performed and rip-up/re-route procedures are applied for failed nets. The process continuesuntil we reach level 0 when the final routing solution is obtained.

III. DENSITY-DRIVEN ROUTING

To deal with wire density optimization, we develop a Two-passTop-down full-chip grid-based Routing system, named TTR (seeFig. 2). The rational for top-down routing lies in the fact that it tendsto route longer nets first level by level, which directly contributesto better wire planning since longer nets have greater impacts onplanarization than shorter ones. We detail the three distinguishedstages of TTR in the following subsections.

A. Density Critical Area Analysis (CAA)

In order to guide the following routing for making better deci-sions, TTR features a density critical area analysis in the preroutingstage that identifies the potential over-dense hotspots. Recently,Cho et al. [9] performed minimum-pin density routing to preventglobal-routing paths from crossing through over-dense areas. Thereason is that a path with higher pin density tends to pass throughmore wire dense areas, since the existence of a pin means thateventually there is at least one wire connecting to other pins. Thisapproach can help reduce the wire density in each global tile.However, there are some limitations. As the global routing instanceshown in Fig. 3 (a), although the routing path n1 passes fewer pins,it may exacerbate the over-dense areas in its adjacent regions. Incontrast, the routing path n2 contains more pins but results in a betterbalanced wire distribution. Moreover, the pin density is not directlyproportional to the wire density. As shown in Fig. 3 (b), the smallpin count in the global tile may still contribute to large wire density.

Therefore, it is necessary to consider both topological informationand wire connections of each pin to complement the density analysis.To remedy the deficiencies, we develop a new enhanced analysismodel based on Voronoi diagrams. The Voronoi diagram of a pointset P partitions the plane into regions, called Voronoi cells, each ofwhich is associated with a point of P . If a point in the plane is closer

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high

low

To-be-routed net Already-routed net

G0

G1

G2

Apply prerouting-guided planarization-aware global pattern routing for local nets and iteratively refine the solution.

First Pass StageUse segment-to-segment detailed maze routing to route short segments and reroute failed nets level by level.

Second Pass StageIdentify the potential density hot spots based on the pin distribution and wire connection to guide the following global routing.

Prerouting Stage

Critical Area Analysis

uncoarsening

uncoarsening

G0

G1

G2

uncoarsening

uncoarsening

Layer/Track Assignment

Perform density-driven layer/track assignment for long segments panel by panel.

Intermediate Stage

Fig. 2. The new two-pass, top-down routing framework.

SourceSource

(a) (b)

n1

n2

TargetTarget

Fig. 3. Limitations of minimum-pin density routing [9]. (a) Path n1 passesfewer pins but tends to exacerbate the over-dense areas in its adjacent regions,whereas path n2 passes more pins but leads to better balanced wire density.(b) Pin count cannot reflect the wire density in the global tile well.

to the point pt ∈ P than to any other point of P , then this point willbe in the interior of the Voronoi cell associated with pt. The boundarysegments of a Voronoi cell are called the Voronoi edges. A Voronoidiagram can efficiently compute the physical proximity and hasbeen well studied in computational geometry [13]. Papadopoulou andLee [21] used Voronoi diagrams of rectilinear polygons to computethe critical areas for short defects in a circuit layout.

The motivation for the Voronoi diagram approach lies in thefollowing observation.

Observation 1: Given the Voronoi diagram of points, the standarddeviation for the size of Voronoi cells strongly depends on thedistribution of these points.As illustrated in Fig. 4 (a), the Voronoi cells for points with non-uniform distribution have large variation in sizes; in contrast, asshown in Fig. 4 (b), for points with uniform distribution, the sizes ofVoronoi cells are almost the same.

Another observation can quantify the proximity relation to indicatewhether a point lies in the dense area.

(a) (b)

Fig. 4. Voronoi diagram for points with (a) non-uniform distribution and(b) uniform distribution.

p

(a) (b)

Fig. 5. Voronoi-diagram-based pin density analysis. (a) Proximity relationinduced by the Voronoi diagram reflects the dense quantity well. (b) Densitycost is measured by the topological proximity and the number of wireconnections.

Observation 2: For a point, the number of adjacent Voronoi cellswhich entirely sit within a specified distance from this point reflectsthe dense quantity of the region where this point lies.

As shown in Fig. 5 (a), the point in the dense area has more Voronoicells around it within a given circle with its center at this point.

Base on these observations, we specify a range r and associate

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each pin p with a density cost dp, which is defined as

dp = ανp + (1 − α)ωp, (1)

where νp is the number of Voronoi cells around p (excluding theVoronoi cell associated with p itself) which entirely sit inside thecircle with a center at p and radius r, ωp is the number of wireconnecting to p, and α, 0 ≤ α ≤ 1, is a user-defined parameter. Forthe example shown in Fig. 5 (b), there are three Voronoi cells aroundp which entirely sit inside the circle, and four wires are connectedto p. Therefore νp and ωp equal 3 and 4, respectively.

In the current implementation, we set the radius r as the averagedistance among pins of adjacent Voronoi cells. In this way, theexpected value for νp would be zero if p lies in a uniformly distributedregion; otherwise, νp would increase as a penalty to reflect the densityhotspot where p lies. Additionally, since two-pin nets practicallydominate the netlist in most designs, the expected value of ωp wouldequal one. Therefore, the ranges of νp and ωp in Eq. (1) are similarand can be reasonably combined together through the α parameter.

After all density costs of pins have been computed, we transformthese costs into the cost of global tiles. For each global tile t, we set itspredicted density cost d̃t = max{dp | p is inside t} in the preroutingstage. Then TTR feeds the pre-estimated density information to thefollowing routing stages. The density critical area analysis can beefficiently performed. We have the following theorem.

Theorem 1: The Voronoi-diagram based density CAA runs inO(|P | lg |P |) time, where |P | is the number of pins.

Note that the Voronoi-diagram based CAA algorithm is performedonly once, and its running time overhead is very small (about 3% ofthe total running time in our experiment). Further, it even leads to3–5% faster overall routing process due to easier density control forlater detailed routing, and it can substantially improve the resultingwire-density uniformity.

B. Planarization-Aware Global RoutingThe global routing plans tile-to-tile routing paths for all nets and

thereby is an important step to decide the wire distribution andmaintain a uniform metal density across the chip. As mentioned inthe introduction, both previous works [9], [20] consider only the wiredensity inside each global tile, which might incur larger inter-tiledensity gradient and thus more irregular post-CMP thickness. As aresult, for better CMP control, a global router has to consider thedensity variation (gradient) among global tiles in addition to wiredensity inside each tile.

In our TTR, the global routing performed in the first top-downuncoarsening pass is based on pattern routing [17]. Pattern routinguses an L-shaped (1-bend) or Z-shaped (2-bend) route to make theconnection, which gives the shortest path length between two pointswhile reducing the routing bends. Therefore, the obtained routingpath is the shortest, and we thus can focus on the objectives that wemost concern.

We define the planarization-aware cost Φt for each global tile t asfollows:

Φt = d̃t+

{κp, if dt ≥ Bu

β(2dt − 1) + (1 − β)(dt − dt)2, if Bl ≤ dt < Bu

κn, if dt < Bl

(2)where dt is the wire density of t, d̃t is the predicted hotspot costcalculated in the prerouting stage, dt is the average wire density oftiles adjacent to t, Bl and Bu are density lower and upper boundsspecified in foundry density rules respectively, and β, 0 ≤ 1, isa user-defined parameter. (Note that both the values of 2dt − 1

and (dt − dt)2

are between 0 and 1.) κp and κn are constants,where κp is a positive penalty that hinders the over denseness in theglobal tile, and κn is a negative reward that encourages paths to gothrough sparse tiles. The second equation simultaneously considerslocal density and minimizes the density difference among adjacentregions.

For more balanced wire distribution, the cost function Φp of theglobal routing path gp is defined as follows:

Φp = avg{Φt | tile t is on the path gp}, (3)

in which the average manner can represent the consciousness of evenwire distribution.

C. Density-Driven Layer/Track AssignmentRecently, Cong et al. [11] proposed the first wire-planning scheme

between global and detailed routers to reduce congestion. Battery-wala et al. [2] also suggested to add a track assignment stagebetween global and detailed routing to improve the routing quality.Ho et al. [14] developed a layer/track assignment heuristic in theintermediate stage for crosstalk optimization. Later in [15], Ho et al.further extended their track assigner for the wirelength reduction inX-architecture routing. However, wire density is not addressed inthese works.

1) Density-Driven Layer Assignment: In this paper, we pro-pose a new layer/track assignment algorithm for wire-density op-timization. To our best knowledge, this is the first work of wireplanning that addresses the wire-density optimization in the literature.

We handle long horizontal (vertical) segments which span morethan one complete global tile in a row (column) in the middlelayer/track assignment stage and delegate short segments to thedetailed router. The full row (or column) of a global tile array iscalled a row (column) panel. We will refer to a row panel as a panelthroughout the paper for brevity, unless specified otherwise.

In a panel, the local density of a column is defined as thetotal number of segments and obstacles at that column, and thepanel density is the maximum local density among all columns. Forexample, Fig. 6 (a) gives a row panel with 11 columns, c1 to c11.There are six segments s1 to s6 in the panel and two obstacles o1 ando2 in layers, and its panel density is equal to 4. We intend to evenlyarrange these segments to two horizontal layers (say layers 1 and 3)while minimizing the panel density at each layer. The density-drivenlayer assignment problem is defined as follows.

• The Density-driven Layer Assignment (DLA) Problem:Given a set L of layers, a set S of disjoint segments in a panel,and a set O of fixed obstacles in layers, assign each segmentof S to a layer, such that for each layer the local density isbalanced, and the panel density is minimized.

To solve the DLA problem, we partition the segments and obstaclesin each panel into |L| layer groups such that the main objective ofDLA is achieved.

First, we build the horizontal constraint graph HCG(V, E) for Sand O in the panel. Each vertex v ∈ V corresponds to a segmentor an obstacle, and two vertices vi and vj are connected by an edgee ∈ E if their spans overlap. The cost of edge e(vi, vj) is defined asthe maximal local density among the overlapping columns betweenvi and vj . With this weighting policy, if two vertices are connectedby an edge with a high cost, they should be separated into differentlayers. Fig. 6 (b) shows the HCG of the panel in Fig. 6 (a). Here,the obstacle o2 and segment s3 overlap in columns c3 and c4, andthe maximal local density of c3 and c4 is 3. So the cost of the edge(o2, s3) equals 3.

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(b)

s6

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Local density 1 1 2 1 1 1 1 1 2 2 0c1 c3 c4 c5 c6 c7 c8 c9 c10 c11c2Column

Segment

Layer 1 obstacle

1234

o2

s4s5

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Local density 0 1 1 1 1 1 2 1 2 2 2c1 c3 c4 c5 c6 c7 c8 c9 c10 c11c2Column

Segment

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1234

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o1

s3

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s6

Local density 1 2 3 2 2 2 3 2 4 4 2c1 c3 c4 c5 c6 c7 c8 c9 c10 c11c2Column

(d)

Fig. 6. A density-driven layer assignment example. (a) A row panel Aconsists of six segments and two obstacles. We intend to evenly assignthese segments to two horizontal layers (layers 1 and 3). (b) The horizontalconstraint graph. (c) The layer-partitioning result for two layer groups byapplying the maximum spanning tree and k-coloring algorithms. (d) The finallayer assignment result by applying a minimum-impact repair procedure toexchange the layers of s6 and o1. (e) and (f) The final local densities of layers1 and 3, respectively.

Consequently, we can formulate the DLA problem as a max-cut, k-coloring problem (MCP) [10] on the HCG graph, where k equals |L|.In this way, we can guarantee that the partitioning result can evenlydistribute the segments of the maximal local density to different layergroups. However, the MCP is NP-complete [10]. Thus, we resort toa simple, yet efficient heuristic by constructing a maximum spanningtree on the HCG and applying a k-coloring algorithm on this tree.Note that the k-coloring algorithm on a tree can be solved in lineartime. Fig. 6 (c) shows a layer-partitioning result of Fig. 6 (a), wheres1, s2, s3 and s6 are partitioned as one layer group, and o2, s4, s5 ando1 are partitioned as another one. Note that the objects o1, s3, s5, ands6 at columns c9 and c10 that induce the maximum local density areseparated into two different layer groups.

At the last step, since obstacles are already in fixed layers, weapplied a minimum-impact repair procedure for obstacles. If anobstacle is not placed in the right layer (e.g., o1 in Fig. 6 (c)), thelayer of a vertex vo of an obstacle is exchanged with that of a vertex

vs of a segment such that the edge cost (vo, vs) is the maximumamong the edges connected with vo in the maximum spanning tree.If there does not exist such a vertex vs, we can just assign vo to thecorrect layer since there is no segment there (otherwise, there mustbe an edge connected with vo). The final assignment result after therepair procedure for exchanging the layer of vertex o1 with that ofvertex s6 is shown in Fig. 6 (d). As a result, the final assignment hasa very balanced density distribution that the average local density oflayer 1 is 1.18 and that of layer 3 is 1.27 while the panel densities inboth layers equal 2. See Figs. 6 (e) and (f) for the resulting segmentassignments for layers 1 and 3, respectively.

Note that for practical concern, in addition to the objectives ofDLA, a good/practical layer assigner shall also assign layers withmore segments of the same nets closer to each other to minimizethe stacked-via usage. We can model the connectivity among layersas a connection graph C(V, E) whose nodes represent layers andedges denote the corresponding connectivity. Then, the problem canbe solved by first computing the Maximum-Weighted HamiltonianPath (MWHP) on C(V, E) and then assigning layers with the largestconnectivity closer to each other. Since the MWHP problem is NP-hard, we apply a greedy algorithm similar to Kruskal’s minimumspanning tree algorithm to handle the MWHP problem. We first sortedges by their weights, and then add edges in non-increasing weightorder if they form a path.

2) Density-Driven Track Assignment: After the layer assign-ment, we intend to uniformly spread the segments in each layerof panels and balance the segment distribution among neighboringpanels. For convenience, we hereafter refer to a layer of a panelas a panel since the layer assignment has already been performed.Let T be the set of tracks inside a panel. Each track τ ∈ T can berepresented by the set of its constituent contiguous intervals. Denotingthese intervals by xi. A segment s ∈ S is said to be assignable toτ ∈ T , τ ≡ ⊎

xi, if either xi is a free interval or is an intervaloccupied by a segment of the same net. The density-driven trackassignment problem is defined as follows:

• The Density-driven Track Assignment (DTA) Problem:Given a panel A and its two neighboring panels Au and Ab, aset of tracks T ∈ A, a set of segments S ∈ A, and a set of fixedobstacles O ∈ A, for a given cost function Ψ : S × T → R

which represents the density cost of assigning a segment to atrack, find a feasible assignment of S to T that minimizes Ψ.

To solve this problem, we propose an Incremental Delaunay-triangulation-based Track Assignment (IDTA) algorithm. In Obser-vation 1, we have discovered the relation between density uniformityand the Voronoi diagram. Instead of using the Voronoi diagram, wecan leverage the good properties of its dual graph, called DelaunayTriangulation (DT), to evaluate the segment distribution. The DT fora point set is a triangulation that minimizes the standard deviationsof angles among all triangles, and the circumscribed circle of everytriangle will not contain any other point in its interior [13]. Similar tothe Voronoi diagram, the standard deviation for the size of triangles inDT can reflect the distribution of these points. Thus, we can representeach segment by three points, two end points and one center point,and analyze the corresponding DT of these points.

Before performing the IDTA algorithm, we first model the distri-bution of segments and obstacles in each neighboring panel into anartificial segment lying on the boundary of A. In order to reflect thedistribution of objects in a neighboring panel An of A, we set thelength of an artificial segment as the average occupied length pertrack in An, and the center of this artificial segment is determinedby the center of gravity of all segments and obstacles in An.

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Algorithm: IDTAInput: A /* The panel */

S /* A set of segments */O /* A set of fixed obstacles */su, sb /* The artificial segments */

Output: T /* The assignment configuration */1 for each segment si ∈ S2 Compute the flexibility of si, ξ(si);3 T ← ∅;4 Construct an initial point set P based on O ∪ {su, sb};5 Construct an initial DT of P ;6 while S is not empty7 Choose the segment sj with the smallest flexibility;8 Determine track(sj) such that the maximum area difference

among the introduced triangles is minimum;9 T ← T ∪ {sj , track(sj)};10 Add the points introduced by sj into P ;11 Update DT incrementally;12 S ← S − {sj};13 for each sk ∈ S overlapping sj

14 Update ξ(sk);15 Return T ;

Fig. 7. The Incremental Delaunay-triangulation-based Track Assignment(IDTA) algorithm.

Fig. 7 shows the IDTA algorithm. Without loss of generality, wediscuss the track assignment at a row panel, and the case for a columnpanel is similar. For the track assignment problem, the x-coordinatesof segments are fixed (i.e., the segments in row panels can only movein the vertical direction), so we can focus on the y direction. At thebeginning, we define the flexibility of a segment si as

ξ(si) = ti +1

�i,

where ti is the number of assignable tracks of si, and �i is the lengthof si. Since the x-coordinate of si is fixed, ti can easily be computed.If the flexibility of si is smaller, which means that si might havelonger length or less space to insert, then si should be assigned first.

After the flexibility computation, we construct an initial DT thatincludes only the obstacles and two artificial segments. Each segmentor obstacle is represented as three points, its left-end, center, andright-end points. Fig. 8 (a) shows the initial DT. The constructionof DT takes O(|P | lg |P |) time, where |P | is the number of points.Note that a DT can be updated incrementally; if a new point is addedinto an existing DT, we only need to update the triangles introducedby this new point. Therefore, the process can be performed veryefficiently. The update will be frequently used in the following steps.

Lemma 1: Adding a new point into an existing Delaunay triangu-lation of |P | points takes O(lg |P |) time.

Segments are assigned sequentially in the non-decreasing orderof their flexibilities. Suppose segment sj has the smallest flexibilityamong all unassigned segments, then we assign sj to a proper track.In order to minimize the area difference among all triangles, the trackwhich results in a DT with smaller area difference is preferred.

After assigning sj to the track track(sj), we need to updatethe DT and the flexibility of segments. Since we can incrementallyupdate the DT, only the new triangles introduced by sj need to bere-generated. Only the segments that overlap sj and are originallyassignable to track(sj) need to update their values of flexibility. Forthose segments, the new flexibility would be the original flexibilityminus 1. The number of segments overlapping with sj is boundedby �j × tj , which is bounded by the constant size of the panel;here, �j is a value, and tj is bounded by the number of tracks in apanel, which is predetermined before the routing and is around 10–

20 in our implementation. Therefore, the total time complexity ofupdating DT and the flexibilities of segments is O(lg |S|), and wehave the following theorem for the overall time complexity of theIDTA algorithm.

Theorem 2: The IDTA algorithm runs in O(|S| lg |S|) time, where|S| is the number of segments in a panel.

Fig. 8 shows a track assignment example. Fig. 8 (a) is the initialDT including only obstacles and artificial segments, and Figs. 8 (b),(c), (d) are the assignment results of s3, s2, and s1, respectively.The flexibilities of unassigned segments are listed on the right sideof the figures. Note that each time when a segment is assigned, theflexibilities of unassigned segments are incrementally updated.

After the track assignment, the actual track position of a segmentis known. Thus, we can perform classical segment-to-segment mazerouting in the detailed routing stage to connect shorter nets whichspan at most two routing tiles, and the whole routing process isfinished.

s2

1234

(a)

o1

1234

(b)

o1

s3

s2

1234

(c)

o1

s3

s2

1234

(d)

o1

s3s1

sb

su

sb

su

sb

su

sb

su

(s3) = 3.125

(s2) = 5

(s1) = 4.5

(s2) = 4

(s1) = 4.5

(s1) = 4.5

s3

s1

Segment

Artificial segment

Layer 1 obstacle

Fig. 8. A density-driven track assignment example. (a) The initial Delaunaytriangulation. (b) Track assignment for segment s3. (c) Track assignment forsegment s2. (d) Track assignment for segment s1.

IV. EXPERIMENTAL RESULTS

The TTR routing system was implemented in the C++ program-ming language on a 1.2 GHz SUN Blade-2000 workstation with 8GB memory. We used the LEDA packages to compute the Voronoidiagrams and Delaunay triangulation. We conducted the experimentsbased on the eleven MCNC routing benchmarks [3] (which contain

836

3–4 routing layers with up to 28K connections) and five real industrialFaraday benchmarks introduced in [1]. (See Table I for the statisticsof the Faraday benchmarks.) In our implementation, the parameterα in Eq. (1) was set to 0.5, and the parameters β, κp, κn, Bl, andBu in Eq. (2) for all benchmarks were given as 0.5, 2, -2, 10%, and40%, respectively.

TABLE I

THE FARADAY BENCHMARK CIRCUITS.

Circuit Size (µm2) #Layers #Nets #Connections #PinsDMA 408.4×408.4 6 13256 36162 73982DSP1 706×706 6 28447 63495 144872DSP2 642.8×642.8 6 28431 36686 144703RISC1 1003.6×1003.6 6 34034 95106 196677RISC2 959.6×959.6 6 34034 95099 196670

We compared the proposed two-pass, top-down routing frameworkof TTR with the grid-based full-chip multilevel router consideringbalanced routing density in [20] (named MROR). The MROR pro-gram was provided by the authors of [20] and was run on the samemachine. For fair comparison, TTR used the same setting for the sizeof routing tiles in all benchmarks as MROR. Note that as reportedin [20], MROR achieves better solutions than the previous work [3],and thus we shall directly compare TTR with MROR.

In addition, we also examined the effects of the Voronoi-diagram-based density critical area analysis (CAA) in TTR by comparingwith the minimum-pin density routing algorithm presented in [9].Note that in [9], the authors applied their algorithm in an ILP-based global router called BoxRouter [8]. Therefore, to focus on thecomparison of the two CAA algorithms, we integrated the minimum-pin density routing algorithm into TTR. In other words, we removedthe prerouting of TTR and replaced the cost function of the globalrouter in Eq. (2) by the minimum-pin density routing algorithm.

Tables II and III show the comparison results on the MCNCand Faraday benchmarks, respectively. Note that since the MRORprogram can only handle the designs with all pins lying in layer 1(as in the MCNC benchmarks), we did not conduct the experimentson the Faraday benchmarks (where pins are distributed betweenlayers 1 and 3) for MROR. In the tables, we used the samemetrics as those in [20] which can evaluate the uniformity of wiredistribution in the routing stage, where “Rout.” stands for routability,“#Netmax” denotes the maximum number of nets crossing a level-0tile, “#Netavg h” represents the average number of nets horizontallycrossing a tile and “σh” gives its standard deviation, and “#Netavg v”gives the average number of nets vertically crossing a tile and “σv”gives its standard deviation. For the TTR routing systems, “#LG”denotes the total number of layer groups for the layer assignment,and “#Seg” shows the total number of segments.

As shown in the tables, all routers obtain 100% routing com-pletion on the MCNC benchmarks, and both routers applying thenew framework of TTR outperform the multilevel router MRORin wire uniformity. Compared with MROR, TTR incorporated withthe minimum-pin density global routing algorithm reduces #Netmax,#Netavg v , and #Netavg h by 32%, 28%, 26% respectively, andTTR with Voronoi-diagram-based CAA can achieve 43%, 34%,36% reductions on #Netmax, #Netavg v , and #Netavg h respectively.Moreover, the routers using the TTR framework also result in atleast 35% smaller standard deviations of wire distribution in bothdirections (which implies better density smoothness) than MROR.The results on the Faraday benchmarks also show that the globalrouting guided by the Voronoi-diagram-based CAA can achieve betterwire uniformity than the minimum-pin density global router. Fig. 9

shows the routing layouts of “S13207” and the corresponding wire-crossing maps in the vertical direction for the aforementioned threerouters, and Fig. 10 shows the results for the Faraday circuit “RISC1”and the horizontal wire-crossing maps. The experimental resultsconsistently show the superior effectiveness and efficiency of ourrouting algorithm and framework in wire density control.

Vertical Wire Crossing

(d)(c)

30

25

20

15

10

5

0

Vertical Wire Crossing

(f)(e)

30

25

20

15

10

5

0

Vertical Wire Crossing

(b)(a)

30

25

20

15

10

5

0

Fig. 9. The routing result and the vertical wire-crossing map in tiles for“S13207.” (The red, green, and blue lines represent metals 1, 2, and 3,respectively) (a) and (b) The routing layout and its vertical wire crossingof MROR [20]. The maximum vertical wire crossing is 27. (c) and (d) Therouting layout and its vertical wire crossing obtained from the minimum-pindensity global routing [9] + TTR’s routing framework. The maximum verticalwire crossing is 13. (e) and (f) The routing layout and its vertical wire crossingof TTR (Ours). The maximum vertical wire crossing is only 11.

V. CONCLUSIONS

We have presented a new two-pass, top-down full-chip grid-basedrouter, named TTR, considering wire density for CMP variationcontrol. TTR features a new Voronoi-diagram-based density criticalarea analyzer, a planarization-aware global router, a layer assignerfor panel-density minimization, and an effective track assigner basedon the incremental Delaunay triangulation. Experimental results haveshown the effectiveness and efficiency of the proposed methods.

REFERENCES

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[2] S. H. Batterywala, N. Shenoy, W. Nicholls, and H. Zhou, “Track Assignment:A Desirable Intermediate Step Between Global Routing and Detailed Routing,”Proc. ICCAD, pp. 59–66, Nov. 2002.

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837

TABLE II

COMPARISON FOR THE WIRE DENSITY CONTROL ON THE MCNC BENCHMARKS.

CPU CPU CPU(sec) (sec) (sec)

Mcc1 45 9.9 11.3 7.6 7.3 77.4 124 2600 41 10.3 11.1 5.1 7.6 36.1 124 2639 30 10.3 11.0 5.9 6.4 33.4Mcc2 96 18.7 20.9 17.3 18.5 2714.9 256 15814 119 20.6 22.2 14.4 19.6 798.0 256 16644 87 20.5 22.2 13.9 16.0 645.0Struct 7 1.4 1.4 1.1 1.6 61.4 193 2128 5 1.2 0.8 0.9 0.8 66.8 167 2124 6 1.1 0.8 1.1 1.0 58.2

Primary1 15 0.7 0.6 1.2 1.8 69.1 328 2423 12 0.8 0.7 0.9 1.4 27.0 215 2207 6 0.7 0.3 0.9 0.8 24.3Primary2 25 2.1 1.9 1.6 4.5 322.2 387 8338 22 2.5 1.9 1.3 2.8 144.0 303 7693 8 1.8 0.9 1.3 1.6 131.0

S5378 15 4.4 3.5 3.4 2.1 4.5 87 1091 8 2.5 2.4 1.6 1.5 8.1 91 1193 9 2.5 2.4 1.8 1.5 8.2S9234 14 4.0 2.6 3.2 1.6 3.2 95 912 7 1.7 1.6 1.4 1.3 5.2 95 1003 9 1.7 1.6 1.6 1.2 5.4

S13207 27 9.3 5.9 5.2 2.8 15.8 97 1727 13 3.4 3.0 2.1 1.8 24.8 97 1821 11 3.3 3.0 2.3 1.7 24.2S15850 26 10.3 7.4 5.4 2.9 23.8 97 1834 12 4.0 3.8 2.3 1.9 34.2 97 1915 13 3.9 3.8 2.4 1.9 33.5S38417 23 7.3 4.3 4.4 2.2 54.2 188 5043 10 3.0 2.4 1.8 1.4 62.5 188 5462 11 2.9 2.4 2.0 1.4 62.4S38584 29 9.1 5.8 5.4 2.9 137.7 189 6004 16 3.3 3.1 2.3 1.6 112.0 189 6328 15 3.3 3.1 2.3 1.6 112.0Comp. 1.00 1.00 1.00 1.00 1.00 1.00 - - 0.68 0.72 0.74 0.59 0.65 1.01 - - 0.57 0.66 0.64 0.64 0.65 0.98

h

TTR (Ours)

#LG #Seg #Netmax #Netavg_v #Netavg_h vv h

MROR [20]

#Netmax #Netavg_v #Netavg_h v #Netavg_v

Minimum pin density global routing [9] + TTR's routing frameworkCircuit #Netavg_hh #Netmax#LG #Seg

TABLE III

COMPARISON FOR THE WIRE DENSITY CONTROL ON THE INDUSTRIAL FARADAY BENCHMARKS.

CPU CPU(sec) (sec)

DMA 99.19% 272 5168 14 3.14 2.77 1.70 1.77 48.8 99.29% 272 5325 10 3.08 2.70 1.75 1.64 47.0DSP1 99.11% 264 4241 11 2.91 2.50 1.95 1.89 124.2 99.18% 263 4529 10 2.85 2.44 2.24 1.95 117.3DSP2 99.10% 268 4676 14 2.78 2.78 1.71 1.92 87.2 99.06% 268 4892 10 2.72 2.70 1.90 1.91 82.3RISC1 99.16% 265 5864 21 3.63 3.79 2.95 3.78 355.3 99.16% 265 6226 17 3.59 3.73 3.08 3.29 333.4RISC2 99.23% 260 6141 21 3.64 3.70 2.55 3.08 297.4 99.19% 260 6533 13 3.59 3.62 2.77 2.89 280.0Comp. 99.16% - - 1.00 1.00 1.00 1.00 1.00 1.00 99.18% - - 0.75 0.98 0.98 1.08 0.95 0.95

Circuit #Netavg_h#Netmax#LG #SegRout.

Minimum pin density global routing [9] + TTR's routing framework

v h#Netavg_v

TTR (Ours)

h#LG #Seg #Netmax #Netavg_v #Netavg_h vRout.

Horizontal Wire Crossing

(b)(a)

Horizontal Wire Crossing

(d)(c)

Fig. 10. The routing result and the horizontal wire-crossing map in tiles for“RISC1.” (The red, green, blue, magenta, coffee, and aqua blue lines representmetals 1, 2, 3, 4, 5, and 6 respectively, and the white space is allocated by7 macros.) (a) and (b) The routing layout and its horizontal wire crossingobtained from the minimum-pin density global routing [9] + TTR’s routingframework. The maximum horizontal wire crossing is 21. (c) and (d) Therouting layout and its horizontal wire crossing of TTR (Ours). The maximumhorizontal wire crossing is only 17.

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