Novel Techniques for Fully Integrated RF CMOS Phase-Locked Loop Frequency Synthesizer Boon Chirn Chye School of Electrical & Electronic Engineering A thesis submitted to the Nanyang Technological University in fulfillment of the requirement for the degree of Doctor Philosophy of Engineering 2004
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Novel Techniques for Fully Integrated RF CMOS Phase-Locked Loop
Frequency Synthesizer
Boon Chirn Chye
School of Electrical & Electronic Engineering
A thesis submitted to the Nanyang Technological University
in fulfillment of the requirement for the degree of Doctor Philosophy of Engineering
2004
ii
STATEMENT OF ORIGINALITY
I hereby certify the content of this thesis is the result of work done by me and
has not been submitted for higher degree to any other University or Institution.
Date Boon Chirn Chye
iii
ABSTRACT
In this thesis, the design of a fully integrated RF CMOS phase-locked loop is
explored. The goal of this research is to provide solutions for the problems associated
with the VCO and the frequency divider in the RF CMOS phase-locked loop.
There are five important contributions in this research. Firstly, a method for
improving the phase noise performance of a CMOS quadrature LC oscillator through
parasitic-compensation is introduced. Due to the parasitic resistance in the inductor,
the LC oscillator suffers from low Q value, which degrades its phase noise
performance. In this design, through the parasitic-compensation method, the LC
oscillator will be made to oscillate at the frequency where the effective impedance of
the parallel LC resonator is at the peak. This will increase the Q value of the LC
resonator, which improves the phase noise performance of the circuit. A fabricated
2.63 GHz quadrature CMOS LC oscillator with a phase noise of –112.3 dBc/Hz at
600 kHz offset is demonstrated, consuming a power of 7.5mW using an on-chip spiral
inductor.
Secondly, based on the understanding of the flicker noise generation in the
MOSFET, a novel method for improving the phase noise performance of a CMOS LC
oscillator is presented. In [8],[9], it has been suggested that the 1/f noise can be
reduced through a switched gate, and the flicker noise generated is inversely
proportional to the gate switching frequency. The novel tail transistor VCO topology
is compared to the two popular VCO topologies, one with a fixed biasing tail
transistor [10],[11], and the other without a tail transistor [12],[13]. A simulated phase
noise of -127.6 dBc/Hz at 600 kHz offset for an oscillation frequency of 1.88 GHz
was achieved with a tank quality factor of 9. To date, few VCOs have met the
iv
specifications of the WCDMA and CDMA2000 standards due to the stringent phase
noise requirement. This is especially true for fully integrated VCOs due to the low
inductor Q. An example of a VCO that meets the system specifications of the
WCDMA/CDMA2000 has been achieved through this novel topology.
Thirdly, a millimeter wave CMOS LC VCO implementing a push-pull buffer
that can double the input frequency was introduced. The oscillation frequency of the
VCO is 102 GHz, which is about twice the tf of the SiGe CMOS transistors of 52
GHz. Thus, fully integrated VCO using SiGe can now be realized for applications
beyond 100 GHz. A VCO has been fully integrated in the 0.25µm SiGe MOSFETs
technology. The VCO has an oscillation frequency of 102 GHz with a tuning range of
3.4 GHz. In this tuning range, the phase noise is –106 dBc/Hz to –107.7 dBc/Hz at 1
MHz offset frequency. Besides being the VCO with the highest frequency reported to
date, this novel VCO also has the best figure of merit (FOM) of 192.9 dB.
Fourthly, a new spur reduction fractional-N frequency divider with a
frequency range 3.5 times larger than that of a conventional fractional-N divider is
presented in this paper. A 1.2 GHz quadrature VCO was designed as the input source
of the frequency divider. The circuit was fabricated using the CMOS 0.25µm
technology, the power consumption of the frequency divider and the quadrature VCO
are 3mW and 6mW at 2V supply, respectively.
Finally, a technique that can fully suppress the fractional spur generated by the
fractional-N frequency divider is proposed. In addition, this provides a simple
solution to spur reduction, which requires only two additional 2-to-1 multiplexers to
the conventional fractional-N frequency divider.
v
ACKNOWLEDGMENTS
I am deeply indebted to my supervisor, Professor Do Manh Anh for giving me
the opportunity to work in this project under his guidance. I would also like to thank
him for his support, patience and time throughout the course of this work. I am
grateful to Associate Professor Yeo Kiat Seng and Associate Professor Ma Jian Guo
for all their help, support and encouragement.
My gratitude is extended to my family for their encouragement and support.
I would like to thank my friends Zhang Xiaoling, Zhao Ruiyan, Alper Cabuk,
Jia Lin, Fan Xianping, Liu Rong, Wong Hon Hin, Sin Tze Yee, Lee Wing Foon,
Qasem Ramadan and Ng Wil Lie for their friendship and support.
I thank all the technical staffs, Miss Hau Wai Ping and Ms Quek-Gan Siew
Kim in IC Design I Laboratory, Mr. Richard Tsoi, Miss Guee Geok Lian and Mrs.
Leong Min Lin in IC Design II Laboratory, for their help.
Fig. 2-1: Block diagram of a PLL..................................................................................9 Fig. 2-2: State variable diagram of a PLL. .................................................................10 Fig. 2-3: Linear time-invariant phase-model of the PLL. ...........................................11 Fig. 2-4: EXOR gate phase detector............................................................................17 Fig. 2-5: The operation of an EXOR gate phase detector. ..........................................18 Fig. 2-6: The transfer characteristics of an EXOR gate phase detector. ....................18 Fig. 2-7: Flip-flop phase detector................................................................................19 Fig. 2-8: Operation of a flip-flop phase detector. .......................................................19 Fig. 2-9: Transfer characteristics of a flip-flop phase detector. .................................20 Fig. 2-10: Phase frequency detector............................................................................21 Fig. 2-11: Operation of the phase frequency detector.................................................21 Fig. 2-12: Transfer characteristics of the phase frequency detector...........................22 Fig. 2-13: Phase frequency detector without dead zone..............................................24 Fig. 2-14: A 3rd order, type-2 charge pump PLL filter. ...............................................25 Fig. 2-15: Bode plot of the open loop response for a 3rd order, type-2 charge pump PLL filter......................................................................................................................27 Fig. 2-16: A 4th order, type-2 charge pump PLL filter. ...............................................30 Fig. 2-17: Bode plot of the open loop response for a 4th order, type-2 charge pump PLL...............................................................................................................................31 Fig. 2-18: Loop filter gain and PLL open loop gain for 3rd and 4th order charge pump PLLs. ............................................................................................................................32 Fig. 2-19: Loop filter phase and PLL open loop phase for 3rd and 4th order charge pump PLLs ...................................................................................................................33 Fig. 2-20: Output spectrum of (a) ideal oscillator; (b) actual oscillator. ...................35 Fig. 2-21: Single sideband and double sideband phase noise.....................................36 Fig. 2-22: Phase noise plot of the noise sources in a PLL. .........................................38 Fig. 2-23: Closed loop transfer function of the VCO noise.........................................41 Fig. 2-24: Effect of the PLL on VCO noise..................................................................42 Fig. 2-25: Phase noise plots (a) low Q; (b) high Q. ....................................................44 Fig. 2-26: Closed loop transfer function of the reference noise..................................45 Fig. 2-27: Effect of the PLL on the reference noise.....................................................45 Fig. 2-28: Effect of the PLL on the divider noise. .......................................................47 Fig. 2-29: Effect of the PLL on the divider noise and the reference noise. .................48 Fig. 2-30: Contribution of the loop filter noise to the total output noise. ...................49 Fig. 2-31: Phase noise contributions in a PLL............................................................50 Fig. 2-32: Phase noise contribution in a PLL with N = 100 and loop bandwidth of 3.3 kHz. ..............................................................................................................................52 Fig. 2-33: Phase noise contribution in a PLL with N = 100 and loop bandwidth of 8.5 kHz. ..............................................................................................................................52 Fig. 3-1: Feedback diagram of an oscillator...............................................................54 Fig. 3-2: Three-stage ring oscillator. ..........................................................................56 Fig. 3-3: Simplified parallel LC resonator. .................................................................58 Fig. 3-4: The cross-coupled LC VCO. .........................................................................59 Fig. 3-5: A more realistic model for the resonator tank..............................................61 Fig. 3-6: The quadrature LC VCO. .............................................................................65 Fig. 3-7: The complementary cross-coupled LC VCO. ...............................................67 Fig. 3-8: A simplified physical model of a spiral inductor. .........................................68
xi
Fig. 3-9: (a) The structure of a spiral inductor; (b) The die photo of a spiral inductor.......................................................................................................................................69 Fig. 3-10: Plot of the equivalent series resistance R versus the inductance L. ...........71 Fig. 3-11: Plot of the quality factor Q versus the inductance L. .................................72 Fig. 3-12: C-V characteristics of the A-MOS varactor. ..............................................73 Fig. 3-13: C-V characteristics of the diode varactor. .................................................74 Fig. 3-14: Phase noise performance of the A-MOS varactor VCO over the tuning range. ...........................................................................................................................76 Fig. 3-15: Phase noise performance of the diode varactor VCO over the tuning range.......................................................................................................................................76 Fig. 3-16: Tank model of the complementary LC VCO. ..............................................77 Fig. 4-1: Parallel LC resonator...................................................................................81 Fig. 4-2: The resonant characteristic of a parallel LC resonator...............................82 Fig. 4-3: Block diagram of the coupled VCO. .............................................................85 Fig. 4-4: Parasitic-compensated LC oscillator. ..........................................................87 Fig. 4.5: Behavioral Model of a two-stage LC oscillator [73]....................................89 Fig. 4-6: Microphotograph of the quadrature LC oscillator.......................................91 Fig. 4-7: Phase noise performance versus Vset...........................................................92 Fig. 4-8: Phase noise performance over the tuning range from 2.59 GHz to 3.13 GHz.......................................................................................................................................92 Fig. 4-9: Power spectrum of the oscillator at ωo’. ......................................................93 Fig. 5-1: VCO with without tail transistor topology. ..................................................98 Fig. 5-2: VCO with fixed biasing tail transistor topology. ..........................................99 Fig. 5-3: Test setup for flicker noise..........................................................................101 Fig. 5-4: Simulated baseband flicker noise for fixed and switched biasing conditions.....................................................................................................................................102 Fig. 5-5: Simulated second harmonic flicker noise for fixed and switched biasing conditions...................................................................................................................103 Fig. 5-6: Memory reduced tail transistor VCO. ........................................................104 Fig. 5-7: Comparison of phase noise performance for the three VCOs....................108 Fig. 5-8: WCDMA/CDMA2000 VCO using the novel circuitry. ...............................110 Fig. 6-1: Schematic of the 102 GHz VCO..................................................................113 Fig. 6-2: Phase noise performance of the VCO.........................................................115 Fig. 6-3: The frequency spectrums of the harmonic components of the 102 GHz VCO.....................................................................................................................................115 Fig. 6-4: ft and fmax plot for Veff = VGS-VT =0.2 V. ....................................................116 Fig. 6-5: Frequency response of the A-MOS varactor. ............................................118 Fig. 6-6: Frequency response of the stripline inductor. ...........................................119 Fig. 6-7: Layout of the 102 GHz VCO......................................................................119 Fig. 7-1: Dual-modulus prescaler with swallow counter. .........................................124 Fig. 7-2: Block diagram of a fractional-N frequency synthesizer. ............................127 Fig. 7-3: Phase error generated in the process to achieve a divide-by-(2 + 1/2) operation. ...................................................................................................................127 Fig. 7-4: Fractional-N divider with phase estimation by DAC. ................................129 Fig. 7-5: Phase error correction by DAC..................................................................129 Fig. 7-6: Fractional-N divider with random jittering................................................131 Fig. 7-7: Fractional-N divider with ∆-Σ modulation.................................................132 Fig. 7-8: Fractional-N divider with phase interpolation technique. .........................134 Fig. 7-9: Fractional-N divider with pulse generation technique...............................135 Fig. 7-10: Yuan-Svensson D-FF. ...............................................................................138
xii
Fig. 7-11: The four possible transients of Yuan-Svensson D-FF in toggle configuration..............................................................................................................138 Fig. 7-12: Huang-Rogenmoser D-FF. .......................................................................139 Fig. 7-13: Frequency divider for divide-by-8 operation. ..........................................141 Fig. 7-14: Analogy between (a) dynamic TSPC CMOS toggle-flip-flop; and (b) three-inverter ring oscillator.........................................................................142 Fig. 7-15: High frequency model of a MOS transistor..............................................143 Fig. 7-16: Flow diagram of the flip-flop design in frequency divider. ......................147 Fig. 7-17: Microphotograph of the frequency divider for a divide-by-8 operation. .156 Fig. 7-18: Experimental results of the frequency divider for a divide-by-8 operation (a) 1 GHz input signal; (b) 125 MHz output signal...................................................157 Fig. 8-1: Effect of unequal instantaneous frequencies. .............................................161 Fig. 8-2: Fractional-N frequency divider with a divide-by-(N + 1/4) operation. .....162 Fig. 8-3: Effect of the implementation of a divide-by-(N + 1/4) operation. ..............163 Fig. 8-4: Block diagram of the simulation setup of a PLL frequency synthesizer using conventional frequency divider and novel frequency divider. ...................................164 Fig. 8-5: Simulation Results of (a) the conventional frequency divider; (b) the new frequency divider. ...................................................................................165 Fig. 8-6: Modulus control circuitry. ..........................................................................166 Fig. 8-7: Phase control circuitry. ..............................................................................167 Fig. 8-8: Phase select circuitry..................................................................................168 Fig. 8-9: Divide-by-8.25 operation at 2 GHz. ...........................................................169 Fig. 8-10: Divide-by-9.75 operation at 1 GHz. .........................................................170 Fig. 8-11: Microphotograph of the frequency divider and 1.2 GHz quadrature VCO.....................................................................................................................................171 Fig. 8-12: Power spectrum of the VCO output at 1.2 GHz........................................172 Fig. 8-13: Power spectrum of the frequency divider output at 123.1 MHz. ..............173 Fig. 8-14: Power spectrum of the frequency divider output at 154.8 MHz. ..............173 Fig. 9-1: A conventional fractional-N frequency divider. .........................................176 Fig. 9-2: Effect of unequal instantaneous frequencies in a fractional-N synthesizer.....................................................................................................................................176 Fig. 9-3: The proposed fractional spur reduction frequency divider. .......................178 Fig. 9-4: Phase error generated in the process to achieve a divide-by-(2 + 1/2) operation (a) without spur reduction; (b) with spur reduction technique. ................180 Fig. 9-5: Block diagram for the simulation of the new fractional-N technique. .......181 Fig. 9-6: Simulation results of a conventional fractional-N PLL..............................182 Fig. 9-7: Simulation results of the new fractional-N PLL with spur reduction circuit implemented. ..............................................................................................................182 Fig. 10-1: The photo of the network analyzer HP8510C...........................................186
1
CHAPTER 1
Introduction
1.1 Motivation
Phase-locked loops (PLLs) find wide applications in many areas such as
communication systems, wireless systems, digital circuits, power systems and disk
drives. PLL is the choice circuit for applications like frequency synthesizers and clock
recovery circuits (CRC) in communication. In the frequency synthesizer, the PLL
enables the generation of a stable periodic waveform whose frequency can be varied
over a wide range in small frequency steps. In the CRC, a PLL with a relatively
narrow bandwidth is used to minimize the effect of the input jitter on the recovered
clock.
In the design of the transceiver, there is a clear trend towards full integration
of the radio-frequency (RF) front end on a single die for the purpose of low cost and
low power. The design of RF building blocks in a CMOS process is now an important
research topic in order to replace the more expensive bipolar process. The use of a
submicrometer CMOS process for the RF circuits enables the circuits to incorporate
the digital baseband processing circuit on the same chip. The emergence of the
submicrometer CMOS technology has resulted in many high speed PLLs being
implemented in CMOS technology. However, due to technology limitations on the
passive component quality, the low transconductance of MOSFET [1] and high
intrinsic 1/f noise in MOSFET, the implementation of high speed fully integrated PLL
remains a challenge.
2
The two high frequency blocks in PLL, namely the voltage-controlled
oscillator (VCO) and the frequency divider, are most crucial in the feasibility of
integration in a CMOS process. The important parameter to determine the
performance of a VCO is the phase noise, which is related to jitter in the time domain.
In order to achieve the low-phase-noise specifications, the LC VCO is preferred to
other oscillator topologies such as inverter-based ring oscillators because of its high
quality factor (Q). However, the Q value of an integrated inductor is poor in the
CMOS process due to the high substrate loss. The thermal noise generated due to the
substrate loss causes significant phase noise. Thus, much effort is still needed to
achieve low phase noise.
Another major obstacle in the CMOS VCO design is the relatively low ft of
MOSFETs, which limits the maximum oscillation frequency of the VCO. The
proliferation of fiber optic communication applications, for example the SONET OC-
768 [2], which operates at 40 GHz, has led to a new challenge to the design of a fully
integrated circuit due to the ever increasing speed of operation. To date, the most
advanced SiGe technology can achieve an tf of about 100 GHz, the Indium
Phosphide (InP) technology can reach up to 160 GHz, and the InP devices will soon
reach an tf beyond 200 GHz. The next generation of the optical network that will
eventually replace the SONET OC-768 will operate at a frequency beyond 100 GHz.
Thus, improvement through circuit design must be done before the CMOS process
can be used in the future millimeter-wave applications.
In an RF transceiver, it is a common requirement that the frequency
synthesizer must be able to produce a periodic waveform whose frequency is accurate
and can be varied in small frequency steps. The fractional-N frequency divider allows
3
the PLL frequency synthesizer to have a frequency resolution finer than the reference
frequency. This technique originates from an early digiphase synthesizer [3], which is
subsequently commercially referred to as the fractional-N frequency divider [4].
Unfortunately, this technique generates unwanted low-frequency spur due to the fixed
pattern of the dual-modulus divider [5]. These low-frequency spur is in addition to the
reference spur [6]. Since this spur can reside inside the loop bandwidth, fractional-N
frequency synthesizers are not practical unless fixed inband spur is suppressed to a
negligible level.
Another problem of the fractional-N frequency divider is that the frequency
range of a fractional-N divider is equal to its reference frequency. This limits its
usefulness especially in wide band applications. A dual-band RF transceiver
architecture for personal communications services (PCS) and cellular-code division
multiple access cellular (CDMA) is demonstrated in [7]. This circuit used a charge-
averaging charge pump to solve the fractional spur problem. However, this approach
is only suitable for a small number of division ratios as it is limited by the complexity
of the charge pump. As the frequency range of a dual-modulus fractional-N
synthesizer in [7] is equal to the reference frequency, a reference frequency of 19.8
MHz cannot sufficiently cover the operating band. For example, the frequency band
for US-PCS spans from 1850 MHz to 1990 MHz, so the frequency range to be
covered is 140 MHz, which is much larger than the reference frequency of 19.8 MHz.
The example shows that the frequency band restricts the choice of the reference
frequency. Generally, as the reference frequency is equal to the operation frequency
of the phase detector (PD) and the charge pump of the PLL, a wide frequency range
will require the phase detector and charge pump to operate at higher frequency, which
requires larger power consumption.
4
1.2 Objectives
The goal of this research is to provide solutions for the problems in the fully
integrated PLL associated with the VCO and the frequency divider stated in the above
section. For the VCO, three approaches will be investigated. In the first approach, a
novel method for improving the phase noise performance of a CMOS quadrature LC
oscillator through parasitic-compensation will be presented. In the second approach,
CMOS LC oscillator implementing a new tail transistor topology that reduces the
intrinsic flicker noise will be introduced. In the last approach, novel millimeter-wave
(mmW) CMOS LC VCO implementing a push-pull buffer that can double the input
frequency will be introduced. For the frequency divider, two approaches will be
investigated. Firstly, a technique for reducing the fractional spur while providing a
wide frequency-coverage through a novel frequency divider will be presented.
Secondly, a fractional spur reduction technique that can fully suppress the fractional
spur will be introduced.
1.3 Major Contributions of the Thesis
There are five important contributions in this research. Firstly, a method for
improving the phase noise performance of a CMOS quadrature LC oscillator through
parasitic-compensation is introduced. Due to the parasitic resistance in the inductor,
the LC oscillator suffers from low Q value, which degrades its phase noise
performance. In this design, through the parasitic-compensation method, the LC
oscillator will be made to oscillate at the frequency where the effective impedance of
the parallel LC resonator is at the peak. This will increase the Q value of the LC
resonator, which improves the phase noise performance of the circuit. A fabricated
2.63 GHz quadrature CMOS LC oscillator with a phase noise of –112.3 dBc/Hz at
5
600 kHz offset was demonstrated, consuming a power of 7.5mW using an on-chip
spiral inductor.
Secondly, based on the understanding of the flicker noise generation in the
MOSFET, a novel method for improving the phase noise performance of a CMOS LC
oscillator is presented. In [8],[9], it has been suggested that the 1/f noise can be
reduced through a switched gate, and the flicker noise generated is inversely
proportional to the gate switching frequency. The novel tail transistor topology is
compared to the two popular topologies, namely, the fixed biasing tail transistor
topology [10],[11], and the topology without a tail transistor [12],[13]. A simulated
phase noise of -127.6 dBc/Hz at 600 kHz offset for an oscillation frequency of
1.88 GHz is achieved with a tank quality factor of 9. To date, few VCOs have met the
specifications of the WCDMA and CDMA2000 standards due to the stringent phase
noise requirement. This is especially true for fully integrated VCOs due to the low
inductor Q. An example of a VCO that meets the system specifications of the
WCDMA/CDMA2000 has been achieved through this novel topology.
Thirdly, a millimeter wave CMOS LC VCO implementing a push-pull buffer
that can double the input frequency is introduced. The oscillation frequency of the
VCO is 102 GHz, which is about twice the tf of the SiGe CMOS transistors of 52
GHz. Thus, a fully integrated VCO using SiGe can now be realized for applications
beyond 100 GHz. A VCO has been fully integrated in the 0.25µm SiGe MOSFETs
technology. The VCO has an oscillation frequency of 102 GHz with a tuning range of
3.4 GHz. In this tuning range, the phase noise is –106 dBc/Hz to –107.7 dBc/Hz at
1 MHz offset frequency. Besides being the VCO with the highest frequency reported
to date, this novel VCO also has the best figure of merit (FOM) of 192.9 dB.
6
Fourthly, a spur reduction fractional-N frequency divider with a frequency
range 3.5 times larger than that of a conventional fractional-N divider is presented in
this thesis. A 1.2 GHz quadrature VCO is designed as the input source of the
frequency divider. The circuit is fabricated using the CMOS 0.25µm technology, the
power consumption of the frequency divider and the quadrature VCO are 3mW and
6mW at 2V supply, respectively.
Finally, a technique that can fully suppress the fractional spur generated by the
fractional-N frequency divider is proposed. In addition, this provides a simple
solution to spur reduction, which requires only two additional 2-to-1 multiplexers to
the conventional fractional-N frequency divider.
1.4 Organization of the Thesis
This thesis is organized into ten chapters. Chapter 1 provides an introduction
to the problem addressed, and an outline of the thesis.
The theory, mathematical description and operation of a PLL will be discussed
in Chapter 2. The noise properties of the PLL building blocks, i.e. the voltage-
controlled oscillator, the frequency divider, the phase detector and the loop filter are
investigated. Attention is paid to the loop filter, which plays an important role in the
transient loop characteristic, the output noise spectrum and the loop stability.
In Chapter 3, an overview of the VCO design will be studied. Several types of
oscillators namely, ring oscillators, cross-coupled oscillators, and quadrature
oscillators will be presented. The design of a differential LC VCO will then be
discussed in detail.
7
Chapter 4 presents a novel parasitic-compensated quadrature LC oscillator. In
Chapter 5, the design of the novel RF CMOS low-phase-noise LC oscillator using
memory reduction tail transistor technique will be discussed. Chapter 6 examines the
design of the novel 102 GHz SiGe MOSFETs LC oscillator.
In Chapter 7, a literature review of the frequency divider will be given.
Several types of frequency synthesizers, such as integer-N frequency synthesizer and
fractional-N frequency synthesizer will be discussed. Conventional spur reduction
techniques will be presented.
Chapter 8 proposes the design of a novel fully integrated CMOS fractional-N
frequency divider for wide-band mobile applications with spur reduction. A novel
fractional-N frequency divider with spur reduction technique will be introduced in
Chapter 9.
Finally, Chapter 10 concludes the thesis with a summary of results and a list of
key research areas for further investigation.
8
CHAPTER 2
Background and Literature Review
of the PLL Frequency Synthesizer
Recent statistics indicate that the RF integrated circuit (RFIC) market has
expanded greatly during the last few years despite the global economy downturn.
Devices such as pagers, cellular and cordless telephones are rapidly penetrating all
aspects of our lives, evolving from luxury items to indispensable tools. About ten
years ago, the introduction of the global system for mobile communications (GSM) in
Europe and the development of low-cost production facilities for the mass production
of highly integrated silicon-based circuits capable of operating at gigahertz
frequencies have created a big market in Europe [14]. In the United States, the
European GSM is deployed in the 1900 MHz band and is named PCS1900. A single
GPS channel is at 1575 MHz. The 2.4 GHz Industrial Scientific Medical (ISM) band
has also attracted numerous applications. It is expected that the advent of third-
generation (3G) mobile communication systems, summarized as international mobile
telecommunication systems (IMT-2000), as well as other wireless applications (e.g.,
Bluetooth [15], wireless local area networks (WLANs) [16], wireless local loops
(WLLs) [17], etc.) will further stimulate the rapid development of the RFIC market.
The explosive growth of today’s telecommunication market has brought an increasing
demand for high-performance RF circuits in low-cost technologies including smaller
size and lower power consumption. A monolithic transceiver is the solution for these
growing demands. In the RF transceivers, one major concern for full integration is the
design of the local oscillator (LO) frequency synthesizer [19].
9
To begin this chapter, a brief discussion on the fundamental principles of the
phase-locked loop (PLL) will be given. Subsequently, several implementations that
exist for the phase detector and the loop will be described. The transient
characteristics of the PLL will then be examined. Finally, the noise characteristics of
each block in the PLL are presented. In this section, the calculation of loop dynamics,
which affect the noise performance, will be discussed. Throughout this work,
examples of the PLL in the applications of frequency synthesizers will be given.
2.1 Fundamental Principles of a Phase-Locked Loop (PLL)
Fig. 2-1: Block diagram of a PLL.
A PLL is a control system, where phase is the variable of interest. The block
diagram of a PLL is shown in Fig. 2-1. The circuit is called a phase-locked loop
because the feedback operation in the loop automatically adjusts the phase of the
output signal Fout to follow the phase of the reference signal Fref. Fig. 2-2 shows the
state variable diagram of the PLL, the circuit is constructed by using the phase of the
reference signal θref(t) and the phase of the output signal θout(t) as loop variables. The
prescaler (Frequency Divider in Fig. 2-1) divides the VCO frequency (and phase) by a
Fout Fref
Fdiv
Phase
Detector
Loop Filter
Frequency Divider
÷N
VCO
10
division modulus of N. Let θdiv(t) be the phase of the output signal of the prescaler, the
following equation is obtained
θdiv(t) = θout(t)/N
Fig. 2-2: State variable diagram of a PLL.
In order to analyze the steady state transfer function of the PLL, the
assumptions are made that a constant reference frequency is applied and the division
modulus is fixed. Now, assuming that the loop is locked and the phase detector gives
an output voltage vpd(t) proportional to the phase difference between its inputs θref(t)
and θdiv(t)
[ ])t()t(K)t(v divrefpdpd θθ −=
where Kpd is the gain of the phase detector in V/rad.
The phase detector output voltage is then passed through the low-pass filter
where the high frequency signal components are suppressed. The loop filter
determines largely the noise and dynamic performance of the loop.
Vc Vpd _
+ Σ
θout θref
θdiv
Glf(s)
÷N
VCO
(2.2)
(2.1)
11
An ideal voltage-controlled oscillator (VCO) generates a periodic output
whose frequency is a linear function of the control voltage vc and is given by
cvcofrout vK ×+= ωω
where ωfr is the free running frequency of the VCO and Kvco is the gain of the VCO
specified in rad/s/V. Since frequency is the derivative of phase, the VCO operation
can be described as
(t)vKdt
(t)dθcvco
out ⋅=
Taking the Laplace transform, it leads to
ssVK
s cvcoout
)()(
⋅=θ
Fig. 2-3: Linear time-invariant phase-model of the PLL.
If the signals around the loop are interpreted by their phases, the small-signal
noise behavior of the loop can be explored by linearizing the components and
evaluating the transfer functions. Fig. 2-3 shows the linear time-invariant (LTI) phase-
(2.5)
(2.4)
(2.3)
θdiv
θpd θvco
_
+ Σ
θout θref Kpd
÷N
+ +
Σ
+ +
Σ
θlf
F(s) +
+ Σ Kvco/s
+
+ Σ
12
model of the PLL. The forward gain is equal to ( ) sKsFKsG vcopd ××=)( , while the
feedback gain is equal to H(s)= 1/N. Hence, the open loop gain OL(s) is obtained as
sNK
sNKsFK
sHsGsOL Fvcopd
⋅=
⋅
⋅⋅=⋅=
)()()()(
where KF is the forward gain of the PLL and has unit of s-1. Equation (2.6) is useful to
study the operation of the PLL, such as the step response and the stability of the
system.
2.2 Transient Characteristics
In this section, the dynamic behavior of the loop when it is subjected to a
phase step or a frequency step in the reference frequency will be examined. Then the
startup behavior of the loop will be discussed.
2.2.1 Tracking
Equation (2.7) represents a phase step with a magnitude of ∆θ being applied
to the reference signal. The assumptions are made that the loop is in lock state and the
phase error is sufficiently small to justify an assumption of linearity.
θ∆θ )t(u)t(ref =
where u(t) is the unit step function. Applying the Laplace transform, equation (2.7)
becomes
ssref θθ ∆=)(
(2.7)
(2.8)
(2.6)
13
For t approaching infinity, the final value theorem of the Laplace transform
states
)s(s)t(st
θθ0
limlim→∞→
=
Therefore, the resulting steady state phase error for a first-order loop is
0])/(1
1[lim])(1
1)([lim00, =
+⋅
∆⋅=
+⋅⋅=
→→ NsKss
sGHss
Fsrefssserr
θθθ
It can be seen from the above equation that the PLL will reduce any phase
error to zero if given sufficient time.
If the input frequency changes with a step size of ∆ω, the input phase equals
θref(t) = t×∆ω. This situation appears when the division modulus in synthesizer is
changed. The resulting steady-state phase error is
pFFssserr K
NNsKs
sω
ωωωθ ∆=
⋅∆=
+⋅
∆⋅=
→]
)/(11[lim 20,
where ωp is the loop bandwidth in radians/sec, which is defined as the frequency
where the open loop gain is equal to one. In a system such as GSM, the local
oscillator (LO) has to switch from the receive channel to the transmit channel or
switch from one frequency band to another frequency band. The switching time
requirement must satisfy the GSM’s system specifications. This switching time TE is
the time a PLL takes to settle the new output frequency to be within a specified
accuracy E. In order to calculate TE, the following equation is used [28]
)s(sss
s)s(GH)s()s(
ppreferr ω
ω∆ω
ω∆θθ+⋅
=+
⋅=+
⋅= 211
(2.9)
(2.10)
(2.11)
(2.12)
14
Equation (2.12) in time-domain can be obtained as
)e()t( t
perr
pω
ωω∆θ −−⋅= 1
The final frequency is obtained after an exponential behavior with a time
constant τp = 1/ωp. For E = 1e-6, the switching time TE is given by [39]
ppE f
.ET 22ln=−=
ω
For a loop bandwidth fp of 3.3 kHz, the switching time TE is equal to
0.667msec. In GSM, for a frequency step of about 100 MHz, the settling time must be
done within 10msec for E = 1e-6 [28].
2.2.2 Acquisition
During startup, the PLL is initially in an unlocked condition, the process of
achieving lock state is called acquisition. Since acquisition is inherently a non-linear
process, its qualitative analysis is beyond the scope of this work. In this work, some
descriptive analysis will be done, more information can be found in [29]-[30].
If the initial VCO frequency is close enough to N×Fref, the PLL will lock up
with just a phase transient. The frequency range over which no cycles will be missed
before lock is obtained, is called the lock range, ∆ωL. If a reference frequency outside
the lock range is applied, the pull-in process will be slower. The normal operation of
the PLL is generally restricted to the lock range.
The pull-in range, ∆ωPI, describes the PLL in a dynamic state or an acquisition
mode. The pull-in range is the range within which a PLL will always become locked
(2.13)
(2.14)
15
through the acquisition process [31]. If the reference frequency is outside the pull-in
range, the PLL will not be able to lock onto the reference signal.
The hold range, ∆ωH, describes the PLL in a static or locked state. The PLL is
initially locked with reference signal. If the reference signal’s frequency changes too
much, the PLL will lose lock at the edge of the hold-in range. The PLL is
conditionally stable within the hold-in range [31]. The hold-in range is larger than
both above defined ranges. As will be discussed in Section 2.3.1, the linear
approximation of the phase error due to a frequency offset is shown to be θres,ss =
∆ω/KF. However, a real phase detector does not have an infinite linear range. For a
sinusoidal-characteristic phase detector, the true expression should be sinθres,ss =
∆ω/KF [28]. Since the sine function cannot exceed unit magnitude, there is no solution
for ∆ω > KF. The hold-in range therefore equals ∆ω = ±KF. Other types of phase
detector, for example the charge pump phase-frequency detector, have a larger linear
range and can therefore extend the hold-in range. However, these definitions are only
valid as long as the limit is set by the phase detector and not by some other
nonlinearities, such as the clipping in an operational amplifier (op-amp) or the VCO
frequency tuning range.
2.3 Phase Detector and Loop Filter
This section will describe the phase detector and loop filter. Various
implementations of phase detectors will be discussed. Then, the transfer
characteristics of the loop filter will be discussed. Finally, the calculation of an
optimum loop bandwidth will be presented. More information can be found in [29]-
[34].
16
2.3.1 Phase Detector
In this section, several representative phase detectors will be described. Phase
detectors can be classified into three major categories: analog phase detector, digital
phase detector, and phase-frequency detector. Firstly, the analog phase detector or
multiplier generates a DC component, which is dependent on the phase difference of
input signals. The DC component is used for phase difference detection. Secondly,
digital phase detector, such as the EXOR and the flip-flop phase detector, detects the
phase difference of the input signals based on their zero crossing points. Thirdly, the
phase-frequency detector is a sequential circuit, and it provides a frequency sensitive
signal to improve the acquisition when the loop is out of lock.
2.3.1.1 Multiplier
A multiplier acts as a phase detector through the trigonometric identity
)BA()BA()B()A( ++−= sin21sin
21cossin
If the input signals to the multiplier are v1 = A1sin(ω1t + θ1) and
v2 = A2cos(ω2t + θ2), the multiplier output signal will be
])(sin[])(sin[21
2121212121
21
θθωωθθωω ++++−+−⋅⋅⋅=
⋅⋅=
ttAAA
vvAv
d
dd
where Ad is the constant associated with the multiplier.
At phase lock, both frequencies are the same and the DC component of the
phase detector output equals 0.5×Ad×A1×A2×sin(θ1-θ2). This component indicates the
phase difference between the two signals. Various unwanted signal components are
(2.15)
(2.16)
17
also present at the output, such as the sum of the two input frequencies. The loop filter
will remove these unwanted signal components. One of the common implementation
of the multiplier phase detector is the Gilbert multiplier [30].
2.3.1.2 EXOR Gate
Fig. 2-4 shows the EXOR gate phase detector. The operation of an EXOR gate
phase detector is similar as an over-driven multiplier circuit and it has triangular
phase detector characteristics. However, square wave inputs of 50% duty cycle are
recommended for the EXOR phase detector. For other duty cycles, the detection range
may be significantly reduced. In addition, it is possible to have the same output
voltage for two different phase errors [120]. The output waveforms for inputs A and B
are shown in Fig. 2-5. The average value C of the output waveform is proportional to
the phase difference between the input signals. The phase detector transfer
characteristic is shown in Fig. 2-6.
Fig. 2-4: EXOR gate phase detector.
C
A
B
18
Fig. 2-5: The operation of an EXOR gate phase detector.
Fig. 2-6: The transfer characteristics of an EXOR gate phase detector.
2.3.1.3 Flip-Flop Phase Detector
An edge-sensitive set-reset (SR) type of flip-flop can be used to detect the
phase difference of pulse trains, which do not have 50% duty cycle. The flip-flop
phase detector is shown in Fig. 2-7. Narrow pulses at input A set the output C, while
A
B
⊕ C=A B
τ T
0 0.5 1
/T τ
C
19
narrow pulses at input B reset the output C. The average value of C has the shape of
a sawtooth, with a linear range of a full cycle. The operation and the transfer
characteristics of a flip-flop phase detector are shown in Fig. 2-8 and Fig. 2-9,
respectively.
Fig. 2-7: Flip-flop phase detector.
Fig. 2-8: Operation of a flip-flop phase detector.
A
B
C
τ T
S
R
Q
A
B
C
20
Fig. 2-9: Transfer characteristics of a flip-flop phase detector.
2.3.1.4 Phase Frequency Detector
The phase frequency detector (PFD) has an unlimited pull-in range [34],
which is an advantage over the EXOR, flip-flop and multiplier phase detector. The
PFD is usually implemented together with a charge pump, as shown in Fig. 2-10. The
PFD has two outputs, Up and Dn, which open or close the two current sources of the
charge pump. The output current is then converted to a voltage across the impedance
Zlf.
The operation of the PFD is shown in Fig. 2-11. The PFD has two inputs, the
reference signal REF and the feedback signal from the divider Div. The reference pulse
causes the output to change to a positive direction, unless the output is already
positive, in which case the pulse has no effect on the output. Similarly, the loop’s
divider output causes a negative transition unless the output is already negative. The
transfer characteristics of the PFD are plotted in Fig. 2-12 and have a linear phase
range of 4π.
0 0.5 1
/T τ
C
21
Fig. 2-10: Phase frequency detector.
Fig. 2-11: Operation of the phase frequency detector.
I
I
VDD
Zlf
IPREF
Div
Up
Dn
PhaseFrequencyDetector
22
Fig. 2-12: Transfer characteristics of the phase frequency detector.
The PFD in Fig. 2-10 suffers from a “dead zone”, which arises from the
crossover distortion, where changes in gain occurring near the zero phase error [35].
If both the reference pulse and the divider pulse appear at the same time, none of the
outputs becomes active and the charge-pump output is in high-impedance state. Even
if the phase difference changes slightly, the phase detector will not respond
immediately since it requires some finite time for the Up and Dn pulses to propagate
through the circuit. Therefore, the charge pump keeps its high impedance state
although there is a slight phase difference. Hence, the phase detector characteristic
actually has a flat response, which is known as dead zone, near the zero phase
difference.
Giving a fixed minimum width to both the charge pump pulses can solve the
problem of the dead zone. Fig. 2-13 shows a PFD circuit that is free of dead zone [36].
0 0.5 1/Tτ
-1 -0.5
C
23
The output terminals Up and Dn are designed to be active low. The delay block after
the 4-input NAND circuit determines the minimum width of the up- and down-pulses.
If the divider output lags the reference signal, the up signal will become active for a
certain time TD. Where TD is equal to the time difference between the two signals, and
the delay through the circuit, including the delay caused by the extra delay stage.
Similarly, the down-pulse will also become active for a short period due to the extra
delay. The net difference between the up-time and down-time determines the total
change in the charge pump output voltage, and is proportional to the phase difference
between the two PFD inputs. For the case when the divider signal leads the reference
signal, even without a phase difference between the two inputs, both the up- and
down-signals are active for a short period determined by the delay stage. However,
the net charge injected into the impedance Zlf is zero, since the two pulses are of equal
magnitude and opposite polarity. In this case, the charge pump is not in a high-
impedance state and the loop is always closed.
24
Fig. 2-13: Phase frequency detector without dead zone.
2.3.2 Loop Filter
There are two types of loop filters, active and passive. An active filter uses op-
amps to generate a tuning voltage higher than that generated by a passive filter. The
op-amp itself provides the DC amplification necessary to develop a high control
voltage required by the VCO in wide band applications. Passive filter has the
advantages of reduced noise and lower circuit complexity. They are formed by only R
(resistor), C (capacitor) elements, and often used as the charge pump loads to generate
the control voltage proportional to the phase error. The charge pump passive loop
filter is used widely for wireless applications, and is referred to as the current source
REF
Div
Delay Stage
Up
Dn
25
loop filter [37]. This is in contrast to the voltage source loop filter for an active loop
filter.
2.3.2.1 Charge Pump PLL
Fig. 2-14 shows a 3rd order, type-2 charge-pump PLL. The phase detector’s
current source outputs pump charge into the loop filter, to produce the VCO’s control
voltage. Compared to a 2nd order charge-pump PLL, the extra capacitor C1 in the 3rd
order PLL is added to smooth out the discrete voltage steps at the control port of the
VCO due to the instantaneous changes in the charge pump current output. At each
cycle of the PFD, a pump current Icp is driven into the filter impedance with an
instantaneous voltage jump of IcpR2. The corresponding frequency jump is
pcpvco RIK ωπω ×=××=∆ 22
which is generally larger than the average frequency increment per cycle [38].
Fig. 2-14: A 3rd order, type-2 charge pump PLL filter.
C 1 C 2
R 2
From Charge Pump, I cp (t)
To VCO
(2.17)
26
The filter can be designed based on the open loop gain bandwidth and the
phase margin required. Positioning the point of minimum phase shift at the unity gain
frequency of the open loop response as shown in Fig. 2-15 ensures the loop stability.
The phase relationship between the pole and zero also allows the determination of the
loop filter component values. The phase margin θp is defined as the difference
between 180° and the phase of the open loop transfer function at the unity-gain
frequency fp. The phase margin is chosen between 30° and 70° for most applications
[39]. The larger the phase margin, the more stable the loop. However, the transient
response is slower and requires a longer switching time. A loop with a low phase
margin may still be stable but could exhibit oscillator problems associated with an
undamped loop, such as longer switching time and increased noise. A phase margin of
45° is a good compromise between desired stability and the other generally undesired
effects.
27
Fig. 2-15: Bode plot of the open loop response for a 3rd order, type-2 charge pump PLL filter.
The impedance of the filter in Fig. 2-14 is
212212
22 1)(
CsCsRCCsRCs
sZ⋅+⋅+⋅⋅⋅
+⋅⋅= (2.18)
Phase (degree)
Amplitude (dB)
(2 T 2) -1π
-40dB/dec
0dB
-20dB/dec
-40dB/dec
Gain Margin
-180
-90
(2 T 1) -1 π
p θ
p f f
f
28
From equation (2.18), the gain and the phase of the loop filter can be derived.
The time constants that determine the pole and zero frequencies of the filter transfer
function are defined by the following equations
21
2121 CC
CCRT
+⋅
⋅=
222 CRT ⋅=
Thus, the 3rd order PLL open loop gain defined by equation (2.6) can be
rewritten as
2
1
112
2
)1()1(
|)(TT
TjNCTjKK
sOL vcopdjs ⋅
⋅+⋅⋅⋅
⋅+⋅⋅== ωω
ωω
There are three poles in equation (2.21), where two of the poles are
contributed by the capacitors C1 and C2, while the third pole is contributed by the
integrator of the VCO. From equation (2.21), it can be seen that the phase term is
dependent on the single pole and zero such that the phase margin can be determined
by equation (2.22).
)(tan)(tan)( 11
21 TTp ⋅−⋅= −− ωωωθ
By equating the derivative of the phase margin to zero, equation (2.22)
becomes
0)(1)(1 2
1
12
2
2 =⋅+
−⋅+
=T
TT
Tdd p
ωωωθ
Thus, the loop bandwidth ωp can be given by
(2.19)
(2.20)
(2.21)
(2.22)
(2.23)
29
121 )( −⋅= TTpω
Sometimes, the 3rd order structure does not provide sufficient rejection to the
reference spur. The reference spur is caused by the current switching noise in the
dividers and that in the charge pump at the reference rate Fref. In wireless
communications, the phase detector operation frequency is generally a multiple of the
RF channel spacing. These spurious sidebands can cause noise in adjacent channels.
This is usually the case in the TDMA digital cellular standards, such as GSM or IS-54.
A narrow loop filter has advantage of better attenuation of the reference spur, but the
requirement of the sub-milliseconds switching between channels makes a relatively
wide loop filter mandatory.
One solution is to use an additional low pass pole for more attenuation of the
unwanted spur. The use of a passive loop filter eliminates the noise contributions from
the op-amp in an active filter. This is critical due to the strict phase error and
integrated phase noise requirements. For example, the integrated phase noise
requirement for the SONET’s OC-192 specification is 1 ps root-mean-square value
(rms). The recommended filter configuration is shown in Fig. 2-16.
(2.24)
30
Fig. 2-16: A 4th order, type-2 charge pump PLL filter.
The additional pole must be lower than the reference frequency to
significantly attenuate the reference spur, but must be at least 5 times higher than the
loop bandwidth to maintain the loop stability [37]. The additional filter time constant
can be defined as
1333 )( −⋅= CRT
The bode plot of the open loop response for the 4th order charge pump PLL is
shown in Fig. 2-17.
(2.25)
C1
C2
R2
From Charge Pump ,Icp(t)
To VCO
C3
R3
31
Fig. 2-17: Bode plot of the open loop response for a 4th order, type-2 charge pump PLL.
A charge pump PLL for the GSM applications has been simulated to illustrate
the open loop response of the 3rd order and 4th order charge pump PLLs. Fig. 2-18
shows the filter response and the PLL open loop gain for the 3rd and 4th order cases.
The 3rd order loop filter response shows a 20 dB/dec slope due to the integrator from
the loop filter, flattening out at the zero frequency which is equal to 1/(2πT2) = 4.5
kHz in the example. For the 4th order loop filter, the response again drops at the rate
of 20 dB/dec starting at the pole frequency of 1/(2πT1) = 54 kHz. The slope of the
Phase (degree)
Amplitude (dB)
(2 T 2)-1π
-40dB/dec
0dB
-20dB/dec
-40dB/dec
Gain Margin
-180
-90
(2 T 1)-1π (2 T 3)-1 π
-60dB/dec
p θ
p f f
f
32
open loop gain for the both 3rd and 4th order charge pump PLL is 20 dB/dec more than
their respective loop filters gain due to the integrator from the VCO. The slope before
the zero is 40 dB/dec, it changes to 20 dB/dec after the zero and then changes back to
40 dB/dec after the first pole. For the 4th order loop filter, the slope changes to 60
dB/dec after the second pole at the frequency of 1/(2πT3) = 1 MHz.
Fig. 2-18: Loop filter gain and PLL open loop gain for 3rd and 4th order charge pump PLLs.
The phase responses are shown in Fig. 2-19. For both the 3rd and 4th order
filters, the phase shift at the zero frequency is –90o. The phase approaches 0o after the
zero, and then drops back to –90o after the first pole. For the 4th order filter, the phase
approaches –180o after the second pole. The open loop phase for both cases differs
from their respective loop filters phase by –90o. For both the 3rd and 4th order loop
filters, the phase starts at –180o. It approaches –90o after the zero, and returns to –180o
33
after the first pole. For the 4th order loop filter, the phase goes to –270o after the
second pole.
Fig. 2-19: Loop filter phase and PLL open loop phase for 3rd and 4th order charge pump PLLs
2.4 Noise Characteristics of PLL Building Blocks
The PLL is susceptible to phase noise or jitter because it operates on the phase
of signals. Phase noise is usually characterized in the frequency domain while jitter on
the other hand is characterized in the time domain. An amplitude- and phase-
modulated sinusoidal output signal of an oscillator can be written as follows
[ ] [ ])(2sin)(1)( ttftvVtV camoout θπ ++= (2.26)
34
where Vo is the amplitude, fc is the carrier frequency, vam(t) is the amplitude-
modulation (AM) component and θ(t) is the phase-modulation (PM) component. The
AM component will be omitted since only the phase noise is concerned.
[ ])(2sin)( ttfVtV coout θπ +=
For a sinusoidal-angle modulation with a rate of fm
t)πf(f∆fθ(t) c
m
2sin⋅=
Let β = ∆f/fm, equation (2.27) becomes
[ ])2(sin2sin)( tftfVtV mcoout πβπ +=
where fm is the modulation frequency, ∆f is the peak frequency-modulation deviation,
and β is the modulation index. For small-angle modulation, where β < 1,
trigonometric identities can be applied. This leads to
Recently, CMOS dynamic circuit techniques have been developed to achieve
high speed operation for digital circuits. Specially, the True Single Phase Clock
(TSPC) [91] circuit technique has become popular for its high speed operation. Single
phase clock strategies like TSPC achieve higher clock frequencies because they can
simplify the clock distribution
Dividers are composed of gates and flip-flops. There are three main types of
flip-flops: J-K flip-flop, D flip-flop and set-reset (S-R) flip-flop. The D flip-flop
(D-FF) is by far the most commonly used flip-flop in a divider. This is due to its
simple function, and few logic inputs.
In this section, a brief discussion of popular high-speed flip-flops, for example,
the D-FF published by Yuan-Svensson [91] and the D-FF published by Huang-
Rogenmoser [92] will be given.
137
7.3.1 Yuan-Svensson D-FF
The D-FF published by Yuan-Svensson [91], which is the state-of-the-art
design and one of the most important high speed digital circuit building blocks will be
discussed in detail. Fig. 7-10 shows the circuit of Yuan-Svensson D-FF, where QB is
the inverted output of the D-FF, D is tied to QB to form a frequency divider and CLK
is the input.
Consider first the state transition (a) in Fig 7-11, where QB = D = 0 and CLK
turns low. Node y1 in Fig. 7-10 attempts to charge up to logic 1 during CLK = 0. As
QB = D = 0, transistor M3 is in cutoff region throughout the clock phase. As the clock
signal CLK remains zero, switch transistors M6 and M9 are off. Node y2 was high in
the previous clock phase and will remain high in the current precharge phase [91].
In the state transition (b) in Fig. 7-11, when CLK turns from low to high, M6
pulls the source of M5 down to ground. Although D = 1 causing M3 to turn on, and
discharging y1. CLK = 1 causing M1 to turn off, much of the charge stored in its
channel is transferred to the gate of M5 (y1). The later effect temporarily compensates
for the drop in voltage due to M3 being turned on. As the voltage at the source of M5
is near to ground, and y1 does not come down much, M5 will remain on. Following
the precharge phase described above, y1 causes node y2 to discharge from high to low
through transistors M5 and M6. The discharge of y2 will in turn cause QB to charge
up to logic 1 via M7 [92].
Subsequently in the state transition (c) in Fig. 7-11, comes the precharge phase
again. The clock signal CLK turns to zero, and the transistors M6 and M9 are turned
off. M2 is also turned off during this clock phase. Finally, in the state transition (d) in
138
Fig. 7-11, the precharged y2 causes QB to discharge from high to low. M1, M4 and
M7 remain turned off during the clock phase.
Fig. 7-10: Yuan-Svensson D-FF.
Fig. 7-11: The four possible transients of Yuan-Svensson D-FF in toggle configuration.
CLK
QB
(d) (b) (a) (c)
M8
M9
M7 M4
M6 M3
M5 M1
M2
VDD
GND
QB
CLK
y2
y1
CLK
CLK
CLK D
139
7.3.2 Huang-Rogenmoser D-FF
Huang-Rogenmoser D-FF [92] is an improved version of Yuan-Svensson D-
FF, thus the operation principle of the Huang-Rogenmoser D-FF is similar to that of
Yuan-Svensson D-FF. Huang-Rogenmoser D-FF is a glitch free, general purpose,
high frequency D-FF with complementary outputs. In addition, Huang-Rogenmoser
D-FF can run at frequencies from tens of hertz to about a couple of gigahertz [92].
Fig. 7-12 shows the circuit diagram of Huang-Rogenmoser D-FF. M13 and M14 are
discharging transistors used to prevent the improper operation of the circuit at low
frequency [110]. M15 and M16 are deglitching transistors while M10 and M11 form
an inverter to provide an inversion of QB. The operations of the discharging transistor
and deglitching transistor are given in [92]. The details of the design of Huang-
Rogenmoser D-FF will be discussed in Section 7.4.
Fig. 7-12: Huang-Rogenmoser D-FF.
QB
D
VDD
GND
M1
M2
M3
M16
M15
M14
M4
M5
M6
M9
M12
M8
M7 M13
M11
M10
CLK CLK
CLK CLK Q
y1
140
7.3.3 Jan Craninckx’s D-FF
Jan Craninckx’s D-FF [94] is based on a standard Master and Slave ECL D-FF
[94]. The circuit exploits the speed enhancement by the reduction in voltage swing.
There are two disadvantages of this circuit. Firstly, the amplitude of the output signal
is approximately 0.7Vp-p operating at 2 GHz under a 3V supply [94]. Hence, an
amplifier might be needed to amplify the output signal, which increases the
complexity of the circuit and introduces extra delay to the frequency divider.
Secondly, an extra biasing voltage is needed in the circuit [94], which again increases
the complexity of the circuit and the power consumption.
7.4 Design of Frequency Divider
Due to the high frequency and wide range of operation, the design of the
frequency divider requires much attention. A frequency divider is designed such that
it is fast enough to operate at the highest frequency, and still be able to operate
properly at lower frequency, with the minimum power consumption. Fig. 7-13 shows
a divide-by-8 frequency divider. Huang-Rogenmoser D-FF is used as the basic
divide-by-2 circuit. The first two flip-flops, which are denoted as A in Fig. 7-13, are
optimized for the high speed. The last two flip-flops, which are denoted as B, are
optimized for the lower speed and minimum power consumption while still be able to
drive the load at the output of the divider.
141
Fig. 7-13: Frequency divider for divide-by-8 operation.
As mentioned previously, both Yuan-Svensson D-FF and Huang-Rogenmoser
D-FF are based on the TSPC circuit technique. An analogy between a dynamic TSPC
toggle-flip-flop and a three-inverter ring oscillator is shown in Fig. 7-14. The toggle-
flip-flop can be regarded as a three-inverter ring oscillator with some additional
control transistors that will regulate the oscillation frequency to about half of the input
frequency from the port CLK [28].
D
Q CLK
QB
A
D
QCLK
QB
A
D
QCLK
QB
B
D
QCLK
QB
B
Fin Fin/8
142
(a)
(b)
Fig. 7-14: Analogy between (a) dynamic TSPC CMOS toggle-flip-flop; and (b) three-inverter ring oscillator.
The design of the flip-flop needs a good understanding of the transistor model.
Fig. 7-15 shows the high frequency model of a MOS transistor [76], where gm is the
transistor transconducance, gs is the backgate transconductance, and rds is the drain-
M8
M9
M7 M4
M6 M3
M5 M1
M2
VDD
GND
QB
CLK
y2
y1
CLK
CLK
CLK
143
source resistance. There are four parasitic capacitance in Fig. 7-15: Cgs, Cgd, Csb, and
Cdb, where the subscripts indicate the location of the capacitance in the model. Cgs is
the gate-channel capacitance to the source, Cgd is the gate-channel capacitance to the
drain, Csb is the source-body junction capacitance, and Cdb is the drain-body junction
capacitance.
Fig. 7-15: High frequency model of a MOS transistor.
There are two types of internal capacitance in the MOS transistor. Firstly,
there are those capacitance that arise from the gate capacitive effect, which are
represented by the two capacitance Cgs and Cgd. The gate electrode (polysilicon) forms
a parallel-plate capacitor with the channel, with the oxide layer serving as the
capacitor dielectric, the oxide capacitance is denoted as Cox. The values of the two
capacitance Cgs and Cgd can be determined as follows [112]
rdsgsVsgmVgs
CdbCgs
Cgd
Vg
+
-Vgs
Csb Vs
Vd
144
1. For a MOS transistor operating in the triode region at small VDS, the channel
will have a uniform depth. The gate-channel capacitance will be WLCox and
can be modeled by dividing equally between the source and gate ends. Thus
OXgdgs WLCCC21
==
2. For a MOS transistor operating in the saturation region, the channel has a
tapered shape and is pinched off at or near the drain end. Thus, Cgd is zero
[113]
OXgs WLCC32
=
0=gdC
3. When the MOS transistor is in the cut off region, the channel disappears
0=gsC
0=gdC
4. The overlap capacitance Cov arises from the fact that the source and drain
diffusions extend slightly under the gate oxide. The overlap length is denoted
as Lov. The overlap capacitance should be added to Cgs and Cgd in all the
preceding formulas.
oxovov CWLC =
(7.2)
(7.3)
(7.4)
(7.5)
(7.6)
(7.7)
145
Secondly, the source-body and drain-body depletion-layer capacitance is
another type of internal capacitance, which are represented by Csb and Cdb. The source
body capacitance can be represented by
0
0
1 VVC
CSB
sbsb
+=
where Csb0 is the capacitance value of Csb at the zero reverse-bias voltage, VSB is the
magnitude of this reverse-bias voltage, and V0 is the junction built-in voltage.
Similarly for the drain diffusion, the drain-body capacitance Cdb can be represented by
0
0
1 VVC
CDB
dbdb
+=
where Cdb0 is the capacitance value at the zero reverse-bias voltage, and VDB is the
magnitude of this reverse-bias voltage. Note that it is assumed that for both junctions,
the grading coefficient m = 0.5 [112].
The circuit in Fig. 7-12 can be optimized using the design flow diagram as
shown in Fig. 7-16. The frequency divider is design to operate from 100 MHz to
1 GHz. The flow starts with the design of the first stage, which consists of M1, M2
and M3 to drive M5, M15 and M16. The second stage consists of discharging
transistor M14, as well as deglitching transistors M15 and M16. The third stage
consists of M4, M5 and M6, which drive M7 and M8. The fourth stage consists of M7,
M8, M9 and M12 to drive M10 and M11. The output stage consists of M10 and M11
to drive M1’, M4’, M6’ and M9’ of the next D-FF, as Q of the present D-FF is
connected to CLK of the next D-FF (refer to Fig. 7.13). In addition, the output stage
(7.8)
(7.9)
146
has a discharging transistor M13. The detailed calculations of the design will be
shown in the next section.
After designing the five stages, the frequency divider is verified through
simulation for the operation frequency from 100 MHz to 1 GHz. If the circuit fails to
operate at high frequency, optimization can be done by fine tuning the aspect ratios of
the transistors in the circuit. Generally, increasing the aspect ratio of the transistor will
decrease the delays in the signal path. However, this will eventually load the nodes in
the circuit. The parasitic capacitance of the transistors increases with their aspect
ratios, this in turn will slow down the circuit.
However, as general guidelines, M2 and M3 can be made smaller, as they only
drive M5, M15 and M16. M15 and M16 are deglitching transistors that require a
minimum aspect ratio [92], so their parasitic capacitance can be neglected. Effectively
the only load that M2 and M3 need to drive comes from M5. The size of M5 can be
increased to drive M7 and M8 faster. The sizes of M7 and M8 can be increased to
drive the output stage faster. The sizes should be adjusted in the mentioned order for
an optimum frequency performance.
If the circuit fails to operate at low frequencies due to the discharging of the
output nodes of each stage, the following guidelines are recommended. Firstly, to
increase the aspect ratios of the discharging transistors M13 and M14. Secondly, to
reduce the aspect ratios of M3, M4 and M7 as this will increase the output resistance
of the respective stages. When the circuit works properly, the layout can be done. The
LVS (layout versus schematic) and parasitic extraction process can be performed to
extract the parasitic introduced by the interconnections. The operation of the circuit is
147
then verified through post-layout simulation. If the circuit doesn’t work properly,
fine-tuning of the circuit must be performed by going through the entire process again.
Fig. 7-16: Flow diagram of the flip-flop design in frequency divider.
Design first stage (M1, M2 and M3)to drive M5, M15 and M16
Design second stage (deglitching transistorsM15 and M16); Discharging transistor M14
Design third stage (M4, M5 and M6)to drive M7 and M8
Design fourth stage (M7, M8, M9 and M12)to drive M10 and M11
Design output stage (M10 and M11)to drive M1', M4', M6' and M9');
Discharging transistor M13
Verify circuit operation from 100MHz to1GHz
Circuit operating too slow
Working
Circuit nodes discharging
Reduce M2 and M3;Increase M5, M7 and M8
Reduce M3, M4 and M7;Increase M13 and M14
Layout, run LVS and parasitic extraction to extract theparasitic value, use the parasitic value for final design
Design finished
148
7.5 Detailed Calculations and Experimental Results
Following the design flow in Fig. 7-16, the frequency divider in Fig. 7-12 was
designed using the Chartered Semiconductor Manufacturing (CSM) 0.25µm
technology for GSM applications. The frequency divider was designed to operate
from 100 MHz to 1 GHz.
As mentioned previously, M15 and M16 are deglitching transistors, and M13
and M14 are discharging transistors. All these transistors are designed to have a
minimum aspect ratio to avoid overloading the circuit, which will affect the circuit
performance [92]. The aspect ratios of the PMOS transistors M16 and M13 are set to
0.5µm/0.25µm, while the aspect ratios of the NMOS transistors M15 and M14 are set
to 0.25µm/0.25µm.
Fig. 7-12 shows that the first stage of the flip-flop consists of M1, M2 and M3.
This stage is active when CLK is low. M1 acts as a switch to VDD, which is used to
power the M2-M3 inverter. As a rule of thumb, this inverter must drive the following
parasitic capacitors with a minimum of five times the maximum CLK frequency in
order to switch M5.
5gs5gd14db14gd16gs16gd
15gs15gd3db3gd2db2gd1p
CCCCCC
CCCCCCC
+++++
++++++=
Note that although some of the transistors are actually in the cut off region, the
parasitic capacitance of those transistors is calculated assuming the transistors are in
the saturation region, this will guarantee the operation of circuit at the high speed.
This parasitic capacitance is approximated to be 40fF. Through equation (7.11), it can
be approximated that a switching current of 2.5mA is needed to charge the parasitic
(7.10)
149
capacitor in 32psec to switch M5. This ensures that the flip-flop will operate at the
maximum CLK frequency of 1GHz.
VCtI ×=×
where I is the switching current, t is the charging time, C is the node parasitic
capacitance, and V is the voltage swing at the node. The aspect ratio of M3 is
calculated as follows
µ.µ..
).-(µA/VmA).(
)(VDD-VCµI
LW
tnoxn
25012358
6102310522
2
22
23
≈=
×=
=⎟⎠⎞
⎜⎝⎛
wherer µn, Cox, Vtn are the NMOS transistor mobility, oxide capacitance and threshold
voltage, respectively. M2 is designed for a symmetrical output drive. For simplicity,
assume Vtn = −Vtp
µ.µ.
µ.µ..
µ.µ.
VµAVµA
LW
CµCµ
LW
oxp
oxn
25085
2501272
25012
115310
2
2
32
=⎟⎟⎠
⎞⎜⎜⎝
⎛≈
⎟⎟⎠
⎞⎜⎜⎝
⎛=
⎟⎠⎞
⎜⎝⎛=⎟
⎠⎞
⎜⎝⎛
For high operating frequencies, the aspect ratio of M1 needs to be large to
supply the current to charge-up the inverter. In addition, M1 and M2 are in series, the
delay to charge up the inverter is longer than the delay in a single transistor, so the
aspect ratio of M1 needs to be larger. However, the charge time is not critical in the
(7.11)
(7.12)
(7.13)
150
lower frequency flip-flop B, the size of M1 in flip-flop B is chosen to be half of the
size of M1 in flip-flop A for optimum performance
µ.µ
LW,
µ.µ
LW
BA 2503
2506
11
=⎟⎠⎞
⎜⎝⎛=⎟
⎠⎞
⎜⎝⎛
Fig. 7-12 shows the second stage consisting of the discharging transistor M14,
as well as the deglitching transistors M15 and M16. The aspect ratios of these
transistors are
µ.µ.
LW,
µ.µ.
LW,
µ.µ.
LW
25050
250250
250250
161514
=⎟⎠⎞
⎜⎝⎛=⎟
⎠⎞
⎜⎝⎛=⎟
⎠⎞
⎜⎝⎛
Fig. 7-12 shows the third stage consisting of M4, M5 and M6. This stage is
active when CLK is high. M4 precharges the output of this stage to VDD when CLK
is low. When CLK goes high, M6 supplies power to M5, which turns the voltage at
the node y2 to low. As a rule of thumb, M5 must drive the following parasitic
capacitors with a minimum of five times the maximum CLK frequency in order to
switch M7 and M8.
887744552 gdgsgdgsdbgddbgdp CCCCCCCCC +++++++=
Cp2 is estimated to be 100fF. A switching current of 6.25mA is needed to
charge the parasitic capacitor in 32psec to switch M7 and M8. This ensures that the
flip-flop will operate at the maximum CLK frequency of 1 GHz. Thus the aspect ratio
for M5 is
(7.14)
(7.15)
(7.16)
151
µ.µ.
).-(VµAmA).(
)(VDD-VCµI
LW
tnoxn
25025521
61023102562
2
22
25
≈=
=
=⎟⎠⎞
⎜⎝⎛
For high operating frequencies, the aspect ratios of M4 and M6 need to be
large to supply the current to charge their drain nodes quickly. Since the charging
time is not critical for the lower frequency flip-flop B, the sizes of M4 and M6 can be
smaller. Thus, the size of M4 and M6 are designed to be
µ.µ.
LW,
µ.µ.
LW
BA 250753
25057
44
=⎟⎠⎞
⎜⎝⎛=⎟
⎠⎞
⎜⎝⎛
µ.µ
LW,
µ.µ
LW
BA 2503
2506
66
=⎟⎠⎞
⎜⎝⎛=⎟
⎠⎞
⎜⎝⎛
The fourth stage consists of M7, M8, M9 and M12 to drive M10 and M11.
This stage is active when CLK is high. M9 acts as a switch to GND, which is used to
power the inverter formed by M7 and M8. This inverter must drive the following
parasitic capacitors with a minimum of five times the maximum CLK frequency in
order to switch M10, M11, M2 and M3.
33221111
101088773
gdgsgdgsgdgs
gdgsdbgddbgdp
CCCCC C
CCCCCCC
+++++
++++++=
Cp3 is estimated to be 100fF. A switching current of 6.25mA is needed to
charge the parasitic capacitor in 32psec to ensure that the flip-flop will operate at the
maximum CLK frequency of 1 GHz. For the lower frequency flip-flop B, about
(7.17)
(7.18)
(7.20)
(7.19)
152
3.125mA is needed to charge the parasitic capacitor in about 64psec. Thus the aspect
ratio for M8 is
µm.µm.
).-)(µA/V(mA).(
)(VDD-VCµI
LW
tnoxnA
25025521
61023102562
2
22
28
≈=
=
=⎟⎠⎞
⎜⎝⎛
and µ.µ.
LW
B 25072
8
=⎟⎠⎞
⎜⎝⎛
Since M7 is designed for a symmetrical output drive. The aspect ratio of M7 is
thus
µ.µ.
µ.µ..
µ.µ.
VµAVµA
LW
CµCµ
LW
oxp
oxn
A
250214
25025572
250255
115310
2
2
87
=⎟⎟⎠
⎞⎜⎜⎝
⎛≈
⎟⎟⎠
⎞⎜⎜⎝
⎛=
⎟⎠⎞
⎜⎝⎛=⎟
⎠⎞
⎜⎝⎛
and µ.µ.
LW
B 25027
7
=⎟⎠⎞
⎜⎝⎛
For high operating frequencies, the aspect ratios of M9 and M12 need to be
large to supply the current to charge their drain nodes quickly. Thus, the sizes of M9
and M12 are designed to be
µ.µ.
LW,
µ.µ.
LW
BA 25063
25027
99
=⎟⎠⎞
⎜⎝⎛=⎟
⎠⎞
⎜⎝⎛
µ.µ.
LW,
µ.µ.
LW
BA 25063
25027
1212
=⎟⎠⎞
⎜⎝⎛=⎟
⎠⎞
⎜⎝⎛
(7.21)
(7.23)
(7.22)
153
The output stage consists of M13 and an inverter formed by M10 and M11.
This inverter must drive the following parasitic capacitors with a minimum of five
times the maximum CLK frequency in order to switch M1, M4, M6 and M9.
996644
11111110104
gdgsgdgsgdgs
gdgsdbgddbgdp
CCCCCC
CCCCCCC
+++++
++++++=
Cp4 is estimated to be 100fF. A switching current of 6.25mA is needed to
charge the parasitic capacitor in 32psec to ensure that the flip-flop will operate at the
maximum CLK frequency of 1GHz. Thus the aspect ratio of M11 is
µ.µ.
).-)(µA/V(mA).(
)(VDD-VCµI
LW
tnoxn
25025521
61023102562
2
22
211
≈=
=
=⎟⎠⎞
⎜⎝⎛
Since M10 is designed for a symmetrical output drive. The aspect ratio of M10
is thus
µ.µ.
µ.µ..
µ.µ.
VµAVµA
LW
CµCµ
LW
oxp
oxn
250214
25025572
250255
115310
2
2
1110
=⎟⎟⎠
⎞⎜⎜⎝
⎛≈
⎟⎟⎠
⎞⎜⎜⎝
⎛=
⎟⎠⎞
⎜⎝⎛=⎟
⎠⎞
⎜⎝⎛
While the aspect ratio of the discharging transistor M13 is
µ.µ.
LW
25050
13
=⎟⎠⎞
⎜⎝⎛
(7.24)
(7.25)
(7.26)
(7.27)
154
Table 7-2 shows the transistor sizes of the frequency divider in Fig. 7-12.
Following the design flow in Fig. 7-16, the actual transistor sizes for the frequency
divider that was fabricated in the Chartered Semiconductor Manufacturing (CSM)
0.25µm technology for GSM applications are shown in Table 7-3.
Table 7-2: Transistor sizes of the frequency divider.
(W/L)1 (W/L)2 (W/L)3 (W/L)4
A 6µ/0.25µ 5.8µ/0.25µ 2.1µ/0.25µ 7.5µ/0.25µ
B 3µ/0.25µ 5.8µ/0.25µ 2.1µ/0.25µ 3.75µ/0.25µ
(W/L)5 (W/L)6 (W/L)7 (W/L)8
A 5.25µ/0.25µ 6µ/0.25µ 14.2µ/0.25µ 5.25µ/0.25µ
B 5.25µ/0.25µ 3µ/0.25µ 7.2µ/0.25µ 2.7µ/0.25µ
(W/L)9 (W/L)10 (W/L)11 (W/L)12
A 7.2µ/0.25µ 14.2µ/0.25µ 5.25µ/0.25µ 7.2µ/0.25µ
B 3.6µ/0.25µ 14.2µ/0.25µ 5.25µ/0.25µ 3.6µ/0.25µ
(W/L)13 (W/L)14 (W/L)15 (W/L)16
A 0.5µ/0.25µ 0.25µ/0.25µ 0.25µ/0.25µ 0.5µ/0.25µ
B 0.5µ/0.25µ 0.25µ/0.25µ 0.25µ/0.25µ 0.5µ/0.25µ
155
Table 7-3: Actual transistor sizes of the frequency divider.
(W/L)1 (W/L)2 (W/L)3 (W/L)4
A 7.5µ/0.25µ 6.5µ/0.25µ 2.25µ/0.25µ 6.25µ/0.25µ
B 3.75µ/0.25µ 6.5µ/0.25µ 2.25µ/0.25µ 3.12µ/0.25µ
(W/L)5 (W/L)6 (W/L)7 (W/L)8
A 5.75µ/0.25µ 6.25µ/0.25µ 8µ/0.25µ 5µ/0.25µ
B 5.75µ/0.25µ 3.125µ/0.25µ 4µ/0.25µ 2.5µ/0.25µ
(W/L)9 (W/L)10 (W/L)11 (W/L)12
A 7.5µ/0.25µ 10µ/0.25µ 5µ/0.25µ 6.25µ/0.25µ
B 3.75µ/0.25µ 10µ/0.25µ 5µ/0.25µ 3.12µ/0.25µ
(W/L)13 (W/L)14 (W/L)15 (W/L)16
A 1µ/0.25µ 0.5µ/0.25µ 0.5µ/0.25µ 1µ/0.25µ
B 1µ/0.25µ 0.5µ/0.25µ 0.5µ/0.25µ 1µ/0.25µ
Fig. 7-17 shows the microphotograph of the frequency divider, which
performs a divide-by-8 operation. Measured results of the frequency divider are
shown in Fig. 7-18.
156
Fig. 7-17: Microphotograph of the frequency divider for a divide-by-8 operation.
157
(a)
(b)
Fig. 7-18: Experimental results of the frequency divider for a divide-by-8 operation (a) 1 GHz input signal; (b) 125 MHz output signal.
158
7.6 Summary
In this chapter, a review of various spur reduction techniques was presented.
The design of high-speed frequency dividers was discussed. The measured results for
the implemented frequency divider were shown.
In Chapter 8, a novel spur reduction fractional-N frequency divider with a
frequency range, which is 3.5 times larger than that of a conventional fractional-N
divider, will be presented. In Chapter 9, a novel technique that can fully suppress the
fractional spur for fractional-N frequency synthesizer will be presented.
159
CHAPTER 8
Fully Integrated CMOS Fractional-N Frequency
Divider for Wide-Band Mobile Applications
with Spur Reduction
The fractional-N frequency divider has become increasingly popular in RF
applications as it allows PLL Synthesizers to have a frequency resolution finer than
the reference frequency. However, there are two main disadvantages of a fractional-N
divider, namely, fractional spur generation and frequency range limitation. A
fractional-N divider generates fractional spur due to the fixed pattern of the dual-
modulus divider [7]. The frequency range of a fractional-N divider is equal to its
reference frequency. This limits its usefulness especially in wide-band applications.
A dual-band PLL synthesizer for personal communications services (PCS)-
and cellular- code division multiple access (CDMA) systems is demonstrated in [7].
This circuit uses a charge-averaging charge pump to solve the fractional spur problem.
However, this approach is only suitable for a small number of division ratios as it is
limited by the complexity of the charge pump. As the frequency range of a dual-
modulus fractional-N frequency synthesizer is equal to the reference frequency, e.g.
19.8 MHz as in [7], the operating band may not be fully covered.
This chapter describes a new technique for reducing the fractional spur while
providing a wide frequency range. The width of the maximum phase error’s pulse
[100] in the new design is less than a quarter of that of the conventional one. This is
achieved through the introduction of a new division ratio (N + 1/4) in the divider. This
160
frequency divider has a frequency range of 3.5 times larger than that of the
conventional fractional-N divider, as its division modulus ranges from (N-1.75) to
(N+1.75) while a conventional fractional-N divider has only a division modulus of N
to (N+1). This technique also reduces the magnitude of the fractional spur to one
quarter of the usual value.
In the modern transceiver design, the quadrature VCO is often needed to
generate the quadrature signals for the LO inputs of either image-reject mixers [62] or
frequency down converters with I/Q outputs. For multiple standard applications, the
VCO needs to have a wide tuning range in order to cover the entire range of operation
frequency. The quadrature VCOs reported in [66] and [61] have a wide tuning range
of 18.5% and 24%, respectively. The results show that the quadrature VCO is a good
candidate for multiple standard applications. As the quadrature VCO is becoming
more popular in modern communication systems [53],[61],[64]-[66],[70]-[73], these
quadrature outputs are used in this new frequency synthesizer.
8.1 Frequency Divider Topology
In a fractional-N frequency divider, a dual-modulus divider, divide-by-(N/N+1)
is used. The fractional division is obtained by periodically changing the division ratio.
To achieve a divide-by-4.125 operation, seven divide-by-4 operations followed by
one divide-by-5 operation are required. As shown in Fig. 8-1, each of the first seven
cycles of the divided signal is slightly shorter than the reference period. Consequently,
the phase error between the reference and the feedback signal grows in every period
of F(ref) till it returns to zero when the divide-by-5 operation occurs. Thus, the phase
detector produces progressively wider error pulses, creating a ramp at the filter output
of the PLL.
161
Here, it can be concluded that if the VCO output is to be equal to
(N + α)F(ref), (e.g., α = 1/8 and N = 4 in Fig. 8-1), the output of the low pass filter
(LPF) will be a repetitive ramp waveform with a period of 1/(αF(ref)). If the loop is
closed, such a waveform would modulate the VCO, creating sidebands at αF(ref),
2αF(ref), etc. with respect to the center frequency. Such sidebands are called
fractional spur. For example, for α = 1/8, the output of the LPF will be a periodic
ramp waveform with a period of 8/F(ref), creating sidebands at 0.125F(ref),
0.25F(ref), etc. with respect to the center frequency.
Fig. 8-1: Effect of unequal instantaneous frequencies.
The new fractional-N frequency divider with (N + 1/4) modulus is shown in
Fig. 8-2. The operation of the (N + 1/4) division fractional-N frequency divider will
162
be discussed in Section 8.3. The inputs of the frequency divider are from a quadrature
VCO. With inputs from the quadrature VCO, a new division ratio of (N + 1/4) can be
achieved, as the phase difference between the consecutive outputs of the quadrature
VCO is 90°. The new divider reduces the generation of fractional spur by the
introduction of a new division ratio of (N + 1/4).
Fig. 8-2: Fractional-N frequency divider with a divide-by-(N + 1/4) operation.
In Fig. 8-3, to achieve a divide-by-4.125 operation, one divide-by-4 operation
is made for each one divide-by-4.25 operation, so the total time for one correct
comparison is 2/F(ref). This effectively reduces the period of the periodic ramp at the
output of the LPF from 8/F(ref) to 2/F(ref). Thus, the sidebands created now are at
0.5F(ref), F(ref), etc. with respect to the center frequency, which are 4 times the
distance as in the case of a conventional divider. The magnitude of the sidebands is
163
now a quarter of the magnitude of that in the conventional divider as shown in
Fig. 8-1. The reason is that the time to accumulate the charge at the output of the LPF
is now a quarter of that of a conventional divider.
Fig. 8-3: Effect of the implementation of a divide-by-(N + 1/4) operation.
To further illustrate the effect of the new division ratio, simulations to achieve
the division ratio of 9.05 were done for a PLL frequency synthesizer as shown in Fig.
8-4. The output frequency F(vco) and the reference frequency F(ref) of the PLL
frequency were 859.75 MHz and 95 MHz respectively.
164
Fig. 8-4: Block diagram of the simulation setup of a PLL frequency synthesizer using conventional frequency divider and novel frequency divider.
In order to achieve a division ratio of 9.05, for the conventional frequency
divider, 19 divide-by-9 operations are needed before one divide-by-10 operation. For
the new divider, 4 divide-by-9 operations are required before one divide-by-9.25
operation. In Fig. 8-5, it is observed that the fractional spur of the new fractional
divider is much smaller than that of the conventional divider and 4 times further from
the carrier as compared to that of the conventional divider.
165
(a)
(b) Fig. 8-5: Simulation Results of (a) the conventional frequency divider;
(b) the new frequency divider.
166
8.2 Circuit Description
8.2.1 Modulus Control
Fig. 8-6 shows the modulus control circuitry. The 3-bit division modulus
control word, Mode, determines the modulus of a division by generating 1, or 2 or 4
pulses depending on the settings of the control bits Mode1, Mode2 and Mode3. For
example, when Mode is 100, where Mode3 is high, while Mode1 and Mode2 are low,
four pulses will be generated at the output Next [94]. The inputs F(in), /2, /4 and /8
correspond to the outputs of the phase select, and the three divide-by-2 flip-flop
outputs respectively as shown in Fig. 8-2.
Fig. 8-6: Modulus control circuitry.
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8.2.2 Phase Control Circuitry
The phase control circuitry is needed to convert the signal Next generated
from the modulus control circuitry to the 3-bit Control Signal in the phase select
circuitry. The 3-bit control signal Ctrl is generated by the two divide-by-2 flip-flops as
shown in Fig. 8-7.
Fig. 8-7: Phase control circuitry.
8.2.3 Phase Select
A phase select circuitry is needed to switch the inputs from One to Two, Two
to Three, Three to Four and then back from Four to One, whenever the Ctrl signal
changes. The multiplexer in the phase select circuitry is implemented using pass
transistors as shown in Fig. 8-8. In this design, Control 1 and Control 2 are the same
signal, so they can be combined into a single bit. When Ctrl is equal to 11 (Control
1/2 Control 3), the output of the phase select circuitry F2 is connected to One. If Ctrl
is 10, F2 is connected to Two. If Ctrl is 01, F2 is connected to Three. Lastly, when
Ctrl is 00, F2 is connected to Four.
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Fig. 8-8: Phase select circuitry.
8.3 Circuit Operation
For forward propagation division, the new divider operates as follows. As
shown in Fig. 8-2, the input signals namely, One, Two, Three and Four, are fed to the
phase select circuitry. When the 3-bit signal Mode is 000, the phase control block is
disabled and its output signal F(in) is not changed. This means that the output of the
multiplexer will be taken from the same input as the previous clock. Hence, F(div) is
8 times smaller than the input frequency F(in). Depending on the required modulus,
the control signal Ctrl will change in such a way that the division control block will
connect F(in) to the signal that is 90° phase shifted with respect to the present signal,
e.g. from 0° to 90° or 90° to 180°. For example, for a division of 8.25, Mode is equal
to 001. Hence, one pulse will be generated at Next. If F(in) is initially connected to
One, after Ctrl changes, a connection will be made to Two. Hence, a division of 8.25
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is achieved as shown in Fig.8-9, where the input frequency in this simulation is at
2 GHz.
Fig. 8-9: Divide-by-8.25 operation at 2 GHz.
In this design, all the division modulus from 8 to 9.75 for N = 8 can be
achieved. In Fig. 8-10, a division of 9.75 was simulated at 1 GHz. In order to achieve
a divide-by-9.75 operation, Mode must be set to 111. Thus, seven pulses will be
generated at Next. When F(in) is initially connected to One, after Ctrl changes, a
connection will be made to Two. As there are seven pulses, the Ctrl will change seven
times in one divide-by-9.75 period. In each sequence, F(ref) will consecutively
connected to One, Two, Three, Four, then go back to One, Two, Three and lastly to
Four.
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Fig. 8-10: Divide-by-9.75 operation at 1 GHz.
Table 8-1: Forward and backward sequences of phase select circuitry.
Input Control 1 and 2 Control 3 Forward Backward
1st Input of 1st Mux 1 1 Four One
2nd Input of 1st Mux 0 1 One Four
1st Input of 2nd Mux 1 0 Two Three
2nd Input of 2nd Mux 0 0 Three Two
The backward propagate division is implemented by using the sequence of the
forward and backward propagation of the phase select circuitry as shown in Table 8-1.
Essentially, for backward propagation, the signals for control 1 and 2 are interchanged.
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Hence, the range of the division ratio for the prescaler is increased by two times,
which ranges from (N − 1.75) = 6.25 to (N + 1.75) = 9.75 for N=8.
8.4 Experimental Results
The frequency divider of Fig. 8-2 was designed and fabricated using the
CMOS 0.25µm process. A 1.2 GHz frequency quadrature VCO was designed to
generate the quadrature signals into the frequency divider. The quadrature VCO was
designed using the parasitic-compensated quadrature VCO technique discussed in
Chapter 4. The active chip area is 1200µm x 1600µm. The divider and the quadrature
VCO consume 9mW at 2V supply, where 3mW is for the frequency divider and 6mW
is for the quadrature VCO. Fig. 8-11 shows a microphotograph of the frequency
divider with the quadrature VCO.
FrequencyDivider
QuadratureVCO
Fig. 8-11: Microphotograph of the frequency divider and 1.2 GHz quadrature VCO.
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Fig. 8-12 shows the power spectrum of the VCO output at 1.2 GHz. A divide-
by-9.75 operation is implemented through forward propagation of the phase select
circuitry, which results in an output frequency of 1.2 GHz/9.75 = 123.1 MHz. A
divide-by-7.75 operation is implemented through backward propagation of the phase
select circuitry, which results in an output frequency of 1.2 GHz/7.75 = 154.8 MHz.
Fig. 8-13 and Fig. 8-14 show the power spectrums of the divider output at 123.1 MHz
and 154.8 MHz, respectively.
Fig. 8-12: Power spectrum of the VCO output at 1.2 GHz.
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Fig. 8-13: Power spectrum of the frequency divider output at 123.1 MHz.
Fig. 8-14: Power spectrum of the frequency divider output at 154.8 MHz.
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8.5 Summary
A new multiple modulus (N + 1/4) fractional-N frequency divider was
presented. This frequency divider provides a new division of (N + 1/4), which reduces
the generation of fractional spur. In addition, it has a large range of multiple modulus
division from (N - 1.75) to (N + 1.75), as shown in the above example it ranges from
6.25 to 9.75 for N = 8. This will enable the frequency divider to support multiple
standard applications for fixed and mobile radios that operate over a wide range of
frequency. This work was published in [114].
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CHAPTER 9
A New Spur Reduction Fractional-N
Frequency Divider
In this chapter, another method to overcome the fractional spur generated by
the fractional-N technique is introduced. In the previous chapter, a spur reduction
technique, which greatly reduced the magnitude of the fractional spur and at the same
time increased the division modulus range, has been introduced. In comparison, this
method eliminates the fractional spur generated. Furthermore, it has the advantage of
simplicity where it needs only two extra 2-to-1 multiplexers.
9.1 Circuit Description
In a conventional fractional-N frequency divider, a dual-modulus divider,
divide-by-(N/N+1), is used. The fractional division is obtained by periodically
changing the division value. To achieve a divide-by-461 operation, five divide-by-4
operations are done before one divide-by-5 operation. The carry of the accumulator in
Fig. 9-1 is in the sequence of 000001000001…, where a division by (N + 1) is
corresponding to “1”.
As shown in Fig. 9-2, each of the first five cycles of the divided signal is
slightly shorter than the reference period. Consequently, the phase difference between
the reference and the feedback signal grows in every period of reference frequency
F(ref) till it returns to zero when the divide-by-5 operation occurs. Thus, the phase
detector produces progressively wider pulses, creating a ramp waveform at the output
of the loop filter.
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Fig. 9-1: A conventional fractional-N frequency divider.
Fig. 9-2: Effect of unequal instantaneous frequencies in a fractional-N synthesizer.
Phase Detector Output
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Here, it can be concluded that if the VCO output frequency is to be equal to
(N + α)F(ref), (e.g., α = 1/6 and N = 4 in Fig. 9-2), the output of the loop filter (LF)
will be a repetitive ramp waveform with a period 1/(αF(ref)).
If the loop was closed, such a waveform would modulate the VCO, creating
sidebands at αF(ref), 2αF(ref), etc. with respect to the center frequency. Such
sidebands are called fractional spur.
Fig. 9-3 shows the proposed spur reduction frequency divider. A 2-to-1
multiplexer is used to select between F(ref) and ground (Gnd), and another
multiplexer selects between the frequency divider output F(div) and Gnd. When
Change is “0”, both the outputs of the multiplexers are grounded. When Change is “1”,
F(ref) and F(div) will be selected by each of the respective multiplexer. The
multiplexers are implemented using pass transistors.
For a fractional-N divider, in order to achieve a divide-by-(N + s/q) operation,
where s and q are integers, (q - s) divide-by-N operations and s divide-by-(N+1)
operations need to be performed. The control signal Change will be set to “1”
immediately after q falling edges of F(ref) are accumulated by the control circuitry.
Hence, at every (r × q) falling edges of F(ref), Change will be set to “1”, where r is an
integer. At the first and (q+1)th falling edges of F(div), Change will be set to “0”.
Thus, at every (r × q) + 1 falling edges of F(div), Change is equal to “0”.
For example, if a division of (9 + 1/20) is required, where N = 9, s = 1 and
q = 20, then, at the 20th, 40th, 60th…. and every multiple of 20th of the falling edges
of F(ref), Change will be set to “1”. While in the 1st, 21st, 41st, 61st…. and every
multiple of (20 × r + 1)st of falling edges of F(div), Change will be set to “0”.
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The signal Carry controls the modulus of the frequency divider. When Carry
is “1”, a divide-by-(N + 1) operation is performed, while a divide-by-N operation is
performed when Carry is “0”.
If Change is initially “0”, F2 (ref) and phase detector output F(PD) are both
grounded, which gives the phase detector a zero output. In order to achieve a divide-
by-(N+2/5) operation, two divide-by-(N + 1) operations are done after every three
divide-by-N operations. So, the carry of the accumulator is in the sequence of
0001100011…, where a division by N+1 corresponds to a “1”. Hence, when the
carry of the accumulator is in the sequence of 0001100011…, Change will have the
sequence of 0000100001….
Fig. 9-3: The proposed fractional spur reduction frequency divider.
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Fig. 9-4 compares the operation results of the two dividers for the case of
N = 2, s = 1 and q = 2. The phase error in (a) has now been eliminated by the
proposed spur reduction technique in (b). This is because at the transient period of the
new fractional-N divider, there is no comparison done between F(ref) and F(div), thus
minimizing the phase error. Only at the last pulse of the five output cycles, F(ref) is
compared to F(div).
(a)
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(b)
Fig. 9-4: Phase error generated in the process to achieve a divide-by-(2 + 1/2) operation (a) without spur reduction; (b) with spur reduction technique.
9.2 Simulation Results
A closed-loop simulation has been carried out to evaluate the performance of
the new spur reduction technique. The setup of the simulation is shown in Fig. 9-5.
The output tuning range is centered at 855 MHz. Here, a divide-by-(9 + 1/20)
operation is to be performed. In order to achieve a fast settling time, the signal
Change is set to “1” for the initial 105µs, thus disabling the function of the
multiplexers for that period. Hence, it is at the steady state that both multiplexers are
181
operational. Consequently, the settling time of the phase lock loop will not be affected
by the introduction of the extra circuitry (multiplexers).
Fig. 9-6 shows the simulation results of conventional PLL, while Fig. 9-7
shows the simulation results of the PLL with the spur reduction technique
implemented. Fractional spur is shown as sidebands in Fig 9-6. While in Fig. 9-7, all
fractional spur is eliminated.
Fig. 9-5: Block diagram for the simulation of the new fractional-N technique.
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Fig. 9-6: Simulation results of a conventional fractional-N PLL.
Fig. 9-7: Simulation results of the new fractional-N PLL with spur reduction circuit implemented.
Frequency (MHz)
F(ou
t) in
dB
m
m1 freq=859.3 MHz dB(VCO)=-6.436
No fractional spur
F(ou
t) in
dB
m
Frequency (MHz)
m2 freq=854.5MHz dB(VCO)=-62.988
m1 freq=859.3MHz dB(VCO)=-6.838
Fractional spur
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9.3 Summary
A new spur reduction frequency divider has been proposed. The advantage of
this technique besides its ability to eliminate all fractional spur is its simplicity
requiring only two extra 2-to-1 multiplexers. The simulation was performed using the
CSM 0.25µm technology, and the HP Advanced Design System. The work was
published in [109].
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CHAPTER 10
Conclusions & Recommendations
10.1 Conclusions
This thesis describes a wide range of techniques employed in phase-locked
loop. The investigation covers mainly two building blocks of the phase-locked loop,
which are the VCO and the frequency divider.
In Chapter 2, the importance of optimizing the loop bandwidth in order to
achieve the best phase noise performance for a phase-locked loop was shown. The
impact of the noise generated from the resistor in the loop filter was highlighted. In
Chapter 3, an overview of the VCO design was presented, and the design
considerations for an LC VCO were shown. In Chapter 4, a novel parasitic-
compensated quadrature LC oscillator was presented.
A fabricated 2.63 GHz quadrature CMOS LC oscillator with a phase noise of
–112.3 dBc/Hz at 600 kHz offset was demonstrated, with a power consumption of
7.5mW at 1.5V supply using an on-chip spiral inductor.
A novel RF CMOS low-phase-noise LC oscillator using the memory reduction
tail transistor was presented in Chapter 5. A simulated phase noise of -127.6 dBc/Hz
at 600 kHz offset for an oscillation frequency of 1.88 GHz was achieved with a tank
quality factor of 9. An example of a VCO that meets the system specifications of the
WCDMA/CDMA2000 has been achieved through this novel topology. In Chapter 6,
the design of the novel 102 GHz SiGe MOSFETs LC oscillator was presented. The
VCO has an oscillation frequency of 102 GHz with a tuning range of 3.4 GHz. In this
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tuning range, the phase noise was –106 dBc/Hz to –107.7 dBc/Hz at 1 MHz offset
frequency. Besides being the VCO with the highest frequency reported to date, this
novel VCO also has the best figure of merit (FOM) of 192.9 dB.
In Chapter 7, a literature review of the frequency dividers was given and a
design method was outlined for the implementation of high speed flip-flop, the basic
building block of frequency dividers. In Chapter 8, the design of a novel fully
integrated CMOS fractional-N frequency divider for wide-band mobile applications
with spur reduction technique was described. The frequency divider was fabricated
and experimentally verified. A novel spur reduction fractional-N frequency divider
was proposed in Chapter 9. Simulation results showed that the fractional spur was
fully suppressed with the implementation of this technique.
On-wafer measurements of the above circuits were carried out using the
HP8510C Network Analyzer (as shown in Fig. 10-1) and Cascade Microtech
Coplanar Ground-Signal Ground (GSG) probes. The HP Spectrum Analyzer 8593E
with the frequency range from 9 kHz to 26.5 GHz was connected to the RF probe to
examine the spectrums of the VCO output.
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Fig. 10-1: The photo of the network analyzer HP8510C.
10.2 Recommendations
As shown in Chapter 2, the phase noise performance of a phase-locked loop
depends greatly on the phase noise performance of the VCO. With a proper design,
noise from the active devices in the VCO can be minimized. Indeed, the active
devices are present only to replenish the lost energy in the resonant tank. They cannot
improve the overall Q of the circuit. It has been shown that a substantial improvement
in phase noise can be achieved by implementing the resonator tank with a high Q [61].
In [61],[104], it was shown that the Q of the inductor could reach about 100 in theory
for gold bondwire inductor. However, this method is costly and it is susceptible to the
effect of the contact resistance and other parasitic, which will reduce the Q
significantly. Another method for improving the Q of the resonator tank is through
crystal-like inductance-capacitance tank [105]. However, this does not help to
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improve the Q due to the requirement that all the inductors must be integrated on-chip.
More work has to be done in order to provide a resonator tank with high Q that can be
easily integrated.
The frequency divider is a critical block in a phase-locked loop frequency
synthesizer as well as in a clock and data recovery circuitry. One of the most
challenging requirements for a frequency divider is its speed of operation. The D-flip-
flop (FF) is commonly used as a frequency divider due to its high speed [116]-[118].
To date, some of the high speed FFs that have been developed, e.g., 40 Gb/s delayed
flip-flop (D-FF) with GaAs HBT [116], 25 Gb/s D-FF with Silicon bipolar [117],
24 Gb/s Super-Dynamic FF with GaAs MESFET [115], and 13.4 GHz Master-Slave
FF with MOSFET [1]. A conventional Master-Slave D-FF can operate at the speed of
one-fifth to one-fourth of the transistor ft for FET devices and one-fourth to one-third
of the transistor fmax for bipolar devices [118],[119]. For high speed applications, e.g.,
the 40 Gb/s Optical Communication – 768 (OC-768) standards, transistors with an ft
of 200 GHz are needed for a frequency divider circuit employing FET devices. Hence,
circuit innovations are urgently needed to make further speed improvements. This
presents a challenge to an RFIC circuit designer.
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Author’s Publications
C. C. Boon, M. A. Do, K. S. Yeo, J. G. Ma, and R. Y. Zhao, “Parasitic-