Novel device technologies - ziyang.eecs.umich.edu

Novel device technologies

• Slides largely based on presentation Li Shang and I gave at Tsinghua University

• Some of the images might be copyrighted by others: don't charge or distribute

Overview

• Historic overview of technology scaling

• CMOS: current status and challenges

• Nanotechnologies: An introduction• Nano circuit and architecture design

– Carbon nanotube technology– Single electron tunneling transistor

• Open questions

Evolution of electronics0

1

1850 1875 1900 1925 1950 1975 2000 2025

Mechanical

Electro-Mechanical

Electronic-VT

Bipolar

NMOS

CMOS……. ?

The first computer

Babbage difference Engine (1822)– 4000 components

– Three tons

– 31 digits

• Pros – automatic• Cons – slow, expensive, not

flexible

The first electronic computer

• Electrical numerical integrator and computer ENIAC (1946)– 18,000 vacuum tubes– 30 tons– 100,000 calculations per

second

• Pro – faster, flexible• Con – too big, not reliable

Semiconductors

The first transistor

The first integrated circuit 4004 Pentium® 4

1.E-21

1.E-18

1.E-15

1.E-12

1.E-09

1.E-06

1.E-03

1.E+00

1940 1960 1980 2000 2020

Cu

bic

Met

er

Vacuum tube

Transistor

NMOS

CMOS

Benefits of scaling

1.E-11

1.E-09

1.E-07

1.E-05

1.E-03

1.E-01

1.E+01

1940 1960 1980 2000 2020

Del

ay (

Sec

) Vacuum tube

Transistor

NMOS

CMOS

1.E-161.E-141.E-121.E-101.E-081.E-061.E-041.E-021.E+00

1940 1960 1980 2000 2020

Jou

les

Vacuum tube

Transistor

NMOS

CMOS

1.E-061.E-051.E-041.E-031.E-021.E-011.E+001.E+011.E+02

1940 1960 1980 2000 2020

Co

st (

$)

Vacuum tube

Transistor

NMOS

CMOS

ENIAC-on-a-chip

• 40 mm2

– 174,000 transistors

• 0.5 W• 20 MHz

Technology outlook

Medium High Very HighVariability

Energy scaling will slow down>0.5>0.5>0.35Energy/Logic Op scaling

0.5 to 1 layer per generation8-97-86-7Metal Layers

11111111RC Delay

Reduce slowly towards 2-2.5<3~3ILD (K)

Low Probability High ProbabilityAlternate, 3G etc

128

11

2016

High Probability Low ProbabilityBulk Planar CMOS

Delay scaling will slow down>0.7~0.70.7Delay = CV/I scaling

256643216842Integration Capacity (BT)

8162232456590Technology Node (nm)

2018201420122010200820062004High Volume Manufacturing

Si Substrate

Metal Gate

High-kTri-Gate

S

G

D

III-V

S

Carbon Nanotube FET

50 nm

35 nm

30 nm

SiGe S/D

Strained Silicon

SiGe S/D

Strained Silicon

90 nm65 nm

45 nm32 nm

20042006

20082010

2012+

Technology Generation

20 nm 10 nm

5 nm5 nm

5 nm

Nanowire

Manufacturing Development Research

CMOS research continues…

Nanotechnology outlook

• Why CMOS technology?– Performance

• Gain, low noise– Area

• Massive integration– Power– Reliability– Fabrication difficulty & cost

• Status & challenges– 65 nm Intel, IBM, TSMC, etc.– Power challenge

• Energy, thermal issues

– Fabrication cost• Photolithograph masks are expensive

– Reliability• Soft errors • Electromigration, dielectric breakdown, etc.

– Process variation

• Why nanotechnology?– To continue technology

scaling to further scale integration, reduce cost, improve performance, and minimize power consumption

• Candidates– Carbon nanotube– Nanowire– Single electron device

Emerging nano devices

Carbon nanotube

Forms of carbon…

Carbon atom can form several distinct types of valence bonds….

A bit of history….

Edison's original carbon-filament lamp

US Patent 223898

1880

1978

F/A-18 HornetThe first aircraft with carbon fiber wings

1985

Discovery of Fullerenes(Smalley)

Nanotubes discovered at NEC, by Japanese researcher

Dr. Sumio Iijima

1991

Carbon nanotube transistor based logic-performing ICs (IBM)

2001

Carbon nanotubes in interconnet applications

(Kreupl, Infineon)

2002

CNT Vias

What are carbon nanotubes?

Graphene Single-WalledNanotube(SWCNT)

Multi-WalledNanotube(MWCNT)

Courtesy: F. Kreupl, Infineon

Eg ~1/d: Thick (>5nm) MWCNTs have a vanishing band gap at 300K, hence metallic…..

What are carbon nanotubes?

Armchair Nanotube (metallic) Zigzag Nanotube (semi-conducting)

SWCNTs

Various roll-ups possible depending on chirality

Chiral nanotube

Properties

• Carbon nanotube – Single-wall or multi-wall– Diameter: 0.4-100nm– Length: up to millimeters– Ballistic transport– Excellent thermal

conductivity– Very high current density– High chemical stability– Robust to environment– Tensile strength: 45 TPa! (high

strength steel ~ 2TPa)– Temperature Stability: up to

2800 oC in vacuum and up to 700 oC in air

3855800

Hone, et al., Phys. Rev.

B, 1999

Thermal conductivity

(W/mK)

40>1000

McEuen, et al., Trans.

Nano., 2002

Mean free path (nm)

@ room temp

<1x107>1x109

Wei, et al., APL, 2001

Max current density (A/cm2)

CuCNT

NRAM

• Non-volatile nanotube random-access memory (NRAM)– Mechanically bent or not: determines bistable on/off states– Fully CMOS-compatible manufacturing process– Prototype chip: 10 Gbit NRAM

– Will be ready for the market in the near future

Source: Nantero

NRAM

• Properties of NRAM– Non-volatile– Similar speed to SRAM

– Similar density to DRAM– Chemically and mechanically stable

Single-electron tunneling transistor (SET)

SET structure

SET background

• Device structure– A nanometer-scale conductive island embedded in an

insulating material– Electrons travel between the island and electrodes

through tunneling junctions

S

CG :gate capacitance CD :drain tunnel junction capacitanceCG2 :optional 2 nd gate capacitance RS :source tunnel junction resistanceCS :source tunnel junction capacitance R D :drain tunnel junction resistance

G

D

G2

CG

CG2CS,RS CD,RD

Source

drain

Gate (G)island

i(t)

optional 2nd gate (G2)

tunneljunction

(S) (D)

SET background

• Coulomb blockade effect– Electrostatic charge: e2/C– Island has a minimal-energy number of electrons

– When integer, tunneling in and out blocked– When ½ integer, tunneling permitted

– Can tune with applied gate voltage, VG

SET characteristics

• Periodic I-V characteristics• This is not due to de Broglie wavelength!

SET characteristics

• Ultra-low power consumption• Strong temperature dependency

• Fabrication challenge• Reliability concern

– Random background charge noise

• Low drive strength

• Low circuit gain

e2 /C≥K BT

R≥h/e2≈26K

g=CG/ C SC D

ICE-FLEX: hybrid SET/CMOS reconfigurable architecture design

• Design space– Power consumption– Performance– Fabrication challenge– Room-temperature operation– Reliability concerns

SET configuration memory

SET local interconnect Hybrid SET/CMOS globalinterconnect

Majority voting logic

SET multi-gate lookup table

SET input switch fabric SET registers

• Reconfigurable Architecture– SET logic block– SET/CMOS interconnect– SET configuration memory– SET/CMOS majority voting logic

SET reconfigurable logic

• SET multi-gate look-up table– Multi-gate structure– Strong temperature

dependence

• SET configuration memory– Phase shifting

controlled by Coulomb charge

SET configuration cache

Curre

nt configura

tion mem

ory

VCG

charge

VGVoutD SIDS

VG

VCG

VGVoutD SIDS

VG

VGStore 1

Store 0

SET configuration cache

Configuration setsset k-1 set0set1

Config. Bit0

Config. Bitm-1

config

ura

tion

m-to-1 multi-gate multiplexer SET tree

Vdd

VG2

Vss

-VG2

Config. Bit0

Config. Bit1

Config. Bitmc-1

s0 s1 snc

s0 s1 snc

s0 s1 snc

mc-to-1 multi-gate SET multiplexer

SET interconnect

• SET local interconnect– Static power dominant

• Hybrid SET/CMOS global interconnect– Dynamic power dominant

VG2

-VG2

VG2

-VG2

HLB input

SINV1 SINV2CINV1 CINV2

Inter-HLB metal wire

Majority voting & arithmetic logic

• SET MVL– Efficient implementation– Suffer from random

background charge effect itself

• SET arithmetic logic– Threshold logic– Non-unate functions

VG2

-VG2

Out

Vss

Vdd

IN1

INk-1

IN1

INk-1

Characterization

Characterization

Characterization

• Ultra-low power sensor applications– AVR (4 MHz) can run for 9.7 years on one AA battery– Scavenging indoor solar energy is sufficient to power

AVR at 1.6 MHz

• Power-efficient high-performance computing– LEON2 SPARC: 1.6 Terra IPS at 100 W power

budget, 16 Terra IPS under 1 kW power budget

Open questions

• Will nanotechnologies replace CMOS completely? – CMOS: high-performance, low cost, mature

fabrication, reliable, relatively low power

• When will nanotechnologies be ready? – Nanotechnologies: fabrication challenge (10–15 years

to mature), reliability challenge, performance concern, etc.

• What can we do?– CAD support, circuit design, architecture research

Open questions

• Characterizing impact of new technologies on applications: start with technology library

• Changes to classical problems: buffer insertion• Nano modeling: Compact fast models validated

against reported results and Monte-Carlo

• Reliability models: Correlations, distributions, rates

• Reliability solutions: Markov random fields or modular redundancy