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Nonlinear Multi-Error Correction Codes for Reliable MLCNAND Flash Memories AIM: The main aim of the project is to design “Nonline ar Multi-Er ror Correction Codes for Reliable MLCNANDFlash Memories” A!"#RAC#: Multi-level cell (MLC) NAND flash memories are popular storage media  because of their poer eff icienc! and large storage densit!" Conventional reliable MLC NAND flash memories based on #C$ codes or %eed-&olomon (%&) codes have a large number of undetectable and mis corrected errors" Moreover' standard decoders for #C$ and %& codes cannot be easil! modified to correct errors be!ond thei r error corr ecti ng capa bi li t! here is the $a mming distan ce of the code" n this pap er' e pro pos e to gene ral constr uct ion s of nonlinear multi-error correcting codes based on concatenations or generalied from *as il+ ev cod es" The pro pos ed constru cti ons can gen era te non lin ear bit -er ror correcting or digit-er ror corre ct ing codes i th ver! fe or even no er rors undetected or miscorrected for all code ords" Moreover' codes generated b! the generalied *asil+ev construction can correct some errors ith multiplicities larger than i thout an! e,tra overh ead in area' late nc!' and poe r cons umpt ion compared to schemes here onl! errors ith multiplicit! up to are corrected" The design of reliable MLC NAND flash architectures can be based on the proposed non lin ear mul ti- err or cor rec ting cod es" The reliabilit!' area ove rhe ad and the  penalt! in latenc! and poer consumption of the architectures based on the K.Aravind Reddy (Director) Cell No: 9652926926, 9640648
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Nonlinear Multi Error Correction Codes for Reliable MLCNAND Flash Memories.doc

Jun 04, 2018

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Page 1: Nonlinear Multi Error Correction Codes for Reliable MLCNAND Flash Memories.doc

8/14/2019 Nonlinear Multi Error Correction Codes for Reliable MLCNAND Flash Memories.doc

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Nonlinear Multi-Error Correction Codes for Reliable MLCNAND

Flash Memories

AIM:

The main aim of the project is to design “Nonlinear Multi-Error

Correction Codes for Reliable MLCNANDFlash Memories”

A!"#RAC#:

Multi-level cell (MLC) NAND flash memories are popular storage media

 because of their poer efficienc! and large storage densit!" Conventional reliable

MLC NAND flash memories based on #C$ codes or %eed-&olomon (%&) codes

have a large number of undetectable and mis corrected errors" Moreover' standard

decoders for #C$ and %& codes cannot be easil! modified to correct errors be!ond

their error correcting capabilit! here is the $amming

distance of the code" n this paper' e propose to general constructions of

nonlinear multi-error correcting codes based on concatenations or generalied from

*asil+ev codes" The proposed constructions can generate nonlinear bit-error

correcting or digit-error correcting codes ith ver! fe or even no errors

undetected or miscorrected for all code ords" Moreover' codes generated b! the

generalied *asil+ev construction can correct some errors ith multiplicities larger

than ithout an! e,tra overhead in area' latenc!' and poer consumption

compared to schemes here onl! errors ith multiplicit! up to are corrected" The

design of reliable MLC NAND flash architectures can be based on the proposed

nonlinear multi-error correcting codes" The reliabilit!' area overhead and the

 penalt! in latenc! and poer consumption of the architectures based on the

K.Aravind Reddy (Director) Cell No:9652926926, 9640648

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8/14/2019 Nonlinear Multi Error Correction Codes for Reliable MLCNAND Flash Memories.doc

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 proposed codes are compared to architectures based on #C$ codes and %& codes"

The results sho that using the proposed nonlinear error correcting codes for the protection of MLC NAND flash memories can reduce the number of errors

undetected or mis corrected for all code ords to be almost at the cost of less

than ./ increase in poer and area compared to architectures based on #C$

codes and %& codes"

!L$C% DIA&RAM:

0ig1 Decoder architecture for the proposed (2.23'2.3'33) nonlinear 4-error-correcting code"

K.Aravind Reddy (Director) Cell No:9652926926, 9640648

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#$$L": 

5ilin, &6 7". and Model&im 8"9c"

A''LICA#I$N AD(AN#A&E":

• The proposed codes have much less undetectable and miscorrected errors

than the conventional #C$ codes and %& codes"

• The be!ond- error correcting capabilit! of the presented nonlinear multi-

error correcting codes results in a further improvement of the reliabilit! of

the s!stem"

• The architectures based on nonlinear multi-error correcting codes can have

close to ero undetectable and miscorrected errors hile consuming less

than ./ more area and poer consumption than architectures based on the

#C$ codes and the %& codes"

%606%6NC6&1

:" Atood' A" 0aio' D" Mills' and #" %eaves' ;ntel &trata memor!

technolog! overvie'< ntel Technol" ="' vol" 3' 377> ?@nline" Available1

http1BB"intel"comBtechnolog!BitjBarchiveB377>"htm

=" Cooe' ;The inconvenient truths about NAND flash memor!'< presented

at the Micron M6MC@N resentation' &anta Clara' CA'"

%" Dan and %" &inger' ;mplementing MLC NAND flash for cost-effective'

high capacit! memor!'< M-&!st" Ehite paper' ?@nline" Available1

K.Aravind Reddy (Director) Cell No:9652926926, 9640648

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http1BBsupport"gatea!"comBsBManualsBDestopsB44.889BmplementingFM

LCFNANDF0lashhite/.paper"pdf  

%" #e' 6" Camerlenghi' A" Modelli' and A" *isconti' ;ntroduction to flash

memor!'<roc" 666' vol" 73' no" 9' pp" 927G4."

Micron' #oise' D' ;Eear-leveling techniHues in NAND flash devices'< gate

memoriesI'< 666 6lectron Device Lett"' vol" J' no" .' pp" 3>2G32"

K.Aravind Reddy (Director) Cell No:9652926926, 9640648