non-volatile magnetic data retention flip-flop with seperated

NON-VOLATILE MAGNETIC DATA RETENTION FLIP-FLOP WITH SEPERATEDPRECHARGE FEEDBACK SENSING

A thesis submitted to the faculty of San Francisco State University

A - in partial fulfillment of2 the requirements for

the Degree^ O lg .

„ Master of Science• v m

In

Engineering of Embedded Electrical and Computer Systems

by

Solmaz Hashemzadeh

San Francisco, California

January 2018

Copyright by Solmaz Hashemzadeh

2017

CERTIFICATION OF APPROVAL

I certify that I have read Non-Volatile Magnetic Data Retention Flip-Flop with Separated

Feedback Sensing by Solmaz Hashemzadeh, and that in my opinion this work meets the

criteria for approving a thesis submitted in partial fulfillment of the requirement for the

degree Master of Science in Embedded Electrical and Computer Systems at San

Francisco State University.

Professor of Computer Engineering\

Dr. Hoa Jiang, Ph.D.Associate Professor of Electrical Engineering

NON-VOLATILE MAGNETIC DATA RETENTION FLIP-FLOP WITH SEPERATEDPRECHARGE FEEDBACK SENSING

Solmaz Hashemzadeh San Francisco, California

2017

Spin Transfer Torque RAM (STT-RAM) promises low power, great miniaturization

prospective and easy integration with CMOS process. It has become a strong non-volatile

memory candidate for both embedded and standalone applications. However, the increase

in process variation and decrease in the supply voltage results in the degradation of the

reliability. This research targets efficient design solutions to improve the reliability of the

STT-based latches. The research investigates different sources of variability and aging in

CMOS and Magnetic Tunnel Junction (MTJ) devices used in the STTRAM process.

Different STT-Latch design styles are also investigated and their robustness against

process variations are analyzed.

I certify that the Abs on of the content of this thesis.

I 2 / 1 7 / 2 o ) 7

Chair, Thesis Committee Date

ACKNOWLEDGEMENTS

Firstly, I would like to express my sincere gratitude to my amazing advisor Dr. Hamid Mahmoodi for his continuous support of my master’s study and related research, for his patience, motivation, and immense knowledge. The door of his office was always open to questions and discussions. His guidance helped me throughout the research and writing of this thesis. I could not have imagined having a better advisor and mentor for my master’s program.

I would like to thank my wonderful parents Ghadireh and Ebrahim, my lovely sister Sara, and my amazing brothers Reza and Saeed for supporting me spiritually throughout writing this thesis and my life in general. Special thanks to my Elder brother Reza who has pushed to my highest limit and made me do my best. Without my family, I wouldn’t be where I am today.

Last but not the least, I would like to thank my friends for listening, offering me advice, and supporting me through this entire process. Special thanks to Fatima, my dear friend and roommate for her understanding, and helping me to enjoy my life-besides-works.

TABLE of CONTENTS

LIST OF TA BLES..........................................................................................................................................vii

LIST OF FIG U R ES...................................................................................................................................... viii

1.1. Computer data storage...................................................................................................................1

1.2. Non-Volatile magnetic Data Retention F lip-Flop...................................................................3

Chapter 2: Background.................................................................................................................................... 5

2.1. Magnetic recording...............................................................................................................................5

2.1.1. Traditional Magnetic R ecording............................................................................................... 5

2.1.2. Regular M agnetoresistance........................................................................................................ 6

2.1.3. Giant Magnetoresistance (G M R )..............................................................................................7

2.1.4. Tunnel Magnetoresistance (T M R )............................................................................................8

2.2. Spin Transfer Torque Memory Technology....................................................................................9

Read and Write Operation f STTRA M ............................................................................................. 11

2.3. Traditional Data Retention Flip-Flop............................................................................................ 13

Chapter 3: Existing Non-Volatile Magnetic Data Retention F lip-Flop................................................14

Chapter 4: Proposed Non-Volatile Magnetic Data Retention F lip-F lop............................................. 16

Chapter 5: Design Optimization Results and Com parison..................................................... 18

5.1. Write D river....................................................................................................................................18

5.2. Optimizing the circuit in FFE and SE m ode ............................................................................25

Chapter 6: Conclusion.................................................................................................................................... 40

References.........................................................................................................................................................41

vi

LIST OF TABLES

Table Page

1. Different types of memory...................................................................................2

2. Write driver optimization results in a predictive lOnm FinFET process....... 20

3. Area, PDP, and Sensing Delay Comparison based on minimum a re a ........... 26

4. Results Based on minimum Power Delay product............................................ 30

5. Results Based on minimum Sensing D elay .......................................................35

LIST OF FIGURES

Figures Page

1. Domain, bits, and Strings [20]..........................................................................................6

2. Giant Magnetoresistance. [21]..........................................................................................7

3. MTJ structure [24].............................................................................................................8

4. (a)Strueture of MTJ. (b) parallel Vs. antiparallel configuration of MTJ [ ] ................ 8

5. (a) basic structure and (b) the schematic of a STTRAM ce ll....................................... 9

6. The direction of the magnetization and spins of the electrons. [22]............................ 9

7.(a) Inplane MTJ (b)Perpendicular M TJ..........................................................................10

8. Write operation P->AP....................................................................................................11

9. Write operation AP->P................................................................................................... 11

10. MTJ Resistance-Voltage Characteristic.......................................................................12

11 .Conventional volatile data-retention flip-flop using balloon latch concept[3] 13

12. Existing non-volatile magnetic data retention flip-flop: Multiplexing Sense- Amplifier Based Magnetic Flip-Flop (SA-MFF) [6].................................................... 15

13. Proposed non-volatile magnetic data retention flip-flop: Separated Precharge Feedback Sensing Non-Volatile FF (SPFS NV-FF)......................................................17

14. Simulation waveforms showing a sequence of normal data sampling to set Q,MTJ write, normal data sampling to reset Q, and MTJ sensing to set Q, for both flip-flops states of Q=0 and Q=l. The MTJ magnetic angle is also shows for MTJ writeverification..........................................................................................................................19

15. MTJ write delay for the SA-MFF (19.3 ns)..............................................................21

16. MTJ write delay for the SPFS NV-FF (1.97ns)....................................................... 21

17. MTJ write power for the SA-MFF (from 85 ns to 120 n s).......................................22

18. MTJ write power for the SPFS NV-FF (from 85 ns to 120 n s)................................23

19. MTJ Failure Rate for SPFS NV-FF............................................................................24

20. MTJ write Failure rate for SA-MFF.......................................................................... 24

21 .H-spice simulation result for SA-MFF (minimum area).......................................... 26

22. H-spice simulation result for SPFS NV-FF (minimum area)..................................27

23. Sensing failure rate for SA-MFF (0.1 % ).................................................................27

24. Sensing failure rate for SPFS NV-FF (0.3%)........................................................... 28

25. Setup time for SPFS NV-FF(1.84p).......................................................................... 28

26. setup time for SA-MFF(367f)..................................................................................... 29

27. hold time for SPFS NV-FF(11.4p).............................................................................29

28. hold time for SA-MFF (18p)....................................................................................... 30

29. H-spice simulation result for SPFS NV-FF...............................................................31

30. H-spice simulation result for SA-MFF...................................................................... 31

31. Sensing failure rate for SPFS NV-FF........................................................................ 32

32.Sensing failure rate for SA-MFF.................................................................................32

33. Setup time for SPFS NV-FF(5.14p)........................................................................ 33

ixx

34. setup time for SA-MFF(1.68p)................................................................................... 33

35. hold time for SPFS NV-FF(5.14p).............................................................................34

36. hold time for SA-MFF(lOp)........................................................................................ 34

37. H-spice simulation result for SPFS NV-FF...............................................................35

38. H-spice simulation result for SA-MFF...................................................................... 36

39. Sensing failure rate for SPFS NV-FF........................................................................ 37

40. Sensing failure rate for SA-MFF................................................................................37

41. Setup time for SPFS NV-FF....................................................................................... 38

42. setup time for SA-MFF................................................................................................38

43. hold time for SPFS NV-FF..........................................................................................39

44. hold time for SA-MFF................................................................................................. 39

x

1

Chapter 1: Introduction

1.1. Computer data storage

A computer data storage, which is also called memory, is like human memory where the information is to be stored temporarily or permanently. It is controlled by the brain of computer, Central Processing Unit(CPU), which is not only responsible for extracting instructions from memory, but also responsible for performing arithmetic and logical operations. Like an orchestra leader, the CPU directs all parts of the system to execute program instructions. The memory can be divided into three main categories: CPU cache memory, primary memory, and secondary memory.

The CPU cache memory is the CPU’s internal memory. Cache holds common data that CPU is going to access repeatedly. It is incredibly fast because it does not have to be constantly refreshed in order to hold data and it is typically Static Random-Access Memory(SRAM). CPU always checks the faster cache memory first to access certain data, and if the data is not there, then it will return to slower primary memory or Random-Access Memory (RAM) to get the data.

The primary memory is typically RAM memory that can be directly accessed by the CPU. It uses capacitors to store data and these capacitors have to be refreshed often constantly and dynamically with electricity in order to store data. Even though RAM can be accessed with minimal delay and is a high-speed storage medium rather than secondary memory, it is still slower than cache.

The secondary memory is a non-volatile memory. It is not directly accessible by the CPU and retains data even if the computer is turned off. Secondary memory is cheaper and slower than primary memory. Hard drives, Solid-state drive, flash memory and floppy disk are all examples of secondary storage.

In table I, we see a comparison among different types of memory based on volatility, cell size, read and write time, endurance, write power, other power consumption, and high voltage [1], SRAM, DRAM, flash, FeRAM, MRAM are existing products. However, PRAM and STT-RAM are prototype.

2

Table 1. D ifferent types o f m em ory [1]

SRAM DRAMFlash

(N O R )Flash

(H AN D )FeRAM MRAM PRAM STT-RAM

Non-volatile No No Yes Yes Yes Yes Yes Yes

Cell size (F 1) 50-120 G-10 10 5 15-J4 16-40 6-12 6-20

Read tim e(n s) 1-100 30 10 50 20-60 3-20 20-50 2-20

Write / Erase time (ns)

1-100 50 / 50 i | »/ 10 ms

1 ms [0.1 ms

50 / 50 3-20 50/ 120 2-20

Endurance 10*’' 10* 10P 105 10“ >10* 10*° >10»*

Write power Low Low Very Sigh Very high Low High Low Low

Other powerconsumption

Currentleakage

Refreshcurrent

None None None None TJane None

High voltage required

No 2 V s -e v 16-20 V 2-3 V 3 V 1.5-3 V <1.5 V

Existrng products Prototype

One of the substantial objectives and plans for creating computers in today’s world is designing a memory chip that has the capabilities of DRAMs, SRAMs, and cache memories and that is also high speed with minimal consumption.

RAM chips (DRAM and SRAM) are fast but volatile. The flash memory and hard drive are non-volatile with low speed. Combining the speed and random access of RAM with low cost and durability of flash, will be a significant change in computer technology. Spin Transfer Torque (STT) RAM is a promising technology for information storage. Not only is it compatible with the standard CMOS technology like SRAM and DRAM, but also the information is stored in a magnetic form that is non-volatile (STT-NV). Moreover, it is more scalable than the existing storage products. In 1965, Gordon Moore made a prediction which the number of transistors that can be integrated on a chip doubles every 8-12 months. This is usually referred to as Moore’s law. However, the inherent scalability issues in memory technology drive us to search for a new form of memory technology, such as implementing magnetic tunnel junction in a magnetic memory devices.

In this research, we propose a non-volatile magnetic data retention flip-flop with Separated Pre-Charge Feedback Sensing for reliable sensing of the state of the non-

3

volatile magnetic cell. This magnetic data retention flip-flop utilizes MRAM (Magnetic RAM) technology for retention of the state of the flip-flop in the power-down mode.

1.2. Non-Volatile magnetic Data Retention Flip-Flop

Power gating in the standby (sleep) mode is an effective method for low power design[2]. However, as the system is put into the power gated mode, the critical data such as the state of the system needs to be retained and recovered upon return to the run mode [3]. Since the traditional CMOS latch and flip-flops are volatile, retention of their state requires either not applying power gating to these elements that store the critical data or to back up the state of such elements in a shadow low power latches that are always powered [3]. In either of the two methods, there is a need for isolating a part of the circuit (the normal or shadow latches) from the power grid of the rest of the circuit which adds complexity and overhead as well as power consumption.

The emergence of CMOS compatible nonvolatile memory technologies such as Spin- Transfer Torque Magnetic Memory (STT-MRAM) [4], and Resistive RAM (ReRAM)[5], offer possibilities of a new approach to the design of data retention flip-flops in which the data retention in power gated mode is achieved via the nonvolatile storage elements offered by these technologies. This way, there is no need to maintain the power supply to the data retention cells in the sleep mode. Hence, they offer design simplicity and low power. There have been several previous designs of non-volatile data retention flip-flops based on these concept and technologies [6-18]. Since in these technologies, the data is retained in resistive form, there is a need for a sense amplifier that converts the resistive state of the non-volatile cell to binary voltage for restoring the state of the flip- flop upon returning from the sleep mode. A critical design consideration in these designs is the reliability of sensing the state of the non-volatile cell under process, voltage, and temperature variations. Misreading the state of the non-volatile cell can be catastrophic since it will result in change of the state of the system upon returning from the sleep mode [8], Therefore, a near zero failure rate is expected for the sense amplifier in these designs [19]. Another challenge is in the reliability of the write circuit that writes the state of the volatile flip-flop to the non-volatile resistive cell before going to the sleep mode[7].

In this research, we propose a new design of the non-volatile data retention flip-flop that addresses the mentioned two challenges. For improved sensing reliability, the

4

proposed design utilizes the concept of two-stage sensing [19], plus a new feedback method that further improves the sensing reliability. In order to improve reliability of the write circuit, we utilize parallel write drivers, each of them writes to one of the nonvolatile elements in the differential pair of the non-volatile elements [7], The contributions of the thesis are as follows:

• A new design of a non-volatile data retention flip-flop

• New method of improving sensing reliability using feedback

• Transistor sizing optimization and fair comparisons between the proposed design and best existing design in STT-MRAM based non-volatile technology.

The remainder of the paper is organized as follows. Chapter 2 provides a background on, magnetic recording technology, STT, and traditional data retention flip-flops. Chapter 3 presents existing non-volatile magnetic data retention flip-flop. The proposed nonvolatile data retention flip-flop is presented in Chapter 4. Chapter 5 discusses design optimizations, simulation results, and comparisons. Finally, conclusions are drawn in Chapter 6.

5

Chapter 2: Background

2.1. Magnetic recording

Magnetic memory or magnetic data storage is a key component in computer operations. This depends on the ability of magnets to magnetize other materials and the ability of those materials to retain their magnetization until forced to change again by exposure to another magnetic field. The following section discusses about different types of magnetic memory technologies.

2.1.1. Traditional Magnetic Recording

A magnetic recording device is composed of a coil of wires attached to some current- sensitive device and a ferromagnetic material [20]. As shown in Fig.l. to write magnetic data to the ferromagnetic material, current is sent through the coil which produces a magnetic field. The spins in the ferromagnetic material are aligned by the magnetic field and they remain aligned until entering another magnetic field. The amount of spin alignment is affected by the strength of magnetic field. Moreover, the magnetic field decreases without the presence of the material.

Switching the direction of the current leads to recording the digital data in a series of ones and zeros. The change in magnetic orientation between two domains represents the binary data. If contiguous domains have the same magnetic field direction, it represents a zero. If they have the opposite filed direction, it represents a one.

The bits can be read by the read head which senses the direction of the magnetic field as it goes over a written bit. A current in the coil of wire is induced by changing magnetic field in the domain. If a zero is represented, the magnetic field does not change, so no current is induced. In case of a one, the magnetic field changes from one direction to the other; this change induces a current in the coil.

6

N S

S N

.N S N S

S N S N

S NjN S|

N S S N

N S

Domains

Ijs n | s n|

Bits representing 0

IN S N S N SIS N S N

Bits representing 1

T n In sW w

A string of Os A string of Is

Figure 1. Domain, bits, and Strings [20]

Limitations of traditional technology, such as speed of ferromagnetic material and the strength of the magnetic field, lead to new magnetic storage devices that use the phenomenon of magnetoresistance to read magnetic data.

2.1.2. Regular Magnetoresistance

The dependence of resistance on magnetic field is called magnetoresistance. The larger magnetic field, the higher resistance [20], This property is used in computers to read magnetic data. A potential difference is applied to a wire that is located close to the magnetic material. By passing the magnetic fields representing data on the material through the wire, the resistance of the wire changes. The change in resistance causes the current to change through the wire. Reading of the magnetic field is done by monitoring the current.

Magnetoresistance is more precise than induction because the induction depends on the change of field. Therefore, we can also understand that it depends on speed of magnetic material. The magnetoresistance depends on the field. Furthermore, the circuitry that is needed to measure magnetoresistance is simpler than the circuitry that is needed for induction.

The combination of inductive writing with magneto resistive reading is a simpler organization than the inductive read/write combination.

7

2.1.3. Giant Magnetoresistance (GMR)

GMR effect was discovered by Albert Fert and Peter Grunberg. It refers to large changes in electrical resistance of magnetically ordered materials which is observed during the presence of an external magnetic field. It vanishes without the field.

GMR is observed by two configurations: tri-layer and super lattice. Tri-layer configuration consists, as shown in Fig. 2., of two ferromagnetic layers and a nonmagnetic (middle) layer. The middle layer, which is nonmagnetic, needs to be thinner than mean free path of conduction electrons, a few nanometers. The top layer is the free layer, because its electron spins are free to change. The bottom layer is called the fixed or pinned layer, because its spin orientation is fixed when the device is made. Electrical resistance change depends on whether the magnetization of these two ferromagnetic layers are in a parallel or an antiparallel. For parallel alignment, the overall resistance is low and for antiparallel alignment, the resistance is high.

Antiparallel Parallelmagnetizations magnetizations

Ferromagnet (Co)Nonmagnetic metal (Cu)Ferromagnet (Co)

Resis

R u

Rtt

Magnetic field

Figure 2. G iant M agnetoresistance. [21]

Spin dependent scattering, which depends on the orientations of the electron’ spins and those magnetic moments, is the key mechanism of GMR effect. Therefore, by discovering GMR effect, the new phenomena, which is called spintronic, was founded.

Spin-electronic or spintronic is a novel field that relies on the intrinsic angular momentum of an electron, spin. Contrary to electronic devices, which information is carried by flow of electricity (presence or absence of electrons represent the zeroes and ones of computer binary code), in spintronic devices, information is carried by spin of electrons. Spintronic is controlled by an external magnetic field. Electrons are polarized by applying an external magnetic field. Thus, spins are aligned either up or down which respectively represents the one and zero of binary code. [21]

2.1.4. Tunnel Magnetoresistance (TMR)

MTJ, just like a GMR, consists of pinned and fixed layer. However, in the TMR, the metallic spacer layer is replaced by an insulating layer that is referred to as tunnel barrier. As shown in figure 3. there is an angle between the magnetization of fixed layer and free layer. M is the magnetization of the free layer, P is the magnetization of the pinned layer or fixed layer, and 9 is the angle between M and P. Je is the current density.

Free Layer Insulator

Fixed Layer

Figure 3. MTJ structure [24]

As shown in fig.4. depending on magnetic orientation of free layer, different resistance observed between the two terminals. If two layers are parallel, more electrons are tunneled of the MTJ device (low resistance). If two layers are anti-parallel, then less electrons are tunneled of the MTJ device (high resistance). The resistance change is known as tunnel magneto-resistance (TMR) ratio.

MTJ Structure

(a)

I AP—P

P CcuifipMMM MTJ A? C0ii%wriiNm MTJ

Figure 4. (a)Structure o f MTJ. (b) parallel Vs. antiparallel configuration o f MTJ [33]

2.2. Spin Transfer Torque Memory Technology

Figure 5. (a) basic structure and (b) the schem atic o f a STTRAM cell[23]

A single STTRAM cell is shown in F ig .ll. It consists of two components: Magnetic Tunnel Junction (MTJ) and access transistor. The transistor could be FinFET or any CMOS transistor, which our design is based on FinFET technology. A transistor is needed due to access the programmable resistors (MTJ) and put in an array form.

Figure 6. The direction o f the m agnetization and spins o f the electrons. [22]

As shown in Fig. 6., the magnetization of the fixed layer is assumed to be unchangeable by any current density. Two spin filtering will happen: First Filtering: Current flows from the free layer to fixed layer, the electrons (s-band) will spin-polarized

10

in the direction of magnetization of the fixed layer. The second spin filtering: electrons reach the free layer, s-d exchange interaction occurs. The electrons will align themselves along the magnetization of the free layer. After processing the electron around the magnetization of the free layer, transvers components of spin angular momentum become zero, since the precession is averaged over all electrons. Since the precession is averaged over all electrons, transverse components of spin angular momentum become zero as the electrons are out of phase. Due to conservation of spin angular momentum, the transverse components of the electron spins will be absorbed and transferred to magnetization of free layer. Therefore, the same interaction also exerts a torque on the magnetization of the fixed layer. This torque effect is commonly known as spin transfer torque (STT) [22], Although the minority-spin electrons, with respect to the free layer, will be reflected back to the fixed layer, the magnetization of the fixed layer will not change because this torque is not strong enough [22], Similar situation happens when the electrons move from the free layer with one exception. The torque exerted by the electrons that process around the magnetization of the fixed layer are insufficient to switch the magnetization. The minority-spin electrons, with respect to the fixed layer, are reflected back to the free layer. These electrons apply torque that enough to switch the magnetization of the free layer antiparallel to the fixed layer. The strength of the torque is normally expressed as the magnitude of current density [22],

Bit line (BL)

Free layer —__

Barrier — -

Pinned layer— —

Word Line (WL)

Source Line (SL)

I (— 1 Selectingtransistor

I r—+ H L 1

Free layer -

Barrier -

(a) inplane Magnetic Tunnel Junction (IMTJ)

Figure 7.(a) Inplane MTJ (b)Perpendicular MTJ [23]

Perpendicular Magnetic Tunnel Junction (PMTJ)

11

As shown in Fig. 7. In-plane MTJ (IMTJ), and perpendicular MTJ (PMTJ) are two types of MTJ, IMTJ where magnetization of ferromagnetic layers lies in the film plane, and PMTJ where magnetization direction is perpendicular to the film plane [23].

Read and Write Operation f STTRAM

For the read operation, the word line is selected and a voltage is applied to the bit line. Current density should be less than the switching current density.

For the write operation, induced current density should be larger than the critical write current density. Writing from parallel to antiparallel and the opposite sides are shown in fig. 8 and fig. 9.

BarrierReference layer (pinned) (Spin filter)

Source Line

Figure 8. W rite operation P->AP[34]

Figure 9. W rite operation A P->P [34]

12

P-stateC o F e

C o F e .

M g O

AP-state

M T J

a P inned/ ' | Layer

P-state j vv A P-state_______ i___ 'v_____________

Figure 10. MTJ Resistance-V oltage C haracteristic [34]

We can see MTJ resistance-voltage characteristic in Fig. 6. MTJ needs high voltage for write, but low voltage for read. Information stored and sensed as resistance.

13

2.3. Traditional Data Retention Flip-Flop

In all CMOS flip-flop or latch designs, data are stored in either a static form using a cross-coupled inverter feedback loop or in a dynamic way using charge stored on a floating node capacitance [25], In either of these methods, the storage is volatile. In power-down (sleep) mode, in order to retain the data stored in such flip-flops without having to keep the power on the flip-flop which would cause extra leakage, the data are backed up to another volatile but always powered latch that is made of high threshold voltage (Vth) transistors for low power. This extra low leakage latch is called the balloon or shadow latch [3]. Fig. shows the concept of the balloon latch applied to a transmission gate master- slave flip-flop [3].

Figure 11 .C o n v e n tio n a l v o la tile d a ta - re te n tio n f lip -f lo p u s in g b a llo o n la tch c o n c e p t [4]

Given that the balloon latch requires continuous presence of power supply in the sleep mode, this design complicates the power supply routing and also it still exhibits some non-zero leakage in the sleep mode.

14

Chapter 3: Existing Non-Volatile Magnetic Data Retention Flip-Flop

In a non-volatile magnetic data retention flip-flop, the state of the flip-flop is backed up to a MTJ (or pair of MTJs) before the sleep mode and the state is restored back from the MTJ(s) right after the wake-up. Among the existing non-volatile magnetic data retention flip-flops [6-16], the Multiplexing Sense Amplifier Based Magnetic Flip-Flop (SA-MFF) [6] offers the best overall performance, and hence is chosen as the state-of-the-art design for comparing against our proposed design. Fig. 12 shows the schematic of the SA-MFF [6], This design uses a sense amplifier based flip- flop [26], and adds a multiplexer (transistors (M4,M6) and (M3,M5)) to choose between the normal data input (D,/D) or the MTJs (MTJO and MTJ1) for sensing. There is also a write drive that once it is enabled, it writes the state of the flip-flop output (Q) into the differential MTJ pair.

The sense amplifier is a conventional pre-charge sense amplifier followed by a modified set/reset latch [26]. The MTJ write circuit utilizes two write drivers that drive opposite logical state to the two ends of the two MTJs that are series connected in the write mode while CLK is zero. Hence, the same write current passes through both MTJs and therefore to make sure the two MTJs are programmed differentially, their free and pinned layer terminals need to be connected the same way (i.e. both pinned layers to the CLK node and the free layers to the write driver outputs). A major drawback of this write scheme is that the two MTJ are put in series in the write mode resulting in added resistance in the write path and hence reduction in effective write current. This requires increasing the size of the write drivers which in turn degrades the performance of the flip- flop in the normal and sensing modes due to the increased capacitances on the write driver output nodes. Due to the high write current requirement of the MTJ, this write scheme may fail to write to the MTJs at nominal supply voltage regardless of how big the size of write drive transistors are made because the current will eventually get limited by the resistance of the series connected MTJs. Under this situation the voltage of the write driver circuit would need to be increased beyond the nominal supply voltage and high Vth transistors may also be needed in the write drivers to avoid accidental write to MTJs due to increased leakage of the write driver at high voltage and large transistor size.These requirements will further complicate the design and increase the overhead of this existing design.

15

I I Sinw ( 1 IMAG3 Write d l « i u

Q

Figure 12. Existing non-volatile m agnetic data retention flip-flop: M ultiplexing Sense-A m plifier Based M agnetic Flip-Flop (SA -M FF) [6]

16

Chapter 4: Proposed Non-Volatile Magnetic Data Retention Flip-Flop

Fig. 15 shows the proposed magnetic data retention flip-flop, referred to as Separated Pre-charge Feedback Sensing Non-Volatile FF (SPFS NV-FF). It utilizes several key techniques for addressing the shortcomings of the conventional SA-MFF and for enhancing sensing reliability, write performance, and normal mode performance of the design. The design utilizes the concept of multiplexing between the data input and the MTJ inputs for sensing. Additionally, the design has three modes of operation: normal flip-flop mode when FFE is high, MTJ sensing mode when SE is high, and MTJ write mode when WEN is high. For enhanced MTJ sensing reliability, the MTJ sensing mode utilizes two stage sensing where a first-stage amplifier feeds to the second stage amplifier. The Data mode uses only the second stage amplifier. The second stage amplifier outputs (S and R) are latched by a modified S-R latch [26]. The first stage sense amplifier utilizes cross-coupled PMOS load on the differential branches to further amplify the voltage differential created by the MTJ pairs during the sensing. Since both MTJ nodes will discharge (at different rates) to ground, in order to avoid the crosscoupled PMOS load from causing short-circuit power, the connection of the crosscoupled PMOS load to the supply voltage (VDD) is cut-off via a feedback path (series connected MOSes driven by S and R), once the sensing evaluation has finished (i.e. when either S or R signals has switched high as a result of the evaluation of the second stage sense amplifier).

A major drawback of the MTJ write circuit in the conventional SA-MFF is that the two MTJs are put in series between the two write drivers and hence requiring a very large size driver and/or a high voltage for the write drivers. To address this shortcoming, we utilize a parallel MTJ write circuit by utilizing three write drivers, where one is a common driver and the other two are drivers that are unique to each MTJ. Since in this scheme the current will flow in the same direction (either to the common driver or out of the common driver), the MTJs need to be flipped in their fee and pinned layer connection as shown in Fig. 13. This arrangement will result in programming the states of the two MTJs in opposite states despite the current flowing in the same direction among the two MTJ paths. Using this write scheme the write drivers do not need to be upsized as much, resulting in less capacitive loading on the MTJ nodes. Consequently, it leads to reduced MTJ sensing delay and reduced MTJ sensing failure rate. Moreover, in the proposed scheme, the write driver outputs are isolated from the normal data sensing paths by the NMOS driven by the SE signal which is low in the normal flip-flop mode.

17

Isolating the output capacitances of the write driver from the normal data paths will also result in improved power and performance of the flip-flop in the normal flip-flop mode.

VDD

FFE VDD FFE

H L > db

Figure 13. Proposed non-volatile magnetic data retention flip-flop: Separated Precharge Feedback Sensing Non-Volatile FF (SPFS NV-FF)

WEN

18

Chapter 5: Design Optimization Results and Comparison

The schematic of SPFS NV-FF and SA-MFF are drawn in Custom Designer and the netlists which have been obtained from the schematic are used in Hspice simulation for comparing these two designs. The design optimizations are performed as follow: First, the sizing of the transistors in the write drivers is optimized for achieving successful write to MTJs. After the write drivers are optimized, then the sizing of the rest of the transistors is optimized for achieving the minimum Power-Delay-Product (PDP) in the normal mode of operation (flip-flop mode; FFE being high) and minimum MTJ sensing delay in the MTJ sensing mode (SE being high).

5.1. Write Driver

The proposed SPFS NV-FF has a larger transistor count than the conventional SA-MFF; however, given that it reduces the size of the transistors on the write drivers by utilizing 3-driver MTJs-in-parallel write scheme, it can achieve significant reduction in the size of the write driver transistors. To establish a fair comparison between the two designs, transistor sizing in both designs need to be optimized for same objectives and under same constraints. Therefore, the sizing of the transistors in the write drivers are optimized for achieving successful write to MTJs.

Both the conventional and proposed designs are optimized and simulated in a predictive lOnm FinFET process [23], The MTJ model is also a predictive model [24], which is scaled to the lOnm node by scaling the MTJ radius parameter down to 8nm (MTJ diameter of 16nm). Fig. 14. shows the simulation waveforms verifying the operation of the proposed flip-flop in all the modes of operation. The flip-flop output is first set to the state of Q=0 and this state is written to the MTJs and then, the flip-flop output is reset to Q=1 in the normal mode, followed by the MTJ sensing operation that successfully restores Q back to 0. The same sequence is repeated for the initial output state of Q=l. This functional verification waveform test is used to optimize the write circuit transistor sizing. The write driver size is reduced until a write failure and consequently a functional failure is observed in these waveforms.

The write driver in the conventional design cannot achieve successful MTJ write at nominal supply voltage, regardless of how big the write driver transistors are. This is due to write current being limited by the series connected MTJ resistances resulting in a

19

maximum current that is yet below the MTJ critical write current. In order to achieve successful MTJ wire in this scheme, the supply voltage of the write controller and drivers have to be increased by 25.5% above the nominal voltage level. It is then observed that at this high supply voltage, the increased leakage of the write driver could result in accidental write to the MTJ that is in the antiparallel state (due to the low critical current for switching from antiparallel to parallel state, compared to the other direction [25]). To address this issue, the write driver transistors are assigned high threshold voltage (Vth) to reduce their leakage. The size of the write driver transistors is set to a minimum that allows successful MTJ write. The write driver of the proposed design on the other hand can easily achieve successful MTJ write even using minimum sized transistors in the write drivers.

n

Figure 14. Sim ulation w aveform s show ing a sequence o f normal data sam pling to set Q, M TJ write, norm al data sam pling to reset Q, and MTJ sensing to set Q, for both flip-flops states o f Q=0 and Q = l. The M TJ magnetic angle is

also shows for MTJ write verification.

Table I shows the results of the write driver optimizations for both designs. Total number of transistor fins is used as a measure of circuit area. The proposed design achieves 92.5% reduction in the write driver area, thanks to the 3-driver MTJs-in-parallel write scheme. As it will be shown later, this reduction in the MTJ write circuit size will translate into improvements in the design performance of the MTJ sensing and normal modes as well through reduction in capacitances of the write driver outputs connected to

20

the MTJ nodes. The MTJ write delay, power, and energy are reduced by 89.8%, 84.2%, and 98.5%, respectively. The MTJ write failure rate is measured by applying statistical intra-die variations to transistor threshold voltages and MTJ radius and insulator thickness parameters. The proposed design for the MTJ write failure rate is 0.4% and it reduced by 95 %.

Table 2. W rite driver optim ization results in a predictive lOnm FinFET process (V dd= lV ; Tem perature= l 10C)

Flip-Flop

WriteDriverVoltage(V)

WritedriverVth

Write Driver Area (# of fins)

MTJWriteDelay(nS)

MTJwritePower(uW)

MTJWriteEnergy(PDP)(fj)

MTJ Write Failure Rate (%)

OldDesign

1.26 High 120 19.3 19.39 374.227 8.5

NewDesign

1 Low 9 1.97 3.05 6.008 0.4

The above result is based on the following simulations:

MTJ write delay (ns):

The MTJ write delay is a delay which measures the maximum amount of time that it takes for the Flip-Flop to write the data in the MTJs. This delay is the maximum delay when the write enable goes from 0 to 1, ntheta (angle between magnetization of ferromagnetic layers) goes from 0 to 1, and write enable goes from 0 to 1, ntheta goes from 1 to 0. In Fig. 13. and 14. the maximum MTJ write of each delay are shown.

21

Figure 16. MTJ write delay for the SPFS N V -FF (1.97ns)

22

MTJ write power:Writing to MTJs in SA-MFF and SPFS NV-FF happens when write enable is 1.

While clock is 0 in SA-MFF, and 1 in SPFS NV-FF. As it shows in Fig. 14 write enable is high from 85 ns to 120 ns. Hence the MTJ write power is measured from 85 ns to 120 ns for both designs. Fig. 17 and 18 show the h-spice simulation results for measuring the write power.

3 nafez sfsu.edu (shashemz)

****** transient analysis tnom= 25.000 temp= 110.000 ******ptot= 19.3949U from= 85.0000n to= i20.0000nvq= 625.0657Uvqbar= 749.8834m

***** job concluded!****** HSPICE -- 1-2013.12-SP1-1 32-BIT (Mar 31 2014) RHEL32 ******

*****»*******nsultiplexing sense aroplifer based magnetic flip-flop *** ***********

****** job statistics summary tnom= 25.000 temp= 110.000 ******

****** Machine Information ******CPU:model name : Intel(R) Xeon(R) CPU X5570 @ 2.93GHzcpu MHz : 2926.141

OS:Linux version 2.6.18-194.32.1.el5 ([email protected] .com) {gcc version 4.1.2 20030704 (

Red Hat 4.1.2-48}) #1 SMP Mon Dec 20 10:52:42 EST 2010

****** HSPICE Threads Information ******

Command Line Threads Count : 1Available CPU Count : 16Actual Threads Count : 1

****** Circuit Statistics ******# nodes = 178 # elements = 109# resistors = G # capacitors = 0 # inductors = G# mutual_inds = 0 # vccs = 0 # vcvs = 0# cccs = G # ccvs = 0 # volt_srcs = 52# curr_srcs = 0 # diodes = 0 # bjts = 0# jfets = G # mosfets = 47 # U elements = G# T elements = G # W elements - G # B elements = 0# S elements = G # P elements = 0 # va device = 10# vector srcs = G # N elements = G

Figure 17. MTJ write pow er for the SA-M FF (from 85 ns to 120 ns)

23

M M ® ;l h,'t'" C‘fV‘ l'1

****** transient analysis tnom= 25.0GG temp= 11G.G0G ******ptot= 3.0575U f rom= S5.G000n tO= 120.G0G0nvq= 749.8345mvqbar= 626.5780U

***** job concludedHSPICE - 1-2013.12-SP1-1 32-BIT {Mar 31 2G14) RHEL32 *»-*»**

sense amplifer based magnetic flip-flop *** ***********

****** job statistics summary tnom= 25.GGG temp= 11G.000 ******

****** Machine Information ******CPU:model name : Intel(R) Xeon{R) CPU X5570 @ 2.93GHzcpu MHZ : 2926.141

OS:Linux version 2.6.18-194.32.I.elS ([email protected]) (gcc version 4.1.2 20083704 (1ted Hat 4.1.2-43)) #1 SMP Mon Dec 20 10:52:42 EST 201G



****** Circuit Statistics ******# nodes = 225 # elements = 137# resistors ■= 0 # capacitors = 9 # inductors = 0# mutual_inds = 0 # vccs = 0 # vcvs = 0# cccs = 0 # ccvs = 9 # volt_srcs = 66# curr_srcs = 0 # diodes = 0 # bjts = G# jfets = 0 # mosfets = 61 # U elements = 0# T elements = D # W elements = 0 # B elements = G4 S elements = 0 # P elements = 0 # va device = 10# vector sres = 0 # N elements = 0

Figure 18. MTJ write pow er for the SPFS NV-FF (from 85 ns to 120 ns)

Finally, the write MTJ failure rate is measured for both designs by Monte Carlo simulations and applying statistical intra-die variations to transistor threshold voltages and MTJ radius and insulator thickness parameters. Fig. 19 and 20 are obtained by running the Monte Carlo simulation (sweep monte=1000) for MTJ Failure Rate. We can see the reduction of MTJ failure rates, which is 95 % by these figures.

am im m m mm®p , 2(?n 4(?n.

b v<ntheial■ vtttfv!

ntHn) ~, 6?n , . 8?"

20n ' ' ’ Ton ' r F 60n ̂ ' 80n

L J

100n 120n 140n 160n

Figure 19. MTJ Failure Rate for SPFS NV-FF

Figure 20. MTJ write Failure rate for SA-M FF

25

5.2. Optimizing the circuit in FFE and SE mode

Once the process of optimizing the write drivers is done, under the same total area constraint set on both designs, the sizing of the rest of the transistors are optimized for achieving minimum Power-Delay-Product (PDP) in the normal mode of operation (flip- flop mode; FFE being high) and minimum MTJ sensing delay in the MTJ sensing mode (SE being high).

Two different methods are applied for PDP and sensing delay optimization. First, we utilize the built-in Hspice optimizer tool [21]. The area constraint is set to be 50% above the area of the bigger of the two designs after the write drivers are optimized, while the rest of the transistors are kept at minimum size. The optimizer allows defining optimization parameters (i.e. the sizes of transistors), optimization goals (minimize PDP and MTJ sensing delay), and optimization constraint (total area less than a max limit). However, due to built-in H-spice optimizer tool constraints, to achieve more accurate results, the optimization is performed by Perl script as a second method.

After 65610 number of simulations, in which transistors’ sizes were swept between one and three, we categorized results based on minimum delay, minimum PDP, and minimum sensing delay. The results are shown in the following section.

First, Area, PDP, and sensing delay of two design are measured. As the results indicate, three of them are improved in SPFS NV-FF in all three categories. Then, clock to q delay, setup time, hold time, sensing failure rates are measured for all categories.

Design Optimization Results and Comparison

5.2.1. Comparison based on minimum area

By considering the minimum area as a parameter for comparing two designs, the results in table 3 is obtained. The area, PDP, and sensing delay is reduced by 74.7 %, 65.6 %, and 69.3 %.

26

Table 3. Area, PDP, and Sensing Delay Com parison based on m inim um area

Multiplexing Sense Amplifier Separated Precharge Feedback Sensing Based Magnetic FF Non-Volatile FF

Area 277 70PDP(J) 1.89e-16 6.5e-17

Sensing Delay(s) 7.5e-ll 2.3c-ll

Fig.21 and 22 show the h-spice simulation results for PDP in flip-flop mode and sensing delay in sensing mode. Sensing delay is maximum delay form clock to output when sensing enable is high which is reduced by 69.3 %.

For PDP, we need to measure power and delay in flip-flop mode. Bothe of them measured by h-spice simulation. Based on our results the clock to output delay (maximum delay from clock to output), is increased by 9.8 %, and power is decreased by 68 %. PDP, which is measured by multiplication of power and clock to output delay is decreased by 65.6%.

jp|GXing ser)<;e amplifer based magnetic flip flop

****** transient analysis tnom= 25.GOO temp- 110.000 ****** ptot= 11.4930U from= 10.0000n to= 160.0G0Gntslh= 14.5416p targ= 55.0195n trig= 55.0G5Gntshl= 75.7626p targ^ 65.G808n tn g^ 65.0G50ntsense= 75.7626ptpc2q_lh= 14.S407p targ= 75.0295n trig= ?5.0150ntpc2q~hl= 16.4543p targ= 125.0315n tn g= 125.0150ntp_c2q= 16.4543ppdp= 1S9.1089avq- 625.0S57uvqbar= 749.8834m

***** 30b concluded !****** HSPICE - I-2G13.12-SP1-1 32-BIT (Mar 31 2014) RHEL32 ******

sense areplifer based magnetic flip-flop **************

****** job statistics summary tnoro= 25.000 temp= 110.0G0 ******

****** Machine Information ******CPU:model name : Tntel(R) Xeon(R) CPU X557G <a 2.93GHzcpu MHz : 2926.141

OS:Linux version 2.6.18-194.32.I.elS <mockbuild(»x86-006.build.bos.redhat.com) (gcc version 4.1.2 20080704 ( Red Hat 4.1.2 48)) #1 SMP Mon Dec 20 1G:52:42 EST 2G10


Command Line Threads Count : 1Available CPU Count ; 16Actual Threads Count : 1

Circuit Statistics

Figure 21.H-spice sim ulation result for SA-M FF (m inim um area)

27

132:mpfet 1.6469k 1.6469k 0. 0. 0.0.

*pval* minimum timestep = le-2G

********#***#mu\tiplexing sense amplifer based magnetic flip-flop **************

****** transient analysis tnom= 25.000 temp= 110.G00 ****** ptot= 3.6444u frore= 10.0000n to= 16G.0000ntslh= 21.9315p targr 65.0270n trig= 65.GG50ntshl= 23.9290p targ= 135.0289n t n g = 135.0050ntsense= 23.92SGptpc7q_lh= 15.4947p targ= 125.0205n trig= 125.0O50ntpc2q~hl= 18.G743p targ= 55.023In trig= 55.0050ntp_c2q= 13.0743ppdp- 65.S725avq= 749.8345mvqbar= 626.5780U

***** j0b concluded j****** hSPICE -- 1-2013.12-SP1-1 32-BIT (Mar 31 2014) RHEL32 ******

*************nwltiplexing sense amplifer based magnetic flip-flop **************

****** j0b statistics summary tnom= 25.000 temp= 110.G00 ******

****** Machine Information ******CPU:model name : Intel(R) Xeon(R) CPU X5570 & 2.93GHzcpu MHz : 2926.141

OS:Linux version 2.6.18-194.32.I.el5 {[email protected]) (gcc version 4.1.2 20080704 ( Red Hat 4.1.2-48)) #1 SMP Mon Dec 20 10:52:42 EST 2G10

»*«*** h SPICE Threads Information ******


Figure 22. H-spice sim ulation result for SPFS N V -FF (m inim um area)

Fig. 23 and 24 show the sensing failure rate for SA-MFF and SPFS NV-FF. Sensing failure rate is driven by running the Monte Carlo (sweep monte=1000) simulations for both designs, which is measured for sensing delay.

Figure 23. Sensing failure rate for SA-M FF (0.1 %)

mailto:[email protected]

28

Setup time is the minimum data to clock offset that causes the causes the clock to output delay to be 5 % higher than its nominal value [32]. Fig. 25 and 26 show the setup time based on h-spice simulation for SPFS NV-FF and SA-MFF. Based on the results we can see the setup time of SPFS NV-FF is increased.

Figure 25. Setup tim e for SPFS N V -FF(1.84p)

29

Figure 26. setup time for SA -M FF(367f)

Hold time is the minimum time interval during which a new datum has to retain its value after the active clock edge so that clock to output delay is 5% higher that its nominal value [32], Fig. 27 and 28 show the hold time for SPFS NV-FF and SA-MFF. The hold time of SPFS NV-FF is decreased by 36.6 %.

Figure 27. hold time for SPFS N V -FF(11,4p)

30

Figure 28. hold time for SA-M FF (18p)

5.2.2. Comparison based on minimum power delay product

By considering the minimum PDP as a parameter for comparing the area two designs, the results in table 4 is obtained. The area, PDP, and sensing delay is reduced by 52.9 %, 68.8 %, and 62.7 %.

Table 2. Results Based on minim um Power Delay product:

Multiplexing Sense Amplifier Based Magnetic FF

Separated Precharge Feedback Sensing Non-Volatile FF

PDP(J) 10.6e-17 3.3e-17

Area 177 80

Sensing Delay(s) 5.9e-l1 2.2e-l 1

31

Fig.29 and 30 show the h-spice simulation results for PDP in flip-flop mode and sensing delay in sensing mode. Clock to output delay is increased by 33.7%, power is decreased by 76.6 %. Therefore, PDP is decreased by 68.8 %

iltiplexing sense ampliter ba i magnetic flip-tlop *

****** transient analysis tnom= 25.G00 tercp= 110.06© ****** ptot= 2.S349U from- lO.OOOGn to= 14G.G0G0ntslh= 21.5237p targ= 65.0265n trig= 65.605Ontshl= 2?.6503p targ= 135.0277n trig= 13S.6S50ntsense= 22.6503ptpc.2q_lh= 11.1513p targ= 125.0162n trig= 125.005©ntpc2q hl= 11.5077p targ= 55.0165n trig= 55.©050ntp_c2q= 11.5G77pprip̂ 33.1990aarea= 65.0000vq= 749.6879mvqbar= 215.9251u

***** job concluded I****** HSPICE -- 1-2013.12-SP1-1 32-BIT {Mar 31 2014) RHEL32 ******

sense amplifer based magnetic flip-flop ****»»


****** Machine Information ******CPU:model name : Intel(R) Xeon(R) CPU X5S70 <3 2.93GHzcpu MHz : 2926.141

OS:Linux version 2.6.1S-194.32.1.el5 (roockbuildOxSe-OOe.build.bos. redhat.cots) (gcc version 4.1.2 2O0807G4 ( ?.ed Hat 4.1.2-4S)) #1 SMP Mon Dec 29 10:52:42 EST 2G10

HSPICE Threads Information

Command Line Threads Count Available CPU Count Actual Threads Count

i

Figure 29. H-spice sim ulation result for SPFS N V -FF

Cjjjj} s. hafezstsu ertu{shashem?>

sense amplifer based magnetic flip-flop **************

****** transient analysis tnom= 25.0GB temp= 11O.0OO ****** ptot= 12.3251U from= lG.DOGOn to= 16O.O000ntslh= S.6114p targ= 55.6136n trig= 55.0050ntshl= 59.6675p targ= 65.0647n trig= 65.O05Ontsense= 59.6675ptpc2q lh= 8.6420p targ= 75.0236n trig= 75.0150ntpc2qlhl= 7.8754p targ= 125.0229n tng= 125.015Dntp c2q- S.6420ppdp= 106.5134avq~ 268.4643uvqbar= 749.6922m

***** job concluded 1****** HSPICE - 1-2013.12 SP1-1 32-BIT (Mar 31 2014) RHEL32 ******

*************multiplexing sense amplifer based magnetic flip-flop **J

****** job statistics summary tnom= 25.0GG temp= 110.000 ******


HSPICE Threads Information

Command Line Threads Count Available CPU Count Actual Threads Count

Circuit Statistics

Figure 30. H-spice sim ulation result for SA-M FF

32

Fig. 31 and 32 show the sensing failure rate for SA-MFF and SPFS NV-FF, which is decreased by 55.5%.

Figure 31. Sensing failure rate for SPFS N V -FF

mmm mm m m mm mmm mml f f n t_ 13£n ( . 137n 13jSn..

TtME(sec) (lm) ( 135n

Figure 32. Sensing failure rate for SA-M FF

33

Fig. 33 and 34 show the setup time based on h-spice simulation for SPFS NV-FF and SA- MFF, which is increased in our design.

Figure 33. Setup time for SPFS N V -FF(5.14p)

Figure 34. setup time for SA -M FF(1.68p)

34

Fig. 35 and 36 show the hold time for SPFS NV-FF and SA-MFF. The hold time of SPFS NV-FF is decreased by 48.6 %.

Figure 35. hold time for SPFS N V -FF(5.14p)

Figure 36. hold time for SA -M FF(lO p)

35

5.2.3. Comparison based on minimum sensing delay

By considering the minimum sensing delay as a parameter for comparing the two designs, the results in table 5 is obtained. The area, PDP, and sensing delay is reduced by 48.5 %, 43.5 %, and 66.6 %.

Table 3. Results Based on m inim um Sensing Delay

Multiplexing Sense Amplifier Based Magnetic FF

Separated Precharge Feedback Sensing Non-Volatile FF

Sensing Delay(s) 5.7e-l1 1.9e-l 1Area 175 90

PDP(J) 13.08e-18 7.3e-17

Fig.37 and 38 show the h-spice simulation results for PDP in flip-flop mode and sensing delay in sensing mode. Clock to output delay is increased by 10.4%, power is decreased by 48.85%. Therefore, PDP is decreased by 43.5 %

@ 1 Home 15—o.

*pval* minimum timestep = le-20

sense amplifer based magnetic flip-flop ***'

****** transient analysis tnom- 25.000 temp- 110.000 ****** ptot= 6.O5O0U from= lO.OOOOn to= 140.000Gntslh= IS.450Sp targ- 65.0235n trig- 65.0050ntshl= 19.4961p targ= 135.0245n trig= 135.0G50ntsense= 19.4961ptpc2q_lh= 12.2179p targ= 125.0172n trig= 125.005Gntpc2q_hl= 11.6763p targ= 55.0167n triq= S5.G050ntp_c2q= 12.2179ppdp^ 73.9186aarea= 75.0000vq= 749.6924mvqbar= 269.7126u

***** jot, concluded I****** HSPICE -- 1-2013.12-SP1-1 32-BIT (Mar 31 2014) RHEL32 ******

»************mu1tip1exing sense amplifer based magnetic flip-flop ***

****** job statistics summary tnom= 25.000 temp- 11G.0G0 ******

****** Machine Information ******CPU:model name : Intel(R) Xeon(R) CPU X5570 <a 2.93GHzcpu MHz : 2926.141

OS:Linux version 2.6.13-194.32.I.el5 (mockbuild<3x36-O06.build.bos.redhat.com) (gcc version 4.1.2 20030704 (

Red Hat 4.1.2-43)) #1 SMP Mon Dec 26 10:52:42 EST 201G


Command Line Threads Count : 1Available CPU Count : 16Actual Threads Count : 1___________

Figure 37. H-spice sim ulation result for SPFS NV-FF

^ 1, Home Q 3. hafez.sfsu.edu (shashemz) x A<>\*******.*.*****mu\tiplexing sense amplifer based magnetic flip-flop *****

****** transient analysis tnom= 25.000 temp= 110.000 ****** ptot= 11.8330U f rom= 10.0000n to= 16O.0000ntslh= 11.0765p targ= 55.0161n trig= 55.0050ntshl= 57.8955p targ= 65.0629n trig= 65.005Ontsense= 57.8955ptpc2q_lh= 11.055Ip targ= 75.0261n tng= 75.0150ntpc2q_hl= 9.7141p targ= 125.0247n trig^ 125.0150ntp_c2q= 11.0551ppdp= 130.8150avq= 153.7857Uvqbar= 749.5384m

***** job concluded 1****** HSPICE -- 1-2013.12-SP1-1 32-BIT (Mar 31 2014) RHE.L32 ****** **** **

*************roultiplexing sense amplifer based magnetic flip-flop *****



OS:Linux version 2.6.18-194.32.1.el5 (mockbuild0x36-006.build.bos.redhat.com) (qcc version 4.1.2 20080704 ( Red Hat 4.1.2-48)) #1 SMP Mon Dec 20 10:52:42 EST 2010



****** circuit Statistics ******

Figure 38. H-spice sim ulation result for SA-M FF

37

Fig. 39 and 40 show the sensing failure rate for SA-MFF and SPFS NV-FF, which is decreased by 40%.

Figure 39. Sensing failure rate for SPFS N V -FF

Figure 40. Sensing failure rate for SA-M FF

38

Fig. 33 and 34 show the setup time based on h-spice simulation for SPFS NV-FF and SA- MFF, which is increased in our design.

Figure 41. Setup time for SPFS NV-FF

Figure 42. setup time for SA-M FF

39

Fig. 43 and 44 show the hold time for SPFS NV-FF and SA-MFF. The hold time of SPFS NV-FF is decreased by 26.6 %.

Figure 43. hold tim e for SPFS N V -FF

Figure 44. hold time for SA-M FF

40

Chapter 6: Conclusion

In this thesis, a SPFS NV-FF for a nonvolatile data retention flip-flop is presented that can achieve near zero failure rate in writing and reading the data to/from the nonvolatile element. The proposed design utilizes a new concept of separated pre-charge feedback sensing for enhanced reliability of sensing the state of the non-volatile element. It also uses a 3-driver nonvolatile-elements-in-parallel write scheme for improved write reliability. The concept of proposed design is STT-MRAM technology where the nonvolatile elements are MTJs. The proposed design outperforms the conventional SA- MFF, which is state-of-the-art in nonvolatile data retention flip-flops.

In particular, the proposed design achieves improved results in PDP, sensing delay, failure rate, and hold time.

In write mode, the MTJs write delay, power, and energy are reduced by 89.8%, 84.2%, and 98.5%, respectively.

In flip-flop and sensing mode: 1) By considering the minimum area as a parameter for comparing two designs, the area, PDP, and sensing delay is reduced by 74.7 %, 65.6 %, and 69.3 %. 2) By considering the minimum PDP as a parameter for comparing two designs, the area, PDP, and sensing delay is reduced by 52.9 %, 68.8 %, and 62.7 %. 3) By considering the minimum sensing delay as a parameter for comparing the two designs, the area, PDP, and sensing delay is reduced by 48.5 %, 43.5 %, and 66.6 %.

41

References

[1] Swapnil s.Bhosale. STT-RAM: Survey of current and emerging trends [PowerPoint

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survey-29260872

[2] M. Keating, D. Flynn R. Aitken, A. Gibbons, and K. Shi, “Low Power Design

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[3] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, “A 1-V High-

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[7] T. Na, et. al. “A comparative Study of STT-MTJ Based Non-Volatile Flip-Flops,”

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[8] K. Ryu, et. al, “A Magnetic Tunnel Junction Based Zero Standby Leakage Current

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20, no. 11,2012

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[9] W. Zhao, et. al., “A Non-volatile Flip-Flop in Magnetic FPGA Chip,” International

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[10] Y. Lung, et. al., “An MTJ-based Non-Volatile Flip-FLop for High-Performance

SoC,” International Journal of Circuit Theory and Applications, vo. 42, no. 4, 2014

[11] Y. Jung, et. al., “MTJ Based Non-Volatile Flip-Flop in Deep Submicron

technology,” International SoC Design Conference, pp. 424-427, 2011

[12] A. S. Iyengar, S. Ghosh, and J.W. Jang, “MTJ-Based State Retentive Flip-Flop with

ENhanced-Scan Capability to Sustain Sudden Power Failure,” IEEE Transactions on

Circuits and Systems I, vol. 62, no. 8, 2015.

[13] S. Yamamoto, Y. Shuto, and S. Sugahara, “Nonvolatile Delay Flip-Flop using Spin-

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