Non-charge Storage Resistive Memory: How it works 6 Emerging...Non-charge Storage Resistive Memory: How it works ... RAM DISK TAPE 103-104 Latency gap ... SMTsympoisum-Japan_Bersuker_Final_no-anim.ppt
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Results obtained in collaboration with: SEMATECH: David Gilmer, Chanro Park, Dmitry Veksler, Paul KirschUniv. of Modena: L. Larcher groupUniv. College London: A. Shluger groupUniv. of Barcelona: M. Nafria group
Acknowledgement
2
10 June 2011 3
[1] W. Y. Choi, and T.-J. King Liu IEDM p. 603 (2007).[2] A. Driskill-Smith, Y. Huai Future Fab p. 28 (2007).[3] J. E. Green Nature v. 445 p. 414 (2007).[4] B. Yu IEEE Trans on Nanotech 7, p. 496 (2008).[5] Kryder, et. al. IEEE TRANS ON MAGNETICS, 45, NO. 10, (2009)
• MLC similar to NAND• $$ similar to NAND• Function, reliability = NAND• Density > NAND • Speed > NAND• RRAM, STT interesting.
0 10 20 30 40 50100
101
102
103
104
105
NW-PC
STT
NanowireMolecular
DRAM
PCFeRAM
NEMS SRAM
MRAM
NOR
low power (fJ/bit) mid power (pJ/bit) mid-hi power (low nJ/bit) high power (nJ/bit)
Switc
hing
Tim
e(r
ead+
writ
e) [n
s]
Density AF2
NAND
RR
Memory benchmarking
Success Criteria:
BL1
BL2
BL3
WL1 WL2 WL3
1F Unit cell = 4F2
small A = small cell
10 June 2011
Which space should RRAM target?
Latency (ns)101-102 106 109
4
CPU
100
RAM DISK TAPE
103-104
Latency gap
Conventional space:
Possible Space for RRAM:
• RRAM fills large latency gap between RAM and SSD
• Possible apps: 1) embedded RAM for logic, 2) storage class memory (data center), 3) NAND competitor.
10 June 2011
Which space should RRAM target?
Latency (ns)101-102 106 109
5
CPU
100
RAM DISK TAPE
CPU RAM DISK TAPE
103-104
Latency gap
Conventional space:
Possible Space for RRAM:
• RRAM fills large latency gap between RAM and SSD
• Possible apps: 1) embedded RAM for logic, 2) storage class memory (data center), 3) NAND competitor.
10 June 2011
Which space should RRAM target?
Latency (ns)101-102 106 109
6
CPU
100
RAM DISK TAPE
CPU RAM SCM SSD DISK TAPE
103-104
Latency gap
Conventional space:
Possible Space for RRAM:
• RRAM fills large latency gap between RAM and SSD
• Possible apps: 1) embedded RAM for logic, 2) storage class memory (data center), 3) NAND competitor.
10 June 2011
Which space should RRAM target?
Latency (ns)101-102 106 109
7
CPU
100
RAM DISK TAPE
CPU RAM SCM SSD DISK TAPE
103-104
Latency gap
RRAM
Conventional space:
Possible Space for RRAM:
• RRAM fills large latency gap between RAM and SSD
• Possible apps: 1) embedded RAM for logic, 2) storage class memory (data center), 3) NAND competitor.
10 June 2011
Filament-based RRAM: Bi-polar operation
RRAM switching involves formation and manipulation of conductive filament focus of this presentation
RESET
SET
Forming
HRS
LRS
X
8
10 June 2011
Why the filament-based HfO2 RRAM
• Expected advantages- scaling: limited by filament
dimensions- retention: high barrier for
spontaneous change of chemical bonds- speed: may require only limited
atomic movement- energy: changes in small dielectric
volume - fab-friendly material
• Challenges: forming is a random process- How to control CF - How to ensure uniformity
Need to understand mechanism
9
10 June 2011
Outline
• Dielectric morphology responsible for switching
• Electrically-active defects associated with morphology
• How Forming occurs: Role of active defects
• Properties of conductive filament determined by forming process
• Filament characteristics in high and low resistive states
Need to address the following questions:
10
10 June 2011
Dielectric properties: Correlation between morphology and electrical characteristics
topographycurrent
Leakage path and breakdown along/at grain boundaries
SiO2Si
HfO2
C-AFM
0 20 40 600.6
0.9
1.2
1.5
1.8
2.1 Topography Current
Position (nm)
Hei
ght (
nm)
1E-3
0.01
0.1
3.0
3.3
3.6I (nA
)0 0
0 20 40 60
0.6
0.9
1.2
1.5
1.8
2.1 Topography Current
Position (nm)
Hei
ght (
nm)
0.01
0.1
3.2
3.4
3.6
I (nA)
Breakdownspot
HfO2
11
10 June 2011
GB structure in HfO2
Conductive “sub-band” b
a
Conductive “sub-band” b
a
Vacancies form conductive sub-band along GB
Modeling grain boundaries in HfO2
(101)
(101)
1nm
(101)
(101)
1nm
O-vacancies diffuses and precipitate at GB
12
10 June 2011
Conduction via grain boundaries
1
10
0 1000 2000 3000t[s]J
/ Jfr
esh
T =375K,Vg =1.8V (un- interrupt)T =375K,Vg =1.8V (interrupted)
1
10
0 500 1000 1500t[s]
J / J
fresh
T=300K , V g=2VT=375K ,Vg=2VT=375K ,Vg=1.6VT=375K ,Vg=1.8V
1
10
0 1000 2000 3000t[s]J
/ Jfr
esh
T =375K,Vg =1.8V (un- interrupt)T =375K,Vg =1.8V (interrupted)
1
10
0 500 1000 1500t[s]
J / J
fresh
T=300K , V g=2VT=375K ,Vg=2VT=375K ,Vg=1.6VT=375K ,Vg=1.8V
V2++e V+
Leakage current via charged oxygen vacancies V+ :
Defect activation:
O-vacancy defect V2+
J.L. Lyons et al. Microel.Eng.2011
Statistical multi-phonon trap assisted tunneling model
e
e
e
V++eV0 V++e
Simulations: TiN/6nmHfO2/TiN
13
10 June 2011 14
Modeling RRAM operations: Forming
• Pre-forming current is grainboundaries driven
Forming
Forming
0.0 0.2 0.4 0.6 0.8 1.0VG[V]
Curr
ent D
ensit
y [A
/cm
2 ]25°C50°C75°C100°Csimulations
Erelax=1.19eVET=2.0-2.4eV
101
100
10-1
10-2
10-3
10-4
10-5
10-6
Fresh
10 June 2011
Forming: Power dissipation during TAT transport
h h e
e
Finite thermal resistor
Grain boundary
Heat flow
3D temperature calculation
Radial heat flow vanishes within 4-5 nm from GB
Phonon emission associated with electron trapping
HfO2
metal
metal
electrode
electrode
HfO2
15
10 June 2011
Simulation of Forming process
• Electron trapping generates phonons lead to higher T promotes generation of new defects
defect generation
h O
Dissociation coordinate
Fox
EactbFox
initial
kTFbEact
eFTG
),(
Defect generation by thermo-electrical stress
HfO2
e
16
10 June 2011
Forming process: vacancy generation along GB
averaged multiple GB
GB evolved into CF
Current during Forming process Temperature-vacancies map
eAbeVE
ps
act
g
905.4
100
Generation rate:
kTFbE
g
act
eFTG
0
1),(
Statistics of Forming voltages
anode
cathode
anode
anode anodecathode
cathode cathode
17
10 June 2011
-1.0 -0.5 0.00.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0 1 2 3 4 523456789
101112
Ano
de
Tem
pear
atur
e (x
100
o C)
Distance (nm)
=0.002 1/oC and mixed BC at electrods
=0.002 1/oC =0
Cat
hode
I (x1
0-4 A
)
Vg (V)
Reset Theory Ohmic
Reset: Filament reoxidation
Reset occurs when filament temperature is sufficient for oxidation
Temperature along CF
0 0(1 ( ))a T T
22
2 2 4T T B
=-(r - x/h (r - r ))
rId Tdx
0 02
T T B0
(1 ( ( ) ))(r - x/h (r - r ))
h
r ra T x TV I dx
0 0(1 ( ))a T T
22
2 2 4T T B
=-(r - x/h (r - r ))
rId Tdx
0 02
T T B0
(1 ( ( ) ))(r - x/h (r - r ))
h
r ra T x TV I dx
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5Voltage [V]
Curr
ent [
A]
10-3
10-4
10-5
10-6
10-7
FORMING
SETRESETOhmic
18
10 June 2011
High resistance state
• HRS requires ~ 0.9 nm dielectric barrier between injecting electrode and filament
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5Voltage [V]
Curr
ent [
A]
10-3
10-4
10-5
10-6
10-7
FORMING
SETRESET
Lines = modelSymbols = data
Ohmic
through barrier
TAT Ohmic transport
tbarr
0.0 0.2 0.4 0.6 0.8VG[V]
Curr
ent [
A]
25°C
75°C
100°C
Erelax=0.77eVET=2.4eV
10-4
10-5
10-6
10-7
Erel=0.7 eVET=1.6-2.6 eV
HRS state
19
10 June 2011
SET: Field-driven barrier breakdown
High field leads to breakdown of dielectric barrier
Field distribution around filament
-1 0 1 2 3 4 5 60
5
10
E, M
V/cm
Distance, nm
Anod
e
Cat
hodealong filament
axis
Away from filament
V=0.6V
Field distribution across cell
d
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5Voltage [V]
Curr
ent [
A]
10-3
10-4
10-5
10-6
10-7
FORMING
SETRESET
anode V = 0.6V
cathode
dielectric
filament
V=0
20
10 June 2011
0 1 2 3 4 5
5
10
15
20
25
30
Ano
de
Tem
pera
ture
(x10
0 o C)
Distance (nm)
Cat
hode filament
cathode
dielectric
SET: Temperature profile after barrier breakdown
High temperature/field leads to oxygen dissociation metallic filament propagates to electrode
dCF thermal conductivity: 0.12 W/KcmCF radius at the cathode: ~ 0.5 nm
(b)HfO 2
barrier
CFO-O-
HfO 2HfO 2
barrier
CFO-O-
(b)HfO 2
barrier
CFO-O-
HfO 2
barrier
CFO-O-
(c)HfO 2
barrier
CFO-O-
HfO 2
barrier
CFO-O-
(b)HfO 2
barrier
CFO-O-
HfO 2HfO 2
barrier
CFO-O-
HfO 2
barrier
CFO-O-
(b)HfO 2
barrier
CFO-O-
HfO2 CF
O-O -
dbarrier
21
10 June 2011
RRAM switching mechanismReset: filament tip oxidation
field-drivend
Set: barrier breakdown
temperature driven
O-
O-
V+ V-
In HRS: TAT via barrier traps
dO-
O-
V+V-
O-
O-
In LRS: Ohmic conduction
metal
dd
metal
metal
metal
22
10 June 2011
Summary
Switching is controlled by 3 major filament parameters: x-section, composition, barrier thickness