Nimish Sane 1 , John Ford 2 , Andrew Harris 3 , and Shuvra S. Bhattacharyya 1

Integrating Dataflow Modeling with the CASPER Toolflow for Design and Implementation of Tunable

Digital Downconverter

Nimish Sane1,John Ford2, Andrew Harris3, and Shuvra S. Bhattacharyya1

1 Dept. of Electrical and Computer Engineering, University of Maryland, College Park2 National Radio Astronomy Observatory, Green Bank

3 Dept. of Astronomy, University of Maryland, College Park

09/30/2009

Nimish Sane

CASPER Workshop 2009 2

Outline:

• Motivation• Dataflow modeling• Tunable Digital Downconverter application• Design approach• Integration with CASPER toolflow


Motivation: DSP systems

• Efficient design and implementation of DSP systems:– Model based design approach– Exposure to underlying model of computation– High-level platform-independent abstraction and

prototype


Motivation: Dataflow modeling

• Dataflow modeling used extensively for –– embedded systems for signal processing and

communication applications– electronic design automation

• Dataflow-oriented DSP design tools typically allow –– high-level application specification– software simulation– resource estimation– synthesis for hardware or software implementation

• Leverage growing body of research in dataflow models of computation to the field of astronomical signal processing


Dataflow-oriented tools:

• Ptolemy (UC Berkeley)• Advanced Design System (Agilent Technologies)• LabVIEW (National Instruments)• CAL• SysteMoc• PEACE• Compaan/Laura• OpenDF• DIF (Dataflow Interchange Format)


Dataflow modeling:

• Data-driven execution• Data = Sequence of tokens; token is a data sample

Dataflow graph: synchronous dataflow (SDF)

• Actor• FIFO Buffer• Consumption Rate• Production Rate• Schedule [(3 ((2 A) BD)) C]

A B C

D

1 2 1 3

2

2


Parameterized Cyclo-static dataflow (CSDF)

D[1 0 0 0]

Decimator (CSDF)D = 4; phase = 0

IN OUTA

11 1B

control

data output

D

1

1 [1, 0, 0, …, 0]1 x D

Use Parameterized DataflowModel (PDF)


Modeling Design Space

XPSDF

XPCSDF

Ex

pre

ss

i ve

po

we

r

Verification / synthesis power

XC, BDF, DDF

XSDF

XCSDF

XCSDF, SSDFMDSDF,

WBDF

X

CFDF


Core Functional Dataflow (CFDF):

• Restricted form of enable-invoke dataflow (EIDF)• Generalized DF model• Flexible and efficient prototyping• Natural description of actors for static and dynamic

DF models• Transformations from other DF models into CFDF• Actor specification

– enable function– invoke function– Set of modes


Actors in Functional DIF (Example: Switch)

Switch

control

out1

out2

in

Application Graph

1

1

1 1

1

1

[1,0]

[0,1]

Switch

1

1

[1,0]

[0,1]False

Output

TrueOutput

Control

Data

Switch Actor

Production & consumptionbehavior of switch modes

Mode

No. of tokens consumed

No. of tokens produced

Control Data True False

control 1 0 0 0

control_true 0 1 1 0

control_false 0 1 0 1

control

control_true control_false

Mode transition diagrambetween switch modes


CFDF representation of tunable decimator

Mode Transitions for Decimator (CFDF)

control

data output

D

1

1 [1, 0, 0, …, 0]1 x D

Each mode is annotated with number of tokens consumed from control and data inputs, and that produced on to the output

D = 4

D = 3


DIF based design flow

The DIF Package

Dataflow M odels

DIF Front-end

Dataflow -basedDSP DesignTools

AutocodingToolsetPtolem y II

OtherTools

Em beddedProcessingPlatform s

Java OtherEm beddedPlatform sJava VM

DIF SpecificationsDIF Language

Static

SDF

CSDFHSDF

DSP DesignsM DSDF

Im age/Video

Signal Proc

Ada

VDM

Algorithm s

DIF-to-C

C

DSPs

AIF / Porting

DIF Spec

DIF Representations

Other Ex/Im

DIF Spec

SPG NM O M L

DIF-Ptolem y Ex/Im

M eta-M odeling

BLDFPDF

Dynam ic

DIF BDF

Com m Sys

DIF-AT Ex/ImDSP

Libraries

TI

VSIPL

Other


Approach:


Target application: Tunable digital downconverter (TDD)

• Part of Green Bank Ultimate Pulsar Processing Instrument (GUPPI), NRAO, Green Bank

• Observing at narrow bandwidths– With same number of channels, this allows finer

spectroscopy– Downsampling the input signal to Nyquist rate for the

chosen (narrow) BW

• Tunable digital downconverter (TDD)– Support various TDD configurations– Support tuning without re-synthesizing the hardware


Block Diagram of Backend with TDD

To downstreamsignal processingunits

8-bit ADC(Sampling + Quantization)

Downconverter+

Mixer

Band-width

CenterFrequency

Clock800 MHz

BasebandInputBW = 800 MHz

8 output lines**200 MS/s each

XAUI_0*

XAUI_1*

*XAUI : 10x Auxiliary User Interface port for streaming data over CX4 connectors of BEE2 and iBOB boards, with maximum data transfer capability of 10 Gbps.

To downstreamsignal processingunits

8-bit ADC(Sampling + Quantization)

Downconverter+

Mixer

Band-width

CenterFrequency

Clock800 MHz

BasebandInputBW = 800 MHz XAUI_0*

XAUI_1*

*XAUI : 10x Auxiliary User Interface port for streaming data over CX4 connectors of BEE2 and iBOB boards, with maximum data transfer capability of 10 Gbps.

** Each output line of ADC block has underlying 8 lines that output 8 bits in parallel

÷ 4


Design specifications for TDD:

• Input:

– 800MHz baseband signal sampled at 1.6 GS/s, available over 8 ADC output lines

– Each ADC output carries 200 MS/s, where each sample is 8-bit fixed point number.

• Output:

– Downsampled signal of pre-selected bandwidth and pass-band, to be fed to XAUI ports


Design specifications for TDD:

• Parameters:– Bandwidth (BW) and center frequency (CF) of the band– User specified– Parameters, once set by the user (observer), remain

constant for a given observation session– BW may take values in the set {20, 40, 50, 80, 100, 200,

400, 64, 128, 240} MHz– Choice of CF will depend upon the BW, and possible values

of CF for a given BW would ensure that entire spectrum is covered along with some overlap between the bands

• Hardware Platform:– iBOB


Tunable Digital Downconverter:

*parameters which affect the functional behavior of the block8 lines each of 8-bit each

ADC output8 lines200 MS/seach

fLO

(CF)*

Mixer

To XAUI Ports

SampleRate

Conv-erter(BW)*

Mixer

fLO

(CF)*

BPF(BW, CF)*

Switch(CF)*

BPF(BW, CF)*

Switch(CF)*

Select(CF)* Select

(CF)*

if output is baseband Baseband output


Functional DIF Prototype:

• CFDF with PCSDF and PSDF as underlying dataflow models

• Canonical scheduling– Simulation– Functional verification– Buffer sizes in terms of number of tokens

Sample Rate Converter

1/5phase = 0{ }4

inputs

4outputs

[1 0 0 0 0]1

1

1

1

[0 1 0 0 0]

[0 0 1 0 0]

[0 0 0 1 0]


TDD in Functional DIF


Integration with CASPER toolflow/ Implementation in Simulink:

• Emulating dataflow semantics in Simulink/Xilinx System Generator (XSG)

• Developing actors/blocks currently not supported in XSG/CASPER/BEE_XPS libraries

• Supporting parameterization without the need for synthesizing hardware each time the configuration of TDD changes


Emulating Dataflow Semantics in Simulink/XSG:• Actors (Nodes) in DF graph

Functional Simulink blocks– enable function: to determine whether

the actor can be fired– invoke function: the actual

functionality of the block• Edges in DF graph FIFO blocks in

Simulink model– Size– Peek number of tokens in the buffer– Blocking read semantics– Implementation: dual port RAM

block + wrapper to provide above features


Parameterization for Simulink blocks:

• Pre-synthesis– Parameterized subsystems with possible

redrawing of underlying blocks– Masked subsystems with mask scripting

• Post-synthesis– Support for tuning TDD parameters during run-

time– Choice of frequency band determines parameters

for underlying blocks– Use of software registers and PowerPC


Conclusion:

• Dataflow model based high-level application specification for– platform-independent prototype– functional simulation and verification– analysis (e.g. buffer sizes in terms of number of tokens)– benchmark for targeted platform-specific implementations

• Integrating DIF based design approach with the CASPER toolflow– Porting DIF based prototype to Simulink/XSG– Emulating DF semantics in Simulink– Supporting parameterized actor blocks

• Design is being currently integrated with the existing version of GUPPI


Unit-testing:

• DSPCAD Integrative Command-line Environment (DICE)– Cross-platform framework for unit-testing– DICELANG plug-ins for application language-

specific project development (C, Java, Verilog, etc.)

– Test – Fail – Edit – Compile – Test methodology


Future work:

• Using more efficient scheduling techniques and porting them to FPGA based platforms

• Automated mapping of application-specification to platform-specific implementation


Acknowledgement:

• Randy McCullough, NRAO, Green Bank• Jason Ray, NRAO, Green Bank• Shilpa Bollineni, NRAO, Green Bank• Scott Ransom, NRAO, Charlottesville• Electronics and software divisions, NRAO,

Green Bank


References:

[1] E. A. Lee and D. G. Messerschmitt, “Static scheduling of synchronous dataflow programs for digital signal processing”, in IEEE Transactions on Computers, 1996.

[2] G. Bilsen, M. Engels, R. Lauwereins, and J. A. Peperstraete, “Cyclo-static dataflow”, in IEEE Transactions on Signal Processing, 1996, 44 (2), 397–408.

[3] B. Bhattacharya and S. S. Bhattacharyya, “Parameterized dataflow modeling of DSP systems”, in Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, 2000, pp. 1948–1951, Istanbul, Turkey.

[4] W. Plishker, N. Sane, M. Kiemb, K. Anand, and S. S. Bhattacharyya, “Functional DIF for rapid prototyping”, in Proceedings of the International Symposium on Rapid System Prototyping, Jan 2008, pp. 17–23, Monterey, California.

Nimish Sane 1 , John Ford 2 , Andrew Harris 3 , and Shuvra S. Bhattacharyya 1

Documents

casper workshop

casper toolflow

design flow

design specifications

datafloworiented tools

modeling design space

dsp systemsefficient

dataflow models of computation