NHẬN DIỆN BIỂN SỐ XE BẰNG KIT DE2 DÙNG NIOS II

I HC QUC GIA TP.H CH MINH TRNG I HC BCH KHOA

KHOA IN IN T

B MN IN T ---------------o0o---------------

LUN VN TT NGHIP I HC

NHN DIN BIN S XE BNG KIT DE2

DNG NIOS II

GVHD: THS.H TRUNG M

SVTH: DNG THIN L

MSSV: 40901520

TP. H CH MINH, THNG 12 NM 2013

I HC QUC GIA TP.H CH MINH CNG HA X HI CH NGHA VIT NAM

TRNG I HC BCH KHOA c lp T do Hnh phc.

---------- ---------- S: ______ /BKT Khoa: in in t B Mn: in T

NHIM V LUN VN TT NGHIP

1. H V TN : MSSV:

2. NGNH: IN T - VIN THNG LP :

3. ti:

4. Nhim v (Yu cu v ni dung v s liu ban u):

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5. Ngy giao nhim v lun vn: ...............................

6. Ngy hon thnh nhim v: ...................................

7. H v tn ngi hng dn: Phn hng dn

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Ni dung v yu cu LVTN c thng qua B Mn.

Tp.HCM, ngy... thng.. nm 20 CH NHIM B MN NGI HNG DN CHNH

PHN DNH CHO KHOA, B MN: Ngi duyt (chm s b):....................... n v:...................................................... Ngy bo v : ........................................... im tng kt: ......................................... Ni lu tr lun vn: ...............................

Li cm n GVHD:

i

LI CM N

Trong qu trnh thc hin lun vn tt nghip ny em nhn c nhiu s

gip t ging vin hng dn ngi cung cp cho em nhng ti liu qu bu.

V vy em xin chn thnh cm n thy H Trung M xut v hng dn em thc

hin ti ny

Em cng gi li cm n ti tt c thy c trong khoa in, c bit l b mn

in t, trng i hc Bch Khoa H Ch Minh tn tnh hng dn em trong 4

nm hc va qua, gip em c kin thc v kinh nghim thc hin ti tt

nghip ln ny.

Em xin gi li cm n ti gia nh ch da vng chc cho em trong nhng

lc kh khn v to iu kin tt nht em hc tp.

Em tham kho rt nhiu bi vit (c lit k trong danh mc tham kho)

trn mng internet v ti ny, cng nh cc ti lin quan trong lnh vc x l

nh. Em xin chn thnh cm n tc gi cc bi vit . Bi bo co ny cng xem nh

l s tng hp kinh nghim m em tch ly c trong qu trnh c v thc hnh cc

gii thut.

Bin Ha, ngy 24 thng 12 nm 2013 .

Sinh vin

Lun vn tt nghip GVHD: THS. H Trung M

ii

TM TT LUN VN

Lun vn ny trnh by v ti:

NHN DIN BIN S XE BNG KIT DE2 DNG NIOS II

Vic thc hin lun vn bao gm hai phn chnh:

S dng cc th vin trong SOPC Builder xy dng phn cng cho chng

trnh. CPU x l s dng NIOS II

Vit code C thc hin chng trnh nhn din bin s xe trn core NIOS II.


iii

MC LC

1. GII THIU ....................................................................................................................... 1

1.1. Tng quan ..................................................................................................................... 1

1.2. Tnh hnh nghin cu trong v ngoi nc ................................................................... 1

1.3. Nhim v lun vn ........................................................................................................ 1

2. L THUYT ....................................................................................................................... 2

2.1. Chng 1: SOPC Builder v Nios II Software Build tool for Eclipse .......................... 2

SOPC Builder: ...................................................................................................... 2

Cc bc thit k mt h thng SOPC builder ..................................................... 7

Nios II Software Build Tools for Eclipse: .......................................................... 12

2.2. Chng 2: Cc k thut x l nh .............................................................................. 18

M hnh nh mu RGB: ..................................................................................... 18

nh xm (gray image): ....................................................................................... 19

nh dng nh BMP: .......................................................................................... 20

Pht hin cnh: ................................................................................................... 22

Bin i Hough: ................................................................................................. 25

Xoay nh: ............................................................................................................ 27

Resize nh: .......................................................................................................... 30

Phng php SVM: ............................................................................................ 34

Bi ton nhn din ch quang hc: .................................................................... 38

3. THIT K V THC HIN PHN CNG ................................................................ 47

3.1. Yu cu thit k........................................................................................................... 47

3.2. S khi tng qut ca h thng: ............................................................................. 48

Gii thch s : ................................................................................................. 48


iv

3.3. Chi tit thit k: ........................................................................................................... 50

CPU: ................................................................................................................... 50

Clock Signal ....................................................................................................... 51

Character buffer for VGA display ...................................................................... 51

Pixel Buffer ........................................................................................................ 52

Pixel Buffer DMA Controller ............................................................................. 52

RGB Resampler .................................................................................................. 53

Scaler .................................................................................................................. 53

Alpha Blender ..................................................................................................... 54

Dual Clock FIFO: ............................................................................................... 54

VGA Controller .............................................................................................. 55

Jtag Uart .......................................................................................................... 56

SDRAM Controller ......................................................................................... 56

Giao tip b nh Flash: ................................................................................... 57

Parallel Port ..................................................................................................... 59

16x2 Character Display .................................................................................. 60

3.4. Kt qu thit k h thng: ........................................................................................... 62

4. THIT K V THC HIN PHN MM .................................................................. 63

4.1. Yu cu t ra cho phn mm ..................................................................................... 63

4.2. Phn tch ...................................................................................................................... 63

Load nh ............................................................................................................. 63

Tin x l ............................................................................................................ 69

Tch bin s: ....................................................................................................... 69

Nhn dng k t ................................................................................................. 72

Giao din ngi dng: ........................................................................................ 74


v

5. KT QU THC HIN .................................................................................................. 78

5.1. Cch thc o c, th nghim..................................................................................... 78

5.2. Gii thch v phn tch v kt qu thu c ................................................................ 78

Kt qu thu c: ............................................................................................... 78

Khuyt im ca ti ....................................................................................... 79

6. KT LUN V HNG PHT TRIN ...................................................................... 80

6.1. Kt lun ....................................................................................................................... 80

6.2. Hng pht trin ......................................................................................................... 80

7. TI LIU THAM KHO ................................................................................................ 81

8. PH LC .......................................................................................................................... 83


vi

DANH SCH HNH MINH HA

Hnh 2-1 V d v mt h thng Nios thc hin trn kit DE2 bng SOPC builder. ....... 3

Hnh 2-2 S block diagram ca core Nios II ............................................................. 4

Hnh 2-3 T chc b nh v I/O ca Nios II .................................................................. 5

Hnh 2-4 Cc phin bn ca NIOS II ............................................................................. 7

Hnh 2-5 Cc bc thit k h thng SOPC ................................................................... 7




Hnh 2-9 Cc bc thit k h thng SOPC ................................................................. 10

Hnh 2-10 Cc bc thit k h thng SOPC ............................................................... 10




Hnh 2-14 Cc bc thc hin Nios II Software .......................................................... 13

Hnh 2-15 Cc bc thc hin Nios II Software .......................................................... 14

Hnh 2-16 Kt qu bin dch chng trnh Nios Demo ................................................ 15

Hnh 2-17 chng trnh bin dch t Quartus xung FPGA .............................. 16

Hnh 2-18 Kt qu chy chng trnh Nios .................................................................. 17

Hnh 2-19 Minh ha m hnh mu RGB ...................................................................... 18

Hnh 2-20 nh xm ...................................................................................................... 20

Hnh 2-21 nh trc v sau khi pht hin cnh ........................................................... 22

Hnh 2-22 b) Sobel. c)Prewitt. d) Robert. e)Laplacian. f)LoG .................................. 25

Hnh 2-23 Ma trn nh v ma trn Hough .................................................................... 26

Hnh 2-24 Minh ha vic xoay nh mt gc a ............................................................. 27

Hnh 2-25 Xoay im N quanh gc O mt gc a s c im M .............................. 28

Hnh 2-26 Kt qu xoay nh ca phng php Forward Mapping .............................. 29

Hnh 2-27 Cc bc i ta nh [4] ........................................................................ 30

Hnh 2-28 nh ban u ................................................................................................ 33

Hnh 2-29 nh resize theo phng php im ln cn gn nht .................................. 33

Hnh 2-30 nh resize theo phng php bilinear ........................................................ 34

Hnh 2-31 nh resize theo phng php bicubic ......................................................... 34

Hnh 2-32 Gi s c hai nhm d liu hun luyn cn phn lp bit trc xi, yi ........ 36

Hnh 2-33 Cu hi t ra l siu phng no l tt nht? p1,p2 hay p3? ....................... 36

Hnh 2-34 Xy dng cc siu phng l l ca cc lp, cc mu nm trn l l vector

ta (Support Vector) ................................................................................................................. 37

Hnh 2-35 Siu phng phn lp cch u hai siu phng l. ........................................ 37

Hnh 2-36 Hnh chiu ngang v chiu dc ca mt on k t. .................................. 43

Hnh 2-37 a. OVR b.OVO c.DAG................................................................................ 45

Hnh 3-1 S khi h thng c thit k bng SOPC ............................................. 48

Hnh 3-2: ch mu ca VGA ................................................................................... 49


vii

Hnh 3-3: Frame hnh hin th ln VGA ....................................................................... 49

Hnh 3-4 Cch nh a ch cho pixel hin th .............................................................. 49

Hnh 3-5 Thng s chn CPU ...................................................................................... 50

Hnh 3-6 Thng s cu hnh cho Clock Signals ........................................................... 51

Hnh 3-7 Thng s cu hnh cho character buffer for VGA display ............................ 52

Hnh 3-8 Thng s cu hnh cho SRAM Controller ..................................................... 52

Hnh 3-9 Thng s cu hnh Pixel Buffer DMA Controller ......................................... 53

Hnh 3-10 Thng s cu hnh RGB Resampler ............................................................ 53

Hnh 3-11 Thng s cu hnh Scaler ............................................................................ 54

Hnh 3-12 Thng s cu hnh Alpha Blender ............................................................... 54

Hnh 3-13 Thng s cu hnh Dual Clock FIFO .......................................................... 55

Hnh 3-14 Thng s cu hnh VGA Controller ............................................................ 55

Hnh 3-15 Thng s cu hnh JTAG UART................................................................. 56

Hnh 3-16 Thng s cu hnh SDRAM Controller ...................................................... 57

Hnh 3-17 Cu hnh khi Tristate Bridge ..................................................................... 58

Hnh 3-18 Cu hnh khi Flash Memory Interface....................................................... 58

Hnh 3-19 Thng s timing ca CFI ............................................................................. 59

Hnh 3-20 Thng s cho Parallel Port kt ni vi Slider Switches. ............................. 59

Hnh 3-21 Thng s cu hnh cho Parallel Port kt ni vi Buttons. ........................... 60

Hnh 3-22 Thng s cu hnh cho khi giao tip LCD ................................................ 61

Hnh 3-23 Kt qu thit k SOPC ca h thng ........................................................... 62

Hnh 3-24 a ch cc vng nh ca h thng ............................................................. 62

Hnh 4-1 Cc bc load nh vo b nh Flash. ........................................................... 64

Hnh 4-2 Qu trnh phn on k t ............................................................................. 73

Hnh 4-3 Cch nh a ch mng mt chiu ................................................................ 74

Hnh 4-4 Cch nh a ch trong character buffer ....................................................... 75

Hnh 4-5 a ch cc thanh ghi ca LCD ..................................................................... 76

Hnh 4-6 Cch nh a ch v tr trn mn hnh LCD .................................................. 76

Hnh 5-1 nh u vo .................................................................................................. 78

Hnh 5-2 nh chp mn hnh VGA sau khi nhn dng................................................ 79


viii

DANH SCH BNG S LIU

Bng 2-1 nh dng file nh BMP ............................................................................... 22

Bng 4-1 m lnh ca LCD .......................................................................................... 76


1

1. GII THIU

1.1. Tng quan

Trong nhng nm gn y k thut x l nh ang pht trin mnh m. Ngy cng

nhiu ng dng lin quan n x l nh trong nhiu lnh vc ca cuc sng: cng ngh thng

tin, h thng nhng. Cc nghin cu v h thng SOPC thng c ng dng th nghim

h thng trc khi i vo ch to thc t.

Lun vn s dng cc gii thut x l nh c bn nhn din bin s xe trn h

thng SOPC ca ALTERA.

1.2. Tnh hnh nghin cu trong v ngoi nc

ti: nhn din bin s xe l ti khng mi. N c nghin cu v hon

thin, c ng dng rng ri trong v ngoi nc. ng dng ca ti:

o Qun l xe ra vo bi gi xe

o Nhn din bin s ca xe vi phm lut giao thng trn ng

o a vo h thng chn xe cc trm thu ph

o

Tuy ti khng mi nhng vic nghin cu cc ti ny trn h thng SOPC cha

nhiu. Vic nghin cu thit k h thng v lp trnh vi x l t cp n gin nht l tin

nghin cu cc ng dng x l nh khc vi tc v s phc tp hn na.

1.3. Nhim v lun vn

Ni dung 1: Tm hiu cch s dng phn mm Quartus v Nios II Software Build

Tool for Eclipse thit k h thng SOPC trn vi x l NIOS

Ni dung 2: Tm hiu cc gii thut x l nh cn bn

Ni dung 3: Xy dng h thng SOPC cho ti

Ni dung 4: Thit k gii thut cho qu trnh nhn din bin s xe

Ni dung 5: Xy dng phn mm hon chnh cho h thng


2

2. L THUYT

2.1. Chng 1: SOPC Builder v Nios II Software Build tool for Eclipse

SOPC Builder:

SOPC Builder l mt cng c thit k h thng ca ALTERA c tch hp trong

phn mm Quartus II. SOPC Builder c dng to ra mt h thng hon chnh trn FPGA

(System on a Programmable Chip-SOPC) mt cch nhanh chng.

Thng thng khi s dng SOPC Builder ngi ta thng dng vi x l NIOS II c

xy dng sn trong th vin. Nhng SOPC Builder l cng c to h thng s dng hoc

khng s dng vi x l. Bn cng c th s dng vi x l khc lp trnh phn mm

SOPC Builder t ng thit k cc thnh phn(components) phn cng cho h thng

theo bn. Trong phng php thit k truyn thng, bn phi t vit m VHDL hoc

Verilog thit k cc thnh phn phn cng hoc ni dy cho cc thnh phn ca h thng.

Vi SOPC Builder bn c th d dng c t cc thnh phn vi GUI ca chng trnh. V

SOPC Builder s t ng to ra m HDL ca thnh phn v ni dy bn trong h thng.

Bn ch cn vit file top-level HDL ni dy bn ngoi h thng: ni cc h thng vi nhau,

ni h thng vi cc linh kin hoc tn hiu thc trn kit DE2.

Cc thnh phn c sn trong th vin SOPC:

Vi x l Nios II

Cc ngoi vi ca vi x l nh: DMA controller v timer

Giao din truyn ni tip nh: UART, SPI(serial peripheral interface)

Cc I/O thng thng

Thit b lin lc ngoi vi nh 10/100/1000 Ethernet MAC

Giao tip vi thit b off-chip

Ngoi cc thnh phn c sn trong th vin, ngi dng c th t thit k thm cc

thnh phn mi bng ngn ng HDL ri a vo h thng SOPC


3

Hnh 2-1 V d v mt h thng Nios thc hin trn kit DE2 bng SOPC builder.

Cc thnh phn c thit k trn chip Cyclone II c gi l on-chip

Cc thnh phn phn nh SRAM, SDRAM, Flash c gi l b nh off-chip

Gii thiu v vi x l Nios II:

Nios II l mt b x l nhng c thit k c bit cho chip FPGA ca Altera. Nios

II kt hp nhiu ci tin hn so vi kin trc Nios ban u ph hp hn vi s a dng ca

cc ng dng nhng: t DSP ti h thng iu khin

Nios II c th c s dng cho cc cell ASIC tiu chun thng qua nh cung cp IP

th ba, Synopsys. Thng qua giy php (license), ngi thit k c th xut thit k Nios t

nn tng FPGA sang sn xut hng lot cc thit b ASIC.

Nios II l th h tip theo b x l th h u ca Altera (cu hnh 16 bit) l Nios.

Nios II l mt core x l thng thng dng RISC vi cc c tnh:

Tp lnh, data path, ng a ch 32 bit

C 32 thanh ghi a dng


4

C 32 ngun ngt

C b iu khin ngt ngoi

Lnh n nhn v chia thc hin trn 32 bit v kt qu to ra 32 bit

Lnh dnh ring cho kt qu nhn 64 bit v 128 bit

Lnh thc hin cc php tnh du chm ng vi chnh xc n

Lnh n cho php ton dch

Truy cp cc thit b ngoi vi on-chip, b nh off-chip v cc ngoi vi khc

nhau

Cung cp mi trng phn mm GNU (General Public License) da trn

C/C++ v Nios II Software Build Tools (SBT) for Eclipse.

Hiu sut ln ti 250 DMIPS

Cu trc core x l Nios II

Hnh 2-2 S block diagram ca core Nios II

T chc b nh v I/O:

T chc b nh v I/O do ngi dng ty chnh nn n khc nhau cc thit k khc

nhau.


5

Mt core x l Nios II dng mt hay nhiu cch di y truy xut b nh v I/O

Instruction master port

Instruction cache- b nh cache nhanh nm bn trong core Nios

Data master port

Data cache-b nh cache nhanh nm trong core Nios

Tightly-coupled instruction or data memory port

Hnh 2-3 T chc b nh v I/O ca Nios II

Instruction v Data Buses:

Nios II c kin trc theo kiu Harvard cung cp hai ng bus d liu v bus chng

trnh ring bit. C hai loi bus ny u theo chun AVALON-MM Master port. Data Master

port kt ni vi c b nh d liu v cc thit b ngoi vi, cn Instruction Master port kt ni

vi cc b nh lnh

Instruction Master Port:


6

Bus chng trnh ca h thng theo chun 32 bit Avalon MM master port. Master

port chng trnh thc hin chc nng duy nht l tm np lnh.

Kin trc Nios cung cp b nh Cache chng trnh qu trnh tm np lnh din ra

nhanh hn

Data Master Port:

Nios II c Bus d liu theo chun 32 bit Avalon-MM master port. Master port d liu

thc hin hai chc nng:

c d liu t ngoi vi hoc b nh khi b x l thc hin lnh load

Ghi d liu ra ngoi vi hoc b nh khi b x l thc hin lnh write.

Kin trc Nios II cung cp b nh cache d liu ci thin tc c v ghi d liu.

Cc loi b nh ca Nios II:

B nh Cache:

Kin trc Nios cung cp b nh cache cho c master port chng trnh v master port

d liu. B nh Cache l on-chip v l mt phn ca core x l Nios II. B nh cache ci

thin thi gian truy xut b nh cho cc h thng s dng b nh off-chip nh SDRAM.

B nh Cache l ty chn, mt core x l c th c mt, hai hoc khng c b nh

cache no, kch thc ca b nh cache cng do ngi thit k quyt nh. Ngi thit k

phi nh i gia kch thc core x l v dung lng b nh cache

B nh ghp (tighty couple memory)

B nh c truy xut qua h thng Bus Avalon, l mt loi b nh on-chip, nhng

khng nm trong core x l. C th c mt hay nhiu b nh ghp. Nu h thng khng c b

nh Cache th cn t nht mt b nh ghp

B nh off-chip:

B nh off-chip l cc b nh hoc ngoi vi khng nm trn chip FPGA, n gm cc

loi nh: SRAM, SDRAM, FLASH,..N c truy xut thng qua cc thnh phn trung gian

ng vai tr giao din (interface) gia core x l v b nh. Tc truy xut ca b nh off-

chip nh hn b nh on-chip

Cc phin bn ca core Nios II:

Nios II /f : l b x l fast c thit k cho cc ng dng hiu sut cao. C nhng

ty chn cu hnh cao m khng c trong cc phin bn Nios II cn li

Nios II/s: l b x l standard c thit k vi kch thc nh trong khi vn duy tr

hiu sut va phi.


7

Nios II/e: l b x l economic c thit k vi kch thc nh nht vi hiu sut

thch hp.

Hnh 2-4 Cc phin bn ca NIOS II

Cc bc thit k mt h thng SOPC builder

Thc hin thit k h thng SOPC theo cc bc sau [1]:

To mt project thng thng trn phn mm Quartus, s dng chip Cylone II

EP2C35F672C6

Vo nhn Tool>SOPC Builder, chng trnh s hin ra ca s nh hnh. t

tn cho h thng ca mnh, chn ngn ng HDL s dng ri bm OK.

Hnh 2-5 Cc bc thit k h thng SOPC


8


Ca s nh hnh 2-6 c hin ra

Ty theo mc ch thit k m ngi dng chn cc thnh phn trong th vin

bn tay phi add vo h thng.

y em lm mt v d xy dng h thng SOPC n gin nht nh sau:

Trong danh sch th vin bn tay phi chn mc Processors>Nios II

Processor , mt ca s mi hin ra nh hnh 2-8.

y l ca s chn cc thng s cho vi x l Nios II, y em chn

phin bn Nios n gin nht l Nios II/e. Sau chn Finish. (Cc tab

pha sau c th c iu chnh theo ngi dng nu cn)

Chn b nh chng trnh nh hnh 2-9. Ri bm Finish

Chn thm thnh phn JTAG UART nh hnh 2-10 .Sau bm

Finish

Tr li mc Nios II Processor chnh li Reset Vector v Exception

Vector nh hnh


9




10




11


Cui cng Save ri bm Generate nh hnh di:



12

Sau khi generate, ta vo file thienly.v th mc cha Project xem cc tn hiu

in/out ca h thng. Hoc c th coi trong file thienly Quartus II Block Symbol File cng

trong th mc xem s chn.

H thng SOPC sau khi c to thnh s c s chn nh sau:

Hnh 2-13 Cc bc thit k h thng SOPC Trong Project vidu to trn ta to mt file Verilog nh sau:

Trong thienly l tn h thng SOPC ta t bc u thit k SOPC.

Save file v bin dch Project ny.

Nios II Software Build Tools for Eclipse:

Vit phn mm cho core x l Nios II cng tng t nh cc b x l nhng khc.

Nios II Software Build Tools for Eclipse hay cn gi l Nios II SBT for Eclipse l mt mi

trng pht trin vit m, bin dch, np v debug chng trnh cho b x l xy dng

bc trn.

Cc bc xy dng phn mm cho b x l:

Click vo biu tng ca phn mm ci t trn my

Chn ng dn n th mc bt k mong mun to project ri bm OK


13

Hnh 2-14 Cc bc thc hin Nios II Software Chn File>New>NiosII Application and BSP from Template


14

Hnh 2-15 Cc bc thc hin Nios II Software

Chn ng dn ca SOPC Information file name nh hnh

t tn cho Project name

khung Template thng thng chn Blank Project vit chng trnh theo mun ca

ngi thit k.

Chn Finish.

To file source c t tn l main.c (tn do ngi vit t)


15

Vit code c vo file ny ri click chut phi vo th mc c tn soft (tn t cho project

bc trn) ca s st tay tri, chn Build Project.

Kt qu bin dch nh di l ng

Hnh 2-16 Kt qu bin dch chng trnh Nios Demo

Tr li ca s ca chng trnh Quartus, chn th Programmer>Start

Nu np chng trnh trn Quartus thnh cng th tr li chng trnh Nios. Sau click

chut phi vo th mc soft ri chn Run As>Nios II Hardware


16

Hnh 2-17 chng trnh bin dch t Quartus xung FPGA

Kt qu chy nh hnh


17

Hnh 2-18 Kt qu chy chng trnh Nios


18

2.2. Chng 2: Cc k thut x l nh

M hnh nh mu RGB:

Khi nim:

M hnh mu RGB trong nh sng , xanh l cy v xanh lam c t hp vi

nhau theo nhiu phng thc khc nhau to thnh cc mu khc. T vit tt RGB trong

ting Anh c ngha l (red), xanh l cy (green) v xanh lam (blue), l ba mu gc trong

cc m hnh nh sng b sung. [2]

Hnh 2-19 Minh ha m hnh mu RGB

C s sinh hc:

Cc mu gc c lin quan n cc khi nim sinh hc hn l vt l, n da trn c s

phn ng sinh l hc ca mt ngi i vi nh sng. Mt ngi c cc t bo cm quang c

hnh nn nn cn c gi l t bo hnh nn, cc t bo ny thng thng c phn ng cc

i vi nh sng vng - xanh l cy (t bo hnh nn L), xanh l cy (t bo hnh nn M) v

xanh lam (t bo hnh nn S) tng ng vi cc bc sng khong 564 nm, 534 nm v

420 nm. V d, mu vng thy c khi cc t bo cm nhn mu xanh nh vng c kch

thch nhiu hn mt cht so vi t bo cm nhn mu xanh l cy v mu cm nhn c

khi cc t bo cm nhn mu vng - xanh l cy c kch thch nhiu hn so vi t bo cm

nhn mu xanh l cy.

Mc d bin cc i ca cc phn x ca cc t bo cm quang khng din ra cc

bc sng ca mu "", "xanh l cy" v "xanh lam", ba mu ny c m t nh l cc

mu gc v chng c th s dng mt cch tng i c lp kch thch ba loi t bo cm

quang.

sinh ra khong mu ti u cho cc loi ng vt khc, cc mu gc khc c th

c s dng. Vi cc loi vt c bn loi t bo cm quang, chng hn nh nhiu loi chim,


19

ngi ta c l phi ni l cn ti bn mu gc; cho cc loi vt ch c hai loi t bo cm

quang, nh phn ln cc loi ng vt c v, th ch cn hai mu gc.

RGB v hin th:

Mt trong nhng ng dng ph bin nht ca m hnh mu RGB l vic hin th mu

sc trong cc ng tia m cc, mn hnh tinh th lng hay mn hnh plasma, chng hn nh

mn hnh my tnh hay ti vi. Mi im nh trn mn hnh c th c th hin trong b nh

my tnh nh l cc gi tr c lp ca mu , xanh l cy v xanh lam. Cc gi tr ny c

chuyn i thnh cc cng v gi ti mn hnh. Bng vic s dng cc t hp thch hp

ca cc cng nh sng , xanh l cy v xanh lam, mn hnh c th ti to li phn ln

cc mu trong khong en v trng

Phn ln cc mn hnh my tnh trn th gii s dng RGB.

Cc nh dng pixel theo kiu RGB thng gp:

16 bit RGB:

24 bit RGB:

30 bit RGB

16 bit RGBA

RGB 32 bit:

nh xm (gray image):

nh xm l nh ch c mt mu vi nhiu cng xm khc nhau nm trn thang

xm (grayscale). Vi nh xm 8 bit, thang xm c tt c 256 mc khc nhau.


20

Hnh 2-20 nh xm

Chuyn i t nh dng RGB sang Gray:

= 0.299 + 0.587 + 0.114

Vi R, G, B l cng ca pixel trong nh RGB.

Y l cng pixel trong nh xm.

nh dng nh BMP:

nh dng file BMP l mt loi file nh bitmap (biu din nh bng mng cc bit) l

mt nh dng dng lu tr nh s khng nn.

nh dng ny dng lu thng tin ca nh s 2D vi nhiu dng khc nhau v

phn gii, nh mt mu hay nh RGB, su ca mu khc nhau (s bit biu din mu).

Cu trc mt file BMP gm 4 phn sau:

Bitmap Header (14 byte): gip nhn dng mt tp tin bitmap

Bitmap Information (40 bytes): lu mt s thng tin chi tit gip hin th nh. C

th l DIB Header hoc BITMAPINFOHEADER

Color Palette (4*x bytes), x l s mu ca nh: nh ngha cc mu s c s dng

trong nh.

Bitmap Data: lu d liu nh.

C nhiu phin bn c s dng lu tr nh bmp khc nhau. Nhng tt c u c

cc trng chung sau y.

Bitmap Header

offset size Tn M t

0000h 2 bytes Signature Dng nhn dng cch lu tr:


21

BM Windows 3.1x, 95, NT, ... etc.

BA OS/2 struct Bitmap Array

CI OS/2 struct Color Icon

CP OS/2 const Color Pointer

IC OS/2 struct Icon

PT OS/2 Pointer

Thng thng l dng BM

0002h 4 bytes FileSize di ca ton file BMP tnh bng bytes

0006h 2 bytes Reserved Gi tr thc t ph thuc vo ng dng dng lu nh

0008h 2 bytes Reserved Gi tr thc t ph thuc vo ng dng dng lu nh

000Ah 4 bytes DataOffset Gi tr Offset bt u lu Data ca nh

Bitmap Information

0Eh 4 Size Kch thc ca InfoHeader thng l =40

12h 4 Width Chiu rng ca nh tnh bng pixel

16h 4 Height Chiu cao ca nh tnh bng pixel

1Ah 2 Planes S mt phng, thng =1

1Ch 2 BitCount S bit biu din mt pixel: 1: nh nh phn. Numcolors=2; 4: 4 bit xm. Numcolors=16

8: 8 bit xm. Numcolors=256

16: nh 16 bit RGB. Numcolors=65,536

24: nh 24 bit RGB. Numcolors xp x 16,7 triu mu.

1Eh 4 Compression Dng nn 0: nh khng nn RGB (thng l loi ny)

1: RLE 8bit/1pixel

2: RLE 4bit/1pixel

3: Bit field hoc Huffman 1D 4: JPEG RLE-24

5: PNG

6: Bit feild

22h 4 ImageSize Kch thc Bitmap Data

26h 4 XpixelsPerM phn gii theo phng ngang Pixels/Meter


22

2Ah 4 YpixelsPerM phn gii theo phng dc Pixels/Meter

2Eh 4 ColorsUsed S mu trong Color Palette

32h 4 ColorsImportant S mu quan trng, 0 nu tt c u quan trng

Color Palette c ln l 4*NumColors, ch c ngha vi nh 1,4,8bit.

Bitmap Data: ni lu d liu nh

Bng 2-1 nh dng file nh BMP

Pht hin cnh:

Pht hin cnh l mt bc quan trng trong nhiu bi ton x l nh. T nh u vo

l nh a mc xm, qua phng php pht hin cnh s cho nh u ra l nh a mc xm vi

cc cnh c cng cao hn hn cc im cn li trong nh.

Hnh 2-21 nh trc v sau khi pht hin cnh C s ton hc:


23

Ton t Gradient:

= [

] =

[

]

= () = [2 +

2]12 = [(

)2

+ (

)2

]

12

Tnh gn ng:

|| + ||

Mt n Sobel:

Z1 Z2 Z3

Z4 Z5 Z6

Z7 Z8 Z9

= (1 + 22 + 3) (7 + 28 + 9) (1)

= (1 + 24 + 7) (3 + 26 + 9) (2)

|| + ||

Trt ma trn 3x3 di y ht bc nh. Gi s ta cn tnh gi tr ca ma trn Gx ti

im 5, ta dng cc im ln cn ca n tnh theo cng thc (1) nh trn. Tng t nh vy

ta tnh ma trn Gy.

Da vo cng thc (1) v (2) ngi ta hnh thnh mt n Sobel theo phng x v

phng y nh sau:

Mt n Roberts cross:

Tng t mt n Sobel, ta lt phn t 2x2 ln lt cc im ca nh ban u

tnh ra gi tr nh cnh.


24

Mt n Prewitt:

Tng t phng php Sobel, hai mt n theo hai phng l:

Laplacian of Gaussian:

2 =2(, )

2+

2(, )

2

Trong :

2(, )

2= ( + 1, ) + ( 1, ) 2(, )

2(, )

2= (, + 1) + (, 1) 2(, )

2 = [( + 1, ) + ( 1, ) + (, + 1) + (, 1) 4(, )]

Mt n Laplacian:

V mt n Laplacian v c bn da trn o hm bc hai nn n rt nhy vi nhiu. V

vy kt qu n nh, trc khi dng mt n Laplacian ngi ta thng dng mt n

Gaussian lc bt nhiu. thun tin ngi ta c th nhn chp hai loi mt n trc khi

cho trt qua nh tnh. iu ny mang n ci li l gim s lng cc bc tnh ton, v

th s gim thi gian x l.

Laplacian of Gaussian

V d v mt mt n LoG vi = 1.4


25

So snh kt qu:

Hnh 2-22 b) Sobel. c)Prewitt. d) Robert. e)Laplacian.

f)LoG

Nhn xt: nhn chung cc phng php trn u cho kt qu tng i ging nhau.

u im ca chng l n gin v d thc hin. Tuy nhin tr (LoG) cc phng php cn li

u nhy vi nhiu. LoG c khuyt im l thng b mt gc, mt cnh ng cong.

Cc phng php pht hin cnh cao cp hn nh k thut Canny s t kt qu tt

hn, nhng li mt thi gian tnh ton phc tp hn. (s khng cp n mc ny).

Bin i Hough:


26

Hnh 2-23 Ma trn nh v ma trn Hough Php bin i Hough bin i mi pixel c ta (0, 0) trong mt phng x-y thnh

mt ng cong c phng trnh l

= () = 0 + 0

trong mt phng Hough. Hm trn l mt hm tun hon vi chu k l 2.

Trong mt phng x-y ta k hiu 0 v 0 ln lt l khong cch t gc ta n

ng thng t nh hnh v. Khi ta c vi mi (x, y) thuc ng thng t th:

0 = 0 + 0

Nh vy mi im (x, y) thuc ng thng t khi bin i qua mt phng Hough th

u i qua im c ta l (0, 0). iu ny suy ra rng: nu ng thng t trong mt

phng nh x-y c biu din bi n pixel, th trong mt phng Hough im (0, 0) s c n

ng cong i qua. V vy hnh thnh khi nim im tch ly trn mt phng Hough. Theo

, c mi ln c mt ng thng i qua mt im (, ) th gi tr tch ly ca im s

tang ln 1 n v.

Do ta xt mt phng nh x-y ch nm trn gc phn t th nht vi 0 0

nn ta ch xt khong 90 90 trn mt phng Hough.

Khong cch ln nht gia ng thng trong mt phng nh vi gc ta bng vi

ng cho ca nh, ta t l pmax. Khong ca p phi xt trong mt phng Hough l

Cc bc ca bi ton pht hin ng thng bng bin i Hough:

Bin i nh v nh nh phn cnh

Thc hin bin i Hough cho nhng pixel trng trn nh cnh


27

Kim tra ma trn tch ly trn mt phng Hough. Lc ra cc im (, ) c gi tr tch

ly ln hn mt ngng no .

Vi mi 0 0 ta tm ra mt phng trnh ng thng trn mt phng nh x-y

l

0 = 0 + 0

Lu : chia ca mt phng Hough theo phng khng nn qu nh, v thi

gian tnh ton s ln. i vi bin i Hough thi gian tnh l mt yu t quan trng v n s

dng 3 vng lp lng nhau. V vy vi nh c phn gii ln s dng bin i Hough rt

tn thi gian.

Xoay nh:

Bi ny xin trnh by cch xoay nh nh hnh minh ha di.

Hnh 2-24 Minh ha vic xoay nh mt gc a Thut ton s dng l quay tt c cc im quanh im trn cng bn tri ca nh mt

gc alpha theo chiu dng qui c. C hai cch thc hin vic xoay ny l nh x xui

(forward mapping) v nh x ngc (reverse mapping). Forward mapping s lm cho nh c

l. Vi reverse mapping, nh mt hn nhng cc mp vn khng c mm lm. [3]

Forward mapping

Trong forward mapping, t mi im ca nh gc, xc nh mt im ca nh kt qu.

Do phi lm trn s khi thc hin php xoay nn nh gc, c nhng pixel khng c "t

mu" lm cho trn nh xut hin nhng "l" li ti. i vi nh en trng khng cn cht lng

cao, sau khi to ra nh xoay vi nhng l trng cha c gn tr, ta c th t gn tr cho l

trng bng gi tr trung bnh ca cc im nh xung quanh.

Hnh hc gii tch cp 3 v i s tuyn tnh i hc c trnh by v cch xoay im M(x, y)

quanh gc ta gc a, thnh N(x', y') nh sau:

Forward mapping:


28

Hnh 2-25 Xoay im N quanh gc O mt gc a s c im M

|

| = |

| ||

Hay

=

= +

Reverse mapping

Vi reverse mapping, t mi im ca nh kt qu, suy ngc li t nh gc ly ra

gi tr mu cn thit. Vi cch ny, tt c cc im trn nh kt qu u c gn gi tr mu

ca mt im tng ng (hay t nht cng l im ln cn ca im ) nh gc nn khng

c hin tng "l" nh trn.

Ta tm ma trn xoay nh trong trng hp ny nh sau:

Do

|

| = |

| ||

Nn

|| = |

|1

. |

|

|| = |

| |

|

So snh:

Sau y l kt qu ca hai thut ton trn. D dng nhn thy l vi reverse mapping,

nh mn hn. Tuy nhin, trong qu trnh tnh ton, vn phi lm trn nn cc mp c hin

tng rng ca. Mt khuyt im ca phng php reverse mapping l ngi lp trnh gp

kh khan hn trong vic tm ra c im gc ca nh sau khi xoay.


29

Hnh 2-26 Kt qu xoay nh ca phng php Forward Mapping

Xoay nh tm:

trn va trnh by cch xoay nh gc ta ban u ca nh, tc l gc trn cng

bn tri. Tuy nhin trong phn ln cc ng dng, ngi ta thng cn xoay nh tm ca bc

nh. lm c vic trc v sau khi xoay nh ngi lp trnh tin hnh i h ta

quy chiu bc nh nh sau:


30

Hnh 2-27 Cc bc i ta nh [4]

Resize nh:

C nhiu phng php resize nh khc nhau. Sau y l cc phng php thng

dng.

Ni suy l phng php c tnh gi tr ca cc im d liu cha bit trong phm vi

ca mt tp hp ri rc cha mt s im d liu bit

Trong khoa hc k thut, ngi ta thng c mt s im d liu bit gi tr bng

cch ly mu thc nghim. Nhng im ny l gi tr i din ca mt hm s ca mt bin

s c lp c mt lng gii hn cc gi tr. Thng chng ta phi ni suy (hoc c tnh) gi

tr ca hm s ny cho mt gi tr trung gian ca mt bin c lp. iu ny c th thc hin

bng phng php ng cong ph hp hoc phn tch hi quy.

Phng php ni suy im ln cn gn nht (Nearest-neighbor):

tng ca phng php ny l ta xp x gi tr ca im trn nh kt qu bng vi

gi tr ca im gn nht trn nh gc sau khi nhn vi t l chiu dc v chiu ngang.

Gi s ta c nh ban u l I c kch thc

Ta cn resize nh ny thnh nh I kch thc

Ta tin hnh tnh nh sau:

=

=

Vi mi im ca nh kt qu I ta tm ngc li ta ca im ny trn nh gc I

sau gn gi tr.

[][] = [][]


31

Vi ta im trn nh gc c tnh nh sau:

= ( )

= ( )

Phng php ni suy tuyn tnh (Bilinear interpolation):

C s ton hc: ni suy hm mt bin.

Ta bit qua hai im cho trc lun lun v c mt ng thng.

() =1

1 0(0) +

01 0

(1)

Gi 0, 1 l gi tr hm ti im 0, 1 v 1 0 = 1. Ta c

(0, 1, ) = (1 )0 + 1 = (1 0) + 0

i vi hm hai bin (, ), phng php ni suy ny c tn gi l bilinear:

(, ) = ((00, 10, ), (10, 11, ), )

V d:

Khi tnh 20,14.5 ta thay = 14.5 14 = 0.5


32

20,14.5 = (210 91) 0.5 + 91 = 150.5

21,14.5 = (95 162) 0.5 + 162 = 128.5

20.2,14.5 = (128.5 150.5) 0.2 + 150.5 = 146.1

Phng php ni suy cubic (bicubic interpolation):

C s ton hc: php ni suy cubic

Ni suy cubic hm mt bin:

C rt nhiu phng php ni suy ng cong hm mt bin khc nhau. y em

trnh by mt phng php m em tm hiu, l phng php CATMULL-ROM

SPLINES

Gi s hm cn tm c dng hm s bc ba:

() = 3 + 2 + +

(0) =

(0) =

(1) = 3 + 2 +

Suy ra

= 2(0) 2(1) + (0) + (1) (1)

= 3(0) + 3(1) 2(0) (1)

= (0)

= (0)

Gi 0, 1, 2, 3 l gi tr ca hm ti cc im 0 = 1, 1 = 0, 2 = 1, 3 = 2

Ta c:

(0) = 1

(1) = 2

(0) =(1) (1)

2 0=

2 02

(1) =(2) (0)

3 1=

3 12

Th cc gi tr trn vo (1) ta c:

= 1

20 +

3

21

3

22 +

1

23

= 0 5

21 + 22

1

23

= 1

20 +

1

22


33

= 1

(0, 1, 2, 3, )

= (1

20 +

3

21

3

22 +

1

23)

3 + (0 5

21 + 22

1

23)

2

+ (= 1

20 +

1

22) + 1

i vi hm hai bin (, ) ngi ta gi l ni suy bicubic. Gi tr hm s xp x nh

sau:

(, )

= ((00, 01, 02, 03, ), (10, 11, 12, 13, ), (20, 21, 22, 23, ), (30, 31, 32, 33, ), )

Trong x l nh, ta da vo 16 im bit t nh gc ni suy ra gi tr ca 1

pixel nh resize. Cng nh phn ni suy im gn nht, ta c:

=

=

Vi i,j l ta ca mt pixel trong nh resize.

= ()( )

= ()( )

=

=

, l ta im 11.

1 , 1 l ta im 00.

1, l ta im 01.

.

So snh cc phng php:

Hnh 2-28 nh ban u

Hnh 2-29 nh resize theo phng php im ln cn gn nht


34

Hnh 2-30 nh resize theo phng php bilinear

Hnh 2-31 nh resize theo phng php bicubic R rng ta nhn thy mi phng php trong ba phng php trn u c mt u im

nht nh:

Phng php ni suy im gn nht l n gin nht, tc x l chng trnh l

nhanh nht, kt qu resize mc tm n, i vi cc nh c nhiu ng cong, ng xo th

nh s b rng, chuyn mu khng mt

Phng php ni suy tuyn tnh tc khng nhanh bng phng php trn nhng

cht lng nh resize c ci thin hn

Phng php ni suy cubic. Tc x l chm hn hai phng php trn nhiu ln.

Cht lng nh resize kh tt. V vy phng php ny thng c s dng trn my tnh c

nhn, c tc x l cao, thi gian x l lc ny khng cn quan trng.

Phng php SVM:

Khi nim

SVM - vit tt tn ting Anh support vector machine [5]l phng php s dng ph

bin trong cc bi ton phn lp trong nhiu lnh vc: x l nh, x l m thanh, k thut

gen,L mt phng php ph bin, c h tr trong th vin ca cc chng trnh x l

nh nh Opencv, Matlab,

SVM dng chun nhn d liu vo v phn loi chng vo hai lp khc nhau. Do

SVM l mt thut ton phn loi nh phn. Phng php ny da trn tng dng mt mt

phng chia cc im trong khng gian thnh hai lp ring bit.

Gi s siu phng tm c c phng trnh l:

. + = 0

Vi x l vector kch thc p chiu ca mu cn nhn dng, w l vector p chiu, c

gi l vector trng s. < . > l tch v hng ca hai vector.

Vi l mu cn c phn lp th


35

Nu . + > 0 th thuc lp 1.

Nu . + < 0 th thuc lp 2.

Mc tiu ca SVM l:

1. Cc tiu li phn lp v

2. Cc i khong cch l gia cc lp.

Tm siu phng ti u:

Gi l vector cc mu hun luyn, l gi tr nhn bit ca ca cc mu . Vi

i=1,2,n Gi tr = 1 hoc = 1 tng ng vi lp th nht v lp th hai.

L ca hai lp l hai siu phng song song c phng trnh l:

. + = 1

. + = 1

Khong cch gia hai siu phng l l 2

. Nh vy mc tiu cc i ha khong cch

gia hai l tr thnh cc tiu ha gi tr .

iu kin thuc nhm th nht l

. + 1

iu kin thuc nhm th hai l

. + 1

Nh vy iu kin chung ca tt c cc mu hun luyn vi i t 1 ti n l:

(. + ) 1

Lc ny bi ton tr thnh tm gi tr w v b tha hai iu kin sau:

{

(. + ) 1 = 1,


36

Hnh 2-32 Gi s c hai nhm d liu hun luyn cn phn lp bit trc ,

Hnh 2-33 Cu hi t ra l siu phng no l tt nht? p1,p2 hay p3?


37

Hnh 2-34 Xy dng cc siu phng l l ca cc lp, cc mu nm trn l l vector ta (Support Vector)

Hnh 2-35 Siu phng phn lp cch u hai siu phng l.

Dng l mm:


38

Do khng phi lc no cng tm ra c siu phng phn tch rch ri gia hai lp,

dng l mm cho php mt vi mu hun luyn b gn nhn sai, tc l iu kin (. +

) 1 khng c tuyt i tha mn.

Phng php ny dng thm bin sai s , dng o sai lch. Biu thc iu

kin c vit li thnh:

(. + ) 1 = 1,

Bi ton phi thc hin thm mc tiu s l cc tiu ha cc tiu li. Nh vy

lc ny bi ton ti u c s nh i gia hai mc tiu l l ln v mc li nh.

Bi ton nhn din ch quang hc:

Nhn din ch quang hc l mt bi ton ph bin trong x l nh. N c s dng

trong nhiu ng dng. Mc ch ca bi ton ny l nhn din chuyn ch trn cc bc nh

thnh dng m ASCII.

Hin nay c nhiu gii php c s dng cho bi ton ny:

Khong cch nh nht

Phn lp da vo quyt nh Bayes

Khp mu.

Phng php SVM

H m Markov

Mng Neuron

Mi phng php c nhng u im v hn ch nht nh. Nhng ph bin nht l

phng php SVM v mng Neuron.

Phn ny trnh by vic s dng SVM vo qu trnh nhn dng ch quang hc.

Qu trnh nhn dng ch quang hc tri qua 2 giai on:

.

Hun luyn

Nhn dng


39

Hai qu trnh ny c th din ra trn hai thit b c lp vi nhau.

Giai on tin x l, trch chn c trng v chin lc phn lp ca hai qu trnh

trn phi ging nhau.

Qu trnh hun luyn:

y l bc quan trng, c th c thc hin trc, ring bit vi chng trnh x l

nh tin hnh nhn dng. u vo ca qu trnh ny l cc mu thu thp, u ra l cc vector

trng s ca cc my phn lp SVM

Mu hun luyn:

Ngi lp trnh phi thu thp mt s lng mu nht nh hun luyn. Qu trnh

thu thp phi m bo cc tiu ch:

Cc mu hun luyn phi c to ra vi quy trnh tng ng vi mu

cn nhn dng sau khi qua giai on tin x l trong qu trnh x l. V d:

Inpu

tO

utp

ut

Mu hun luyn

Text

H thng nhn dng

Tin x lTrch chn c trng

Hun luyn theo nguyn

l SVM vi chin lc xc nh

Vector

trng sW,Bias


40

mu cn nhn dng sau khi qua giai on tin x l l mt nh nh phn,

kch thc 10x20, ch ci trong mu nm st vi ng bao nh, th mu

dng hun luyn cn phi tha mn tt c cc tiu ch .

Cc mu hun luyn phi mang c trng ca cc lp cn hun luyn. V d

cn nhn din ch A th nhn vo mu ta phi c c l ch A, khng

th a vo mu khng th c c bng mt thng m gn nhn l ch

A, nh vy s lm h thng nhn dng km chnh xc.

Cc mu hun luyn cng a dng cng tt, tc l hnh hun luyn khng

c rp khun ging nhau, qu sc nt, qu p. Nh vy trong qu trnh

nhn dng nu gp mu xu nhng vn c th c c th s nhn dng

tht bi. C th thu thp cc mu hi mo, hi nghing, hi m nhng vn

phi m bo l vn c c trng ca mu cn nhn dng. V phng php

SVM ch s dng cc vector bin mi lp, tc l cc vector d b nhm

ln gia hai lp nht nn vic s dng nhiu mu na n nhau l v ch,

khng lm tng cht lng phn lp.

i vi cc lp gn ging nhau: v d s 5 vi s 6, hoc s 3 vi s 9,

Cn s dng cc mu c c im d b nhm ln gia hai lp nht, nhng

vn c th c c ng bng mt thng.

V s lng mu, khng phi lc no nhiu cng l tt. Nh ni trn, nu

cc mu c c im na n nhau hoc copy ra th s lng lc ny l v ch.

Nu mu c thu thp tt, a dng c th m t mi lp mt cch tng

i chnh xc th qu trnh nhn dng s t kt qu ng tin cy.

Qu trnh hun luyn tun theo cc c s ton hc ca phng php SVM to ra

cc vector trng s W nhm s dng trong qu trnh nhn dng. S lng, thnh phn ca cc

my vector c hun luyn ty thuc vo chin lc phn lp c gii thiu phn di.

Qu trnh nhn dng:


41

H thng s dng vector trng s W v Bias to ra siu phng phn lp:

. + =




: l vector trng s

: l s Bias

Tin x l:

y l cng on x l cc nh u vo ng b ha d liu nhm chun b phn

lp.

Chuyn nh thnh nh en-trng

Xoay nh cho dng ch trng vi phng ngang

Phn on k t

Resize nh

Vector

trng sW,Bias

Inpu

t

Ou

tpu

t

Mu nhn dng

Text

H thng nhn dng

Tin x lTrch chn c trng

Phn lp theo chin lc nht

nh

Inpu

t

Kt qu phn lp


42

Trong cc bc nh cha ch, ta thng gp vn l nh b mo, khng ngay hng

theo phng ngang. Gii php thng c s dng xoay nh cho thng l Projection

Profile. Ngoi ra ngi ta c th s dng bin i Hough tm c gc lch ca cc dng

ch so vi phng ngang xoay li cho thng. (Bin i Hough c trnh by trn)

Projection Profile.

Cc bc thc hin

Trn tng phng t -45 n 45 (khong ny l do ngi vit nh), ta tnh

hnh chiu ca nh. Hnh chiu theo mt phng l mt mng cc gi tr m mi gi tr l

tng s im trng trn mt ng thng theo phng . Mi mng s c mt phng sai

gia cc phn t trong mng.

Phng no c phng sai ca mng ln nht l phng ca dng ch trn vn bn

m ta xt. Nh vy ta bit c gc lch gia dng ch v phng ngang ca vn bn.

Xoay nh dng ch trng vi phng ngang

Phn on k t:

Bc ny s n gin i vi ch in nhng d b li vi ch vit tay.

Ngi ta s dng hnh chiu theo phng ngang v phng dc ca vn bn phn

on.


43

Hnh 2-36 Hnh chiu ngang v chiu dc ca mt on k t. Da vo hnh chiu ngi ta c th ct ri on vn bn thnh tng ch ci hoc ch

s.

Resize nh:

C s l thuyt ca bc ny c trnh by phn trn.

Cc ch ci hoc ch s sau khi c ct ri s c resize v mt kch thc chun

no cng vi kch thc ca mu c hun luyn chun b cho qu trnh nhn dng.

i vi bi ton nhn din ch ngi ta s dng nh nh phn (trng en).

Trch chn c trng

C v s cch trch chn c trng mu khc nhau. Ty theo nghin cu ca ngi

vit, tuy nhin ngi ta hng ti vic chn c trng mang tnh tiu biu, cng khc nhau

cho mi lp hun luyn cng tt. nh gi c cch no l cch ti u cn c s th

nghim v nh gi hon chnh.

Sau y l mt s cch chn c trng xut:

S dng tt c cc pixel ca nh:

y l phng php n gin nht. S dng tt c cc pixel ca nh lm c trng.

V d mt nh c kch thc 10x20 th s c tt c 200 c trng. Tuy nhin phng php ny

c khuyt im l s c trng s dng ln, khin cho thi gian x l tang.

Trng s vng:

nh u vo s c chia thnh nhng vng nh hn. S im en, hoc im trng

trong vng c m s dng lm c trng.


44

V d: mt nh kch thc 10x20 nu ta chia thnh nhng vng nh hn l cc c

kch thc 2x2 th mt vector c tt c 50 c trng.

Dng biu hnh chiu:

C th s dng biu hnh chiu theo cc phng khc nhau lm c trng. n

gin nht l s dng phng chiu dc v chiu ngang, nu mun s dng nhiu c trng

hn ngi ta c th s dng hnh chiu theo ng cho .Phng php ny khng b nh

hng bi nhiu, nhng b nh hng bi nghing ca ch.

V d: mt nh kch thc 10x20 s c 10 c trng theo ct v 20 c trng theo

hng ngang. Tng cng mt vector s c 30 phn t nu ta s dng biu hnh chiu dc v

ngang.

Chin lc phn lp

Thut ton SVM ch gii quyt phn lp nh phn tc l s lp l 2. Nu mun phn

lp vi s lp ln hn, v d nh 26 lp trong nhn din ch ci th cn p dng cc chin

lc trong qu trnh hun luyn v phn lp.

C ba chin lc phn lp ph bin:

Mt chng mt (OVO: One verus One)

Mt chng phn cn li. (OVR: One verus Rest)

Chin lc phn cp. (DAG: Directed Acyclic Graph)


45

Hnh 2-37 a. OVR b.OVO c.DAG

Chin lc mt chng mt (OVO):

Vi N lp cn phn, h thng s c tt c (1)

2 my phn lp nh phn. Mi my

c hun luyn phn lp gia tng cp hai lp vi nhau. Mi mu d liu khi cn nhn

dng s i qua ht tt c cc my nh phn ny. Mi my s cho mt quyt nh d liu thuc

v lp no trong hai lp ca my. Sau khi kt thc s c (1)

2 quyt nh, n s da vo s

phiu bu gia ca tt c cc my phn lp quyt nh kt qu s chn lp no.Nu lp

no trong N lp c s phiu bu cao nht th mu s c phn vo lp .

Do tc phn lp s rt chm nu s lng lp hoc s lng c trng ln. Tuy

nhin y li l chin lc chnh xc nht so vi cc chin lc cn li, nn nu tc khng

quan trng hoc s lng phn lp nh th ngi lp trnh s dng phng php ny.

Chin lc mt chng phn cn li (OVR):

Mi lp s c xy dng mt m hnh my phn lp nh phn ring. Mi my SVM

c hun luyn phn loi mt lp vi s mu cn li khng thuc lp . Nh vy vi N

lp cn phn loi th c tt c N my phn lp. Nu c nhiu lp c chn trong N lp th

kt qu cui cng l lp c tr tuyt i kt qu th vo siu phng SVM cao nht trong cc


46

lp c chn . Mt la chn khc ca phng php ny l: qu trnh phn lp s c

dng li bng lnh break nu c mt my cho kt qu lp no c chn - cch ny bt

n nh v d dn n kt qu sai.

Chin lc ny c mt u im l s my phn lp t, do thi gian nhn dng s rt

nhanh. Tuy nhin thi gian hun luyn s lu v mi my phn lp c ng vo l s lng d

liu hun luyn ln. chnh xc ca chin lc ny khng cao do my vector c hun

luyn t cu trc d liu khng tt, (khi hun luyn mt-phn cn li th phn cn li l tp

hp ca nhiu lp khc nhau nn c trng rt phc tp)

Chin lc phn cp (DAG):

Xy dng cy quyt nh cho c bi ton, mi my phn lp nh phn trn cy u

theo kiu mt i mt, c tt c (1)

2 my phn lp nh phn c hun luyn, nhng qu

trnh phn lp ch i qua N-1 my phn lp. Xem v d vi bi ton phn lp vi s lp l 5

trong hnh di y:

Chin lc ny cng c khuyt im l nu phn lp sai mt nt c th dn n kt

qu sai cho ton b. Nh v d trn, nu d liu cn nhn dng l s 1, nhng nt u tin

n c phn vo lp 5, th n mt c hi phn vo lp ng l lp 1. Tuy nhin chin

lc ny khc phc c khuyt im ca chin lc OVR l d liu hun luyn khng

b phc tp ha. y l chin lc c tc phn lp nhanh nht nhng cng mt n nh

nht trong ba chin lc.


47

3. THIT K V THC HIN PHN CNG

3.1. Yu cu thit k

Thit k h thng SOPC xung kit DE2 thc hin chng trnh nhn din bin

s t nh.

H thng bao gm:

Thit b hin th nh: mn hnh VGA

B nh lu nh

B nh m cho vic hin th nh

B nh chng trnh

Cc khi x l hin th nh

Thit b hin th m ASCII ca bin s c nhn dng: LCD hoc mn

hnh VGA

Nt bm iu khin qu trnh x l

Trong th vin SOPC Builder ca Altera c b th vin University Program bao gm

nhng thit k phn cng thng dng s dng trn kit DE2. Altera cng cung cp mt s v

d thit k h thng my tnh v giao tip ha n gin: DE2_Media_Computer, Tt

c c cung cp bi chng trnh University Program nm trong ng dn:

C:\altera\11.1\University_Program\NiosII_Computer_Systems\DE2\DE2_Media_Co

mputer

C:\altera\11.1\University_Program\Examples\IP_Core_Demos\Video_Demos_using_

SOPC_Builder\DE2


48

3.2. S khi tng qut ca h thng:

Hnh 3-1 S khi h thng c thit k bng SOPC Chi tit chc nng tng khi tham kho [6]

Gii thch s :

CPU

H thng s dng core Nios II/s. V y l h thng x l nh tc x l l rt quan

trng, v vy m core Nios II/e khng thch hp. Core Nios II/f x l rt nhanh tuy nhin h

thng gp kh khan trong vic s dng phn t Character Buffer cho vic hin th ch ra

mn hnh VGA (C th do vn bn quyn). Core Nios II/s c tc x l chp nhn c,

tuy s dng bn time limited nhng khng pht hin thy vn pht sinh.

CPU Nios II

SRAM Controller

Character Buffer for

VGA

Pixel Buffer DMA

controller

RGB Resampler

Scaler

Alpha Blender

Dual Clock FIFO

VGA Controller

JTAG UART

Tristate Bridge

Flash Memory Interface

Buttons

16x2 Character Display

Parallel Port

SRAM512 KB

Data Master

Tristate

master

SDRAM Controller

Instruction master

USB BlasterSDRAM

8 MB

VGA DAC

FLASH4 MB

Clock Signal

Slave

LCD

Clk

SDRAM

clk

VGA

VGA

Controller

On chip FPGA

Off chip DE2

stream

30 bit

color

640x480

v clk

VGA

Backgroundforeground

Slider SW

Parallel Port


49

Hin th hnh nh ln VGA [7]

S dng k thut DMA (Direct Memory Access) hin th hnh nh. [8]

Mn hnh VGA hin th nh vi phn gii l 640x480, di dng RGB 30 bit.

Hnh 3-2: ch mu ca VGA Cch nh a ch pixel trn VGA [6]:

Hnh 3-3: Frame hnh hin th ln VGA

Hnh 3-4 Cch nh a ch cho pixel hin th Tn dung lng b nh lu 1 frame nh:

640 480 30 = 9 216 000 = 1.1

qu trnh truy xut nh c nhanh th cn dng b nh SRAM lm buffer lu

nh. Nhng vn l dung lng ca SRAM ch c 512 KB. B nh onchip to ra nh thit

k FPGA th dung lng rt nh (do rng buc v s phn t logic khi thit k FPGA). B

nh SDRAM cn c dng lm b nh d liu v b nh chng trnh, v d liu x l cng

c dung lng rt ln.

Do cn phi thu nh phn gii ca frame nh v ch hin th pixel li. Hai

khi RGB Resampler v Scaler nhm t yu cu v dung lng.

Khi RGB Resampler: chuyn pixel nh dng RGB 16 bit thnh pixel

RGB 30 bit.

Khi Scaler chuyn nh phn gii t 320x240 sang nh 640x480

B nh lu nh Flash:

29 20 19 10 9 0

row 0, col 0 row 0, col 1 row 0, col 639 row 1, col 0... ... row 479, col 639


50

Flash l b nh lu nh c down t laptop xung. Altera s dng gi file nh dng

ZIP khng nn cha 1 hay nhiu nh khc nhau. ln ca b nh Flash l 4 MB. s

dng b nh Flash cn dng khi flash memory interface giao tip vi b nh Flash off

chip.

B nh chng trnh v d liu:

S dng SDRAM cha d liu ang x l v d liu ca cc mng nh rt ln. Cc

b nh khc khng dung lng cha.

Jtag Uart:

Dng in hm printf ra ca s chng trnh dng kim sot trong qu trnh

thit k phn mm.

H thng clock:

Clock h thng s dng ngun xung clock trn board l clock 50 MHz.

B Clock Signal c chc nng to thm clock s dng cho khi VGA

Controller v khi SDRAM Controller t clock vo h thng 50MHz [9]

VGA clock: c tn s 25 MHz.

SDRAM Controller clock: tn s 50MHz nhng tr pha 3ns so vi clock h thng.

3.3. Chi tit thit k:

CPU:

Chn CPU Nios II/s

Hnh 3-5 Thng s chn CPU Thm vector ngt v phn cng tnh ton Floating-point cho h thng:


51

Clock Signal

To xung clock cho SDRAM v VGA Controller t clock h thng 50 MHz

Hnh 3-6 Thng s cu hnh cho Clock Signals

Character buffer for VGA display

y l khi nhn u vo l m ASCII ri chuyn sang dng hin th hnh nh, s

dng phng thc DMA hin th ln mn hnh VGA.

Mn hnh VGA hin th c tt c 60 hng, mi hng 80 k t.


52

Hnh 3-7 Thng s cu hnh cho character buffer for VGA display

Pixel Buffer

S dng b nh Sram lm Pixel Buffer nhm thc hin k thut DMA.

Hnh 3-8 Thng s cu hnh cho SRAM Controller

Pixel Buffer DMA Controller

Khi iu khin truy cp b nh cha frame nh trc tip.


53

Default Buffer Start Address: a ch bt u ca buffer nh. y l a ch ca ca

SRAM.

Hnh 3-9 Thng s cu hnh Pixel Buffer DMA Controller

RGB Resampler

Khi chuyn i nh dng 16 bit RGB sang nh dng 30 bit RGB

Hnh 3-10 Thng s cu hnh RGB Resampler

Scaler

Khi Scale chuyn i t phn gii 320x240 thnh 640x480.


54

Hnh 3-11 Thng s cu hnh Scaler

Alpha Blender

Khi kt hp hai dng nh: character v pixel thnh mt dng duy nht. Dng pixel

c gi l background cn dng character l foreground.

Hnh 3-12 Thng s cu hnh Alpha Blender

Dual Clock FIFO:


55

Gip chuyn i dng video gia hai vng c tn s clock khc nhau. ng vo

chui d liu vo vi tn s clock vo, sau i qua b m FIFO v ra vi tn s clock

khc.

Hnh 3-13 Thng s cu hnh Dual Clock FIFO

VGA Controller

L khi giao tip vi b VGA DAC (off-chip).

Hnh 3-14 Thng s cu hnh VGA Controller


56

Jtag Uart

Truyn d liu gia board v my tnh. Dng cho qu trnh debug trong qu trnh lp

trnh phn mm

Hnh 3-15 Thng s cu hnh JTAG UART

SDRAM Controller

Cu hnh cho SDRAM Controller nh bn di giao tip vi b nh SDRAM trn

board.


57

Hnh 3-16 Thng s cu hnh SDRAM Controller

Giao tip b nh Flash:

maped b nh Flash trn board DE2 vi vng a ch b nh d liu ta cn s

dng hai khi trong th vin: Tristate Bridge v Flash Memory Interface (CFI)

Cu hnh CFI nh hnh v giao tip vi b nh Flash 4MB.

Cc thng s Timing chn nh hnh v.


58

Hnh 3-17 Cu hnh khi Tristate Bridge

Hnh 3-18 Cu hnh khi Flash Memory Interface


59

Hnh 3-19 Thng s timing ca CFI

Parallel Port

Trong ti ny em s dng 2 port song song kt ni vi: Buttons v Slider

Switches. Vi port Buttons cn tick vo cc la chn to ngt nh hnh. [10] [11]

Hnh 3-20 Thng s cho Parallel Port kt ni vi Slider Switches.


60

Hnh 3-21 Thng s cu hnh cho Parallel Port kt ni vi Buttons.

16x2 Character Display

y l port giao tip vi mn hnh LCD trn board DE2. [10] [12]


61

Hnh 3-22 Thng s cu hnh cho khi giao tip LCD


62

3.4. Kt qu thit k h thng:

Hnh 3-23 Kt qu thit k SOPC ca h thng S b nh ca cc thnh phn h thng:

Hnh 3-24 a ch cc vng nh ca h thng


63

4. THIT K V THC HIN PHN MM

4.1. Yu cu t ra cho phn mm

c file nh bitmap t b nh Flash

Ct c vng cha bin s

Nhn dng k t trn bin s

Xy dng giao din giao tip gia ngi dng v chng trnh.

n gin ha bi ton ta t ra cc tiu chun cho nh u vo:

Kch c bin s phi tng i ln trong nh

Bin s c th nghing nhng khng nghing qu 45

Gi nh l bin s cn trng r s.

4.2. Phn tch

nhn din c bin s xe c rt nhiu gii thut khc nhau. Nhng hu ht cc

cch u i qua cc cng on chnh sau y:

Ngoi ra cn cn m bo vic giao tip gia ngi dng v chng trnh thng qua

cc thit b ngoi vi: mn hnh VGA, LCD, PushButtons, Slider Switches.

V vy chng trnh cn thc hin thm cc chc nng:

Hin th nh ln mn hnh VGA

Hin th ch ln mn hnh VGA

Xy dng h thng nt bm iu khin c: PushButtons, Slider

Switches

Hin th kt qu ra mn hnh LCD

Load nh

Ti nh vo b nh Flash:

u tin gi cc nh bitmap cn s dng vo mt gi file .zip khng nn.

Load nh

c file nh t b nh Flash trn Board

Tin x l

Chuyn i nh dng nh RGB sang nh a mc xm

Tch bin s

Xc nh vng cha bin s

Ct vng cha bin s

Xoay bin s li cho thng

thng thng

Nhn dng k t

Phn on k tp dng bi ton

nhn dng ch quang hc vo vic nhn dng k t.


64

Sau nhp chut phi vo project trong ca s st tay tri. Chn mc Flash

Programer nh hnh.

Hnh 4-1 Cc bc load nh vo b nh Flash.


65

Chn file .sopcinfo trong th mc lu project quartus nh hnh

Vo mc connections chn nh hnh


66

Sau bm Start. Ca s giao din hin ra nh bn di l ng.


67

Sau vo BSP Editor thc hin theo cc bc sau to ng dn vo b nh

Flash.


68

Sau bm vo nt Generate

Nh vy cc nh c gi trong file xe.zip u c down vo b nh Flash.

truy xut n mt nh trong Flash ta cn s dng ng dn:

my_fs/xe/xe2_24bit.bmp\0

xe2_24bit.bmp l tn ca file nh cn load.

c nh bitmap t b nh Flash:

Da vo cu trc ca file bitmap trnh by phn trc m ta d dng c c file

nh.

S dng cc hm trong th vin chun ca C : stdio.h c nh bitmap 24 bit:

Phi chuyn sang nh dng RGB 16 bit v h thng SOPC c thit k hin th

nh 16 bit t buffer nh ln mn hnh. nh dng RGB 16 bit l nh dng tin li nht cho

vic hin th.

nh dng 24 bit th mi mu R, G, B mi mu c biu din bi 8 bit

nh dng 16 bit th R v B mi mu chim 5 bit, ring G c biu din bi 6 bit

Cch chuyn i t nh dng pixel 24 bit sang 16 bit nh sau:

(Unsigned short)Red=Red_24>>3;

M file

S dng hm fopen m file nh

c cc thng s nh

(S dng hm fseek) : c chiu rng, chiu

di nhs bit biu din 1

pixel

a ch offset n data

c data nh

Da vo a ch offset tm c bc trc nhy n a ch lu data (dng hm fseek)

c gi tr data nh 24 bit theo tng byte (hm fgetc).

Chuyn i data nh

Chuyn nh dng pixel RGB 24 bit thnh nh

dng RGB 16 bit


69

(Unsigned short)Green=Green_24>>3;

(Unsigned short)Blue=Blue_24>>3;

RGB_16= (Red


70

ca gii thut, cc phng php lc nhiu ca ngi vit m mi phng php s

ci thin c phn no cc khuyt im.

Phng php Hough da trn vic pht hin cnh on thng trong nh do

s sai nu qu trnh pht hin cnh khng tt. Nu trong nh c nhiu

on thng song song hay vung gc nhau th phng php ny khng th

p dng c. N ph thuc nhiu vo kch thc bin s trong nh

Phn on nh da vo mc xm: phng php ny nhy vi chi, kch

thc bin s xe, mu sc trong nh, nu nh xe mu trng th phng

php ny rt d sai. thnh cng ph thuc rt nhiu vo qu trnh ly

ngng ca nh.

Phng php n thun da vo mt cnh. y l phng php khng

n nh rt d b nhiu kt qu chnh xc khng cao.

Phng php da vo mu sc ca nh RGB li rt nhy vi mu sc, kch

thc bin s, n rt gn vi phng php phn on nh da vo mc

xm.

Rt tic v bit qu tr nn em cha nghin cu phng php pht hin

vng bin s da vo training.

Trong ti ny em chn phng php bin i Hough pht hin bin s.

Kt thc qu trnh ny ta s ct c nh bin s c x l xoay nh cho

thng.

Mt im lu phn ny l i vi cc php ton trong vng lp cn c thc hin

dng s nguyn. Cc gi tr sin, cos cn c tnh trc bng Matlab v lu li di dng

mng tr khi to.

Ly cnh

S dng mt n Sobel pht hin cnh

Bin i Hough

Bin i Hough nh nh phn sau khi ly cnh.

chia nh nht ca ma trn Hough l:

2 theo phng gc v

2 v theo phng khong cch

Mi im trong ma trn Hough c biu din bi 1 struct vi 3 trng gi tr:

khong cch (r), gc (theta), gi tr tch ly (acc).

Lc li ma trn Hough


71

S dng nhiu iu kin khc nhau lc cc im trn ma trn Hough tm ra im

cn tm:

Gi tr tch ly phi ln

Gi tr tch ly l cc tr trong vng ln cn gii hn bi bn kch 2.( vung

5x5)

Gi tr gc >70 hoc abs(gc)>15 hoc (gc)


72

Kt thc bc trn ta c nh vng bin s (c th b mo) v gc nghing ca cnh

ngang bin s. Gi s gc nghing l b.

Ta tm gc nghing nh cn xoay thng li bng biu thc:

= ( 90)

Vic xoay nh c thc hin bng phng php Forward mapping, tm xoay l

im trung tm nh.

Trc khi xoay ta cn xc nh trc v tr mi ca 4 nh bin s. T suy ra c

kch thc nh sau khi xoay sau khi hnh bin s nm va kht mng nh.

Sau khi xoay ta gn gi tr cc l trng bng trung bnh ca 4 im ln cn n. Do bin

s ch c mu trng v en nn cht lng ca nh khng b nh hng ng k.

Nhn dng k t

Phn ny ta p dng bi ton nhn din ch quang hc trnh by phn l thuyt

vo nhn dng ch s.

Chuyn nh xm thnh nh trng en

T bin s l nh xm ta chn mt ngng no , v d 130 chuyn i nh thnh

nh en trng. tng qut hn ta c th s dng cc phng php ly ngng chuyn

i.

Phn on k t

Da vo hnh chiu theo phng ngang v dc ct cc s:


73

Hnh 4-2 Qu trnh phn on k t Resize tng k t:

S dng phng php resize im gn nht a nh cc k t v kch thc

[10x20]. Mc d phng php ny cho cht lng resize nh khng cao, nt nh khng mn,

nhng do nh resize l nh en trng nn cht lng y khng nh hng g n vic nhn

dng lm. V tc li quan trng hn.

Trch chn c trng

Lun vn ny s dng phng php biu hnh chiu vi hai phng l: phng

ngang v phng dc.

Nh vy vi mi mu c kch thc l [10x20] s c 30 c trng.

Training SVM

y gi s mi v tr k t trn bin s xc nh c l ch hay s: gi thit

l v tr k t th 3 hng th nht l ch, cn tt c cc v tr cn li l s. Nh vy ta xy

dng hai bi ton phn lp: mt dng phn lp s v ci cn li dng phn lp ch.

Vi bi ton phn lp s c 10 lp cn phn lp t 0 n 9. Bi ton phn lp ch c

21 lp cn phn gm: A, B, C, D, E, F, G, H, K, L, M, N, P, R, S, T, U, V, X, Y, Z. Do cc

ch ci khc khng thy xut hin trn bin s xe thng thng nn khng thu thp c mu

hun luyn. Do s lp cn phn nh, khng ln nn c th dng chin lc mt chng mt

Qu trnh trch chn c trng cc mu v hun luyn hun luyn din ra hon ton

trn PC c nhn, dng phn mm Matlab, theo chin lc mt chng mt (OVO). [13]

Do Matlab ch xut ra gi tr vector Alpha ch khng phi vector W nn ta tm W

bng cch:

= . _


74

Mu training c thu thp t cc bin s xe trong bi xe. c x l v lu trong th

mc km theo.

Cc gi tr W v Bias ca mi bi ton c lu li v c s dng trong qu trnh

nhn dng. W v Bias c a vo chng trnh C di dng mng gi tr c khi to t

u chng trnh. V v chng trnh C thc hin cc php tnh vi s thp phn (dng float,

double) rt lu nn ta phi chuyn tt c cc vector W v Bias thnh kiu s nguyn. Bng

cch nhn tt c cho 2^15. Dng hm round trong Matlab.

Vic tnh ton siu phng phn lp vn lm nh bnh thng.

Nhn dng

Qu trnh nhn dng c thc hin bng CPU Nios, s dng cc vector W v Bias

lu

H thng s dng vector trng s W v Bias to ra siu phng phn lp:

. + =




: l vector trng s

: l s Bias

Giao din ngi dng:

Xy dng cc hm nhm h tr s giao tip ca ngi dng v h thng x l:

Hin th nh ln mn hnh:

Ta cn xy dng cc hm dng hin th mng gi tr nh 8 bit hoc 16 bit ln mn

hnh.

Ta cn lu rng buffer hin th nh nh a ch theo dng mng mt chiu:

Hnh 4-3 Cch nh a ch mng mt chiu

Trong khi cc mng nh dng x l li c lu di dng mng hai chiu

tin x l. i a ch nh t dng mng hai chiu sang mng mt chiu ta s dng biu

thc:

row 0, col 0 row 0, col 1 row 0, col 639 row 1, col 0... ... row 479, col 639


75

_ = ( 9) +

v nh xm nh dng 8 bit cn chuyn i nh dng 8 bit thnh 16 bit.

Cch n gin nh sau:

= = 8 3

= 8 2

Di y l mt on code v nh xm 8 bit ln mn hnh bt u ti im c ta

(x, y) trn mn hnh VGA:

void draw_gray(gray_struct *g,int x,int y)

{

volatile short * pixel_buffer = (short *) 0x01400000;

int i, j,offset_frame;

unsigned short m;

for(j=0; j < g->Height; j++)

{

for(i=0; i < g->Width; i++)

{

offset_frame = ((y+j) data[i][j]>>3)>2)>3));

*(pixel_buffer + offset_frame) = m;

}

}

}

Gray_struct l struct c nh ngha lu nh gray 8 bit:

typedef struct{

unsigned char **data;

short Width;

short Height;

}gray_struct;

Hin th ch ln mn hnh

Cch hin th ch ln mn hnh rt n gin. Ta ch cn ghi vo a ch ca character

buffer m ASCII tng ng

Hnh 4-4 Cch nh a ch trong character buffer Sau y l on code vit mt chui k t ln mn hnh bt u ti v tr c ta (x,

y), chui k t c kt thc bng gi tr ASCII bng 0 nh sau:

void VGA_text(int x, int y, char * text_ptr)

{

int offset;


76

volatile char * character_buffer = (char *)0x1480000; //

VGA character buffer

/* assume that the text string fits on one line */

offset = (y


77

*(LCD + 1) = *(text_ptr); // write to the LCD Data register

++text_ptr;

}

}

H thng PushButtons v SW

PushButtons v Slider Switches giao tip vi core x l thng qua cc port song song.

Mc ch ca h thng nt ny l ngi dng chn hnh c x l.

Slider Switches s dng SW2, SW1, SW0 chn s th t nh cn x l.

Sau khi chn nh bng SW xong nhn KEY1 xc nhn. Lc ny chng trnh s

xy ra ngt, trong chng trnh ngt s cp nht li th t file nh nh c chn. Chng

trnh x l nh tip theo s x l nh mi nht c cp nht.


78

5. KT QU THC HIN

5.1. Cch thc o c, th nghim

S dng cc nh chp x l nhn din bin s

Thu thp cc mu hun luyn l cc nh chp bin s xe trong bi gi xe, ct

ri ch s bng phn mm trn my vi tnh ri hun luyn trn Matlab

5.2. Gii thch v phn tch v kt qu thu c

Kt qu thu c:

Xy dng c h thng SOPC thc hin chc nng h thng x l nh.

Nhn din c chnh xc mt vi bin s.

Hiu v cc thut ton x l nh.

Phn mm c thit k vi vic ti u ha thi gian.

Hnh 5-1 nh u vo


79

Hnh 5-2 nh chp mn hnh VGA sau khi nhn dng

Khuyt im ca ti

Kt qu l vng bin s ch c ct chnh xc trong cc nh c cnh bin s c vin

en r rng, vin inox gn nh tht bi. iu ny l do qu trnh pht hin cnh bng mt n

Sobel cha tt.

Ch s c nhn dng kh tt, tuy nhin kt qu nhn dng c th b sai nu nh b

nghing d gc nghing kh nh. iu ny l do phng php trch chn c trng dng hnh

chiu cha tt.

D c gng ti u gii thut t thi gian x l nhanh nht nhng tc nhn

din vn khng p ng c yu cu ca vic nhn din bin s xe. Nguyn nhn l do

nhng hn ch v phn cng: b nh truy cp tc nhanh nh b nh on-chip v SRAM

nh, core x l Nios II/s tc x l khng cao, s dng xung clock tc thp trn kit.


80

6. KT LUN V HNG PHT TRIN

6.1. Kt lun

Nhn chung ti hon thnh c bn vic thit k SOPC v lp trnh cho core Nios

thc hin c vic nhn din bin s.

Sau khi thc hin ti ny em c thm kinh nghim v cc gii thut x l nh ni

chung v bi ton nhn din bin s xe ni ring. Vic t lp trnh tt c cc hm x l nh

bng code C gip cho em nhiu kinh nghim hn trong t duy lp trnh. Tuy nhin cng v

vy m cc gii thut x l trong ti nm mc c bn. Tc x l ca h thng thp

cng l l do khin cho vic p dng cc gii thut vi tnh ton phc tp l khng th.

6.2. Hng pht trin

H thng SOPC ti ny c xy dng mt cch cn bn, cn nhiu khuyt im.

Em hy vng c th tch ly thm kinh nghim xy dng c h thng hot ng tt hn

ti ny khng mi, tuy nhin l mt ti tt cho vic rn luyn cc k nng v

phng php trong lnh vc x l nh, l tin gii quyt cc vn phc tp hn. Trong

tng lai em s c gng nghin cu tm c gii thut tt hn cho qu trnh nhn din

bin s xe.


81

7. TI LIU THAM KHO

[1] Altera, "Introduction to the Altera SOPC Builder Using Verilog Designs".

[2] "M hnh mu RGB," [Online]. Available:

http://vi.wikipedia.org/wiki/M%C3%B4_h%C3%ACnh_m%C3%A0u_RGB.

[3] Goccay, "[X l nh] Xoay nh," 2012 4 13. [Online]. Available:

http://goccay.vn/showthread.php?4601-Xu-ly-anh-Xoay-anh.

[4] G. Owen, "2D Rotation," 2 6 1999. [Online]. Available:

http://www.siggraph.org/education/materials/HyperGraph/modeling/mod_tran/2

drota.htm. [Accessed 2013].

[5] "Support vector machine," Wikipedia, [Online]. Available:

http://en.wikipedia.org/wiki/Support_vector_machine.

[6] Altera, "Video IP Cores for Altera DE-Series Boards," Altera, 2012.

[7] J. D. Bakos, Writer, Embedded Systems Video Out and Image Transformation.

[Performance]. University of SouthCarolina.

[8] "C ch DMA," Wikipedia, [Online]. Available:

http://vi.wikipedia.org/wiki/C%C6%A1_ch%E1%BA%BF_DMA.

[9] Altera, "Clock Signal for Altera DE-Series Boards," Altera, 2011.

[10] Altera, "Media Computer System for the Altera DE2 Board," Altera, 2010.

[11] Altera, "Parallel Port for Altera DE-Series Boards," Altera, 2011.

[12] Altera, "16x2 Character Display for Altera DE2-Series Boards," Altera, 2011.

[13] Malab, "Matlab Product Help," Matlab.

[14] P. A. Phng, Mt s phng php trch chn c trng hiu qu cho bi ton

nhn dng ch vit tay ri rc, Tp ch khoa hc i Hc Hu, s 53, 2009.

[15] P. Breeuwsma, "Cubic interpolation," [Online]. Available:

http://www.paulinternet.nl/?page=bicubic.

[16] H. D. Hiu, c nh bitmap t SD card hin th mn hnh VGA trn kit DE2,

H Ch Minh: LVTN K s, i hc Bch Khoa TP.HCM, 2013.


82

[17] University Program. [Performance]. Altera Corporation.


83

8. PH LC

M Verilog gn chn cho h thng SOPC:

module Example_3_Both_Buffers (

// Inputs

CLOCK_50,

SW,

// Bidirectionals

// Memory (SRAM)

SRAM_DQ,

// Outputs

// Memory (SRAM)

SRAM_ADDR,

SRAM_CE_N,

SRAM_WE_N,

SRAM_OE_N,

SRAM_UB_N,

SRAM_LB_N,

// VGA

VGA_CLK,

VGA_HS,

VGA_VS,

VGA_BLANK,

VGA_SYNC,

VGA_R,

VGA_G,

VGA_B,

DRAM_ADDR,


84

DRAM_BA_0,

DRAM_BA_1,

DRAM_CAS_N,

DRAM_CKE,

DRAM_CS_N,

DRAM_DQ,

DRAM_UDQM,

DRAM_LDQM,

DRAM_CLK,

DRAM_RAS_N,

DRAM_WE_N,

FL_DQ,

FL_ADDR,

FL_WE_N,

FL_RST_N,

FL_OE_N,

FL_CE_N,

//KEY

KEY,

//LCD

LCD_DATA,

LCD_BLON,

LCD_EN,

LCD_ON,

LCD_RS,

LCD_RW,

);

/********************************************************************/

// Inputs

input CLOCK_50;

input [17:0] SW;


85

// Bidirectionals

// Memory (SRAM)

inout [15:0] SRAM_DQ;

// Outputs

// Memory (SRAM)

output [17:0] SRAM_ADDR;

output SRAM_CE_N;

output SRAM_WE_N;

output SRAM_OE_N;

output SRAM_UB_N;

output SRAM_LB_N;

// VGA

output VGA_CLK;

output VGA_HS;

output VGA_VS;

output VGA_BLANK;

NHẬN DIỆN BIỂN SỐ XE BẰNG KIT DE2 DÙNG NIOS II

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