NexGen Vertical GaN Enhancement Mode Gate Drive Interface ...€¦ · © Copyright 2020 NexGen Power Systems Inc. | Proprietary and Confidential 1 NexGen Vertical GaN™ Enhancement

© Copyright 2020 NexGen Power Systems Inc. | Proprietary and Confidential 1

NexGen Vertical GaN™ Enhancement Mode Gate Drive Interface Design __________________________________________________________________________________________________

Contents 1. Introduction 2. NexGen Vertical GaNTM Characteristics 3. Gate Drive IC Characteristics 4. Gate Drive Interface 5. Gate Drive Analysis 6. Idealized circuit simulation 7. Applications/Simulations 8. Hard Switch Totem Pole False Turn on vs. Component Variation 9. Reverse Bias Effect on Dead Time Reverse Conduction Losses 10. Initial Pulse Bias in a Totem Pole Boost 11. ZVS Resonant Switching LLC simulation 12. Component Selection for Driver Interface Design 13. NexGen Gate Drive Evaluation Board 14. Summary

Introduction NexGen has created a high voltage, low Rds,on GaN transistor (Figure 1) with a significant decrease in die area and cost over other lateral

GaN solutions. Further, NexGen’s JFET is also cost competitive with Si MOSFETs, Si IGBTs and SiC MOSFETs while offering significant

advantages over them in switch mode power supplies.

A standard JFET depletion mode transistor is “on” with zero bias gate voltage. It requires a negative voltage on the gate to increase

the depletion layer sufficiently to pinch off the channel and turn the transistor off. A normally-on JFET requires a cascode arrangement,

(typically a low voltage MOSFET in series with the source of the depletion mode JFET) if it is to be used as a power transistor in a switch

mode power supply. To eliminate the need for a cascode configuration, the NexGen’s Vertical GaNTM Vertical GaN-on-GaN JFET channel

structure and doping concentration is designed to shift the turn on threshold level above zero, providing a low Rds,on enhancement-

mode operation that guarantees the device is off with zero gate to source bias.

NexGen’s JFET gate characteristics are distinctly different from the common isolated gate MOSFET. It has a physical PN junction from

the gate to the channel (source and drain) with a typical forward voltage of 3.5V. It also has no body diode that can be forward biased

when the device goes from on to off. The JFET channel conducts when the gate to source voltage exceeds the threshold voltage. This

bidirectional JFET channel conducts in the reverse direction while eliminating the typical Qrr problems associated with a MOSFET body

diode.

While shifting of the JFET threshold voltage Vth to +1.25V eliminates the normally on JFET characteristic, the threshold voltage is low

when compared to an isolated gate MOSFET (typically 5V). Low threshold voltage has its benefits as it results in the reduction of the

energy dissipated while driving the gate. On the other hand, low threshold voltage has to be managed so that shoot through voltages

don’t falsely turn on the channel, especially during drain bounce conditions.

A low threshold voltage combined with the 3.5V gate diode forward voltage are the primary considerations when designing the gate

drive interface for NexGen’s Vertical GaNTM enhancement mode JFET.


Figure 1: NexGen Vertical GaNTM High Conduction Enhancement Mode JFET.

This document uses the spice model developed by NexGen for its 1200V, 85mΩ device to examine its gate drive requirements using

commonly available gate drive ICs. The simulation and analysis examine power requirements, the effect of parasitic components of

the transistor, the gate drive source impedance and PCB layout parasitics. Both hard switching and resonant switching circuits are

examined.

The performance limitations vary with device package, layout and the associated parasitics. NexGen Vertical GaNTM is offered in a TO-

247 and QFN packages. Stray package inductance varies with package type.

NexGen Vertical GaN Characteristics Figure 1 shows a schematic representation of the device with a graph of the gate charge characteristics. The gate drive must charge

the input capacitance (Ciss=Cgs) to the miller plateau voltage followed by discharging Cgd=Crss from the peak drain voltage. Figure 3 plots

the channel current as a function of the gate to source voltage. The threshold voltage is 1.25V with channel current reaching over 30A

at a 2.5V gate voltage. Figure 4 characterizes the gate diode forward voltage and current exhibiting a forward voltage near 4V. A low

threshold voltage combined with NexGen’s Vertical GaN fast drain dv/dt, makes the gate node vulnerable to spikes coupled to the

gate via the drain to source capacitance, creating a potential for a false turn on. Gate to source and drain diodes also conduct when

forward biased to Vf of 3.5V. This leaves a very narrow voltage range between when the device is fully on and when the gate diode

begins to conduct. A low impedance drive above the Vf voltage is not acceptable due to the excessive gate diode current that would

result.

Cds

Cgd

CgsRint

Vth≈1.25V

Vf = 3.5V

Vf = 3.5V

Vth

Vp

Vf

Qgs Qgs+Qgd Qgt

Qg

Vg

Ron

Transistor


Figure 2: Vertical GaN™ FinFET Equivalent Circuit.

Figure 3: Channel Current vs. Gate to Source Voltage Figure 4: Gate Current vs Gate to Source Voltage

NexGen’s Vertical GaNTM Device Properties NexGen’s Vertical GaNTM NXG2EB120985, 1200V 85mΩ vertical JFET properties are summarized in Table 1 with typical non-linear

capacitances shown in Figure 5. The transistor is offered in a QFN and TO-247 package. Each package has a separate Kelvin connected

source pin to isolate the gate drive from the source power path. Typical inductances for each package are shown in Table 3 with the

gate drive PCB loop inductance included. Table 2 breaks down the total gate charge (Qg) required drive the gate to 3.5V for various

drain voltages. The corresponding average bias current for a 1MHz switching frequency is also displayed.

Symbol Parameter Unit

BVds Drain to Source Breakdown (min.) 1200 V Vgs=0V, Id=100A

Rds,on Drain to source resistance (typ.) 85 mΩ Id=15A, Vgs=2.75V, Tj=25C

Vth Gate Threshold 1.2 V Vds=5V, Id=1mA

Qg Total Gate Charge 16.9 nC Vds=960, Vgs=0 to 3.2V, Id=16A

Vf Gate diode Forward Voltage 3.5 V

Rg Gate Resistance 1.5 Ω Open Drain, f=1MHz

gm Transconductance

Qoss Output Charge Vds=800V

Eoss Energy stored in output capacitance Vds=800V Table 1: NexGen JFET data sheet parameters.

Vds (V) Qg (nC) Igate (mA) @ 1MHz

200 4.7 4.7

400 7.5 7.5

600 9.6 9.6

800 11.1 11.1 Table 2: Gate current and turn on time vs. drain Voltage


Figure 5. Ciss, Coss, and Crss vs. Vds

Ct Rt

Rd

Ld

Ls

Lg

0V

5-12V

Cds

Cgd

Cgs

Interface

Transistor

Figure 6: Detailed Model of device parasitics (blue box) and interface circuit (red box).

Package Source Inductance (nH)

LS

Drain Inductance (nH) Ld

Total Gate Loop Inductance (nH) Lg

TO-247 1.5 1.5 10

QFN 0.1 0.05 10 Table 3: Inductance of various packages for FinFET.


Gate Drive IC Characteristics For this document, all viable gate drive IC candidates are 1MHz switching frequency capable. The properties of various “off-the-shelf”

1MHz capable drivers that are shown in Table 4. Figure 8 shows Silicon Lab’s Si8273 driver interfaced to NexGen’s Vertical GaNTM

device. The driver output is modeled as a 2.7 source resistance and 1.8A current limit when high and a 1 and 4A current sink limit

when low with rise and fall times of 10.5ns and 13.3ns respectively.

Parameter Si8273 Si8238AD UCC21520 Unit

Maximum Driver side Supply Voltage 30 24 25 V

UVLO 3.5, 5.5, 8.3,12.2

5.8,8.6, 11.1,13.8

5.7,8.2 V

Isolation Output to Output 1.5 2.5 1.5 kVrms

Isolation Input to Output 2.5 5 5.7 kVrms

Output Current 1.8 source,

4.0 sink 2.0 source,

4.0 sink 4.0 source,

6.0 sink A

Output Impedance 2.7 source

1 sink 2.7 source

1 sink 5.0 (1.47)

source, 0.55 sink

Ω

Rise/Fall Times 10.5/13.3 @ 200pF

12 @ 200pF

6/7 @ 1.8nF

ns

Propagation delay matching 5 ns

Common mode transient immunity 200 45 100 V/ns Table 4. Typical Driver Properties

Gate Drive Interface For a gate drive interface to be compatible with the NexGen’s Vertical GaNTM JFET, it must have a low source impedance – up to the

gate diode Vf (3.5V) at which point it must be current limited. With a 1.25V threshold voltage, we also need to consider a sufficiently

negative off voltage to prevent the gate from being pulled above the threshold voltage during the Vds turn off transition.

The network Rd, Rt, and Ct in Figure 7 combined with a unipolar gate drive meets these requirements by providing a low impedance

path through Rt and Ct past the threshold voltage and up to the gate diode junction voltage. When the gate diode voltage becomes

forward biased Ct charges to Vg-Vf and Rd limits the gate current. At turn off the voltage on Ct (Vg-Vf) drives the gate negative, providing

margin from a false turn on due to the fast drain dv/dt at turn off.

A loosely regulated single rail bias supply and the inherent diode limited gate voltage eliminates many of the common concerns

associated with other GaN transistors. This is one of the cost advantages of the Vertical GaNTM JFET – it does not need an expensive,

tightly regulated rail bias supply.


Cds

Cgd

Cgs

Vth≈1.25V

Vf = 3.5V

Vf = 3.5V

Rt

Rd

CtVinVf

Interface

Transistor

Driver

Figure 7. Proposed Interface for NexGen’s e-mode Vertical GaNTM JFET. The blue short dashed box shows the JFET model and the large dashed

red box shows the interface model. The standard driver is on the left.

Vth≈1.25V

Vf = 3.5VI

s

o

l

a

t

i

o

nUVLO

5V

Vi

UVLO

Driver IC

Interface

Transistor

CtRt

RdVg

Vs

Cgd

Cgs

CdsRint

Vf = 3.5V

Figure 8: Gate Drive for NexGen’s e-mode Vertical GaNTM JFET with interface circuit.

Gate Drive Analysis

Turn-On Condition

Figure 9 details the gate voltage at turn-on. Prior to reaching the plateau voltage (Vp), during time t1, the gate capacitance is equal to

Ciss=Cgs+Cgd. The plateau voltage (Vp) is the gate voltage required to achieve the drain load current. During this phase of turn-on, the

drain voltage does not change. Since Ct and Ciss see the same charge, the equality in Equation 1 can be used to solve for the gate

voltage. Equation 3 expresses the time to charge to the plateau. Note that Ciss is not linear and varies with voltage while the equations

below assume a constant capacitance. Rt is the combination of the driver source resistance, the interface network resistance, and the

internal transistor gate resistance.

(𝑉𝑖𝑛 − 𝑉𝑔𝑠) ∙ 𝐶𝑡 = 𝑉𝑔𝑠 ∙ 𝐶𝑖𝑠𝑠 (1)

𝑉𝑔𝑠 =𝑉𝑖𝑛

1+𝐶𝑡

𝐶𝑖𝑠𝑠

(2)

𝑡1 =−𝑅𝑡∙𝐶𝑡∙𝐶𝑖𝑠𝑠

𝐶𝑖𝑠𝑠+𝐶𝑡∙ ln (1 −

𝑉𝑔𝑠

𝑉𝑖𝑛 ∙ (

𝐶𝑡+𝐶𝑖𝑠𝑠

𝐶𝑡)) (3)


VthVp

Vf

t1t

Vg

Vds

t2 t3

IdVd

Id

Vg

t

Figure 9: Turn-on.

During the second phase of turn-on the gate to source voltage and charging current is constant while the drain to gate capacitance

(Cgd=Crss) discharges. Equation 4 gives the time (t2) required to charge the gate past the plateau voltage.

𝑡2 =𝑅𝑡∙𝐶𝑟𝑠𝑠∙𝑉𝑑𝑠

𝑉𝑖𝑛−𝑉𝑔𝑠 (4)

During the final phase of turn-on, the gate drive charges the gate above the plateau to the level where the gate diode conducts. At

this point the gate voltage is clamped by the gate diode and the series capacitor Ct continues to charge to Vin-Vf. Once Ct charges to

the steady state value the gate diode current is limited by Rd. The steady state current into the gate after forward biasing the gate

diode is:

𝐼𝑓𝑤 =𝑉𝑖𝑛−𝑉𝑓

𝑅𝑑 (5)

Turn-Off Condition

At turn-off, Ct must absorb the turn-off gate charge and force the gate voltage negative. For a Ct that is much greater than Cg the initial

gate voltage at turn-off is 𝑉𝑓 − 𝑉𝑖𝑛 . For smaller values of Ct, the initial reverse voltage settles at 𝑉𝑓 − 𝑉𝑖𝑛 ∙ (𝐶𝑡

𝐶𝑡+𝐶𝑔𝑠). Equation 6

describes the negative voltage applied to the gate at turn-off, where tc1 is defined in Equation 7. This idealized equation assumes a

fixed Cgs at turn-off which is not the case for the real transistor.

𝑉𝑟𝑖 = 𝑉𝑓 − 𝑉𝑖𝑛 ∙ (𝐶𝑡

𝐶𝑡+𝐶𝑔𝑠) ∙ (1 − 𝑒−𝑡/𝑡𝑐1) (6)

𝑡𝑐1 =𝑅𝑜𝑛∙𝐶𝑡∙𝐶𝑔𝑠

𝐶𝑡+𝐶𝑔𝑠 (7)

An alternate charge balance analysis yields the same steady state result and allows easy substitution of common transistor

specifications that represent the change in capacitance as the transistor is turned off.

Equation 8 equates the charge of Ct and Cgs at turn-off. The initial voltage prior to turn-off is Vin-Vf for Ct and Vf for Cgs. At turn-off the

source voltage steps to zero and the voltage on both capacitors settles to Vr in Equation 9. This voltage is the same as the steady state

value in Equation 6.

𝐶𝑡 ∙ (𝑉𝑖𝑛 − 𝑉𝑓 + 𝑉𝑟𝑖) = 𝐶𝑔𝑠 ∙ (𝑉𝑓 + 𝑉𝑟𝑖) (8)

𝑉𝑟𝑖 = 𝑉𝑓 −𝑉𝑖𝑛∙𝐶𝑡

𝐶𝑡+𝐶𝑔𝑠 (9)


After turn-off, current through Rd continues to charge the transistor gate Cgs. At the end of the “off” time the reverse gate voltage will

have decayed to a less negative potential. Vrf varies with duty cycle and off time. See Figure 10 waveforms.

𝑉𝑟𝑓(𝑡) = [𝑉𝑓 − (𝑉𝑖𝑛∙𝐶𝑡

𝐶𝑡+𝐶𝑔𝑠)] ∙ (1 − 𝑒−𝑡𝑜𝑓𝑓/𝑡𝑐2) (10)

𝑡𝑐2 = 𝑅𝑑 ∗ (𝐶𝑡 + 𝐶𝑔𝑠) (11)

Vf

Vs

VriVrf

Ig

ton toff

Vgs

Vin

t

t

t

Figure 10: Typical Gate Voltage and Current with Interface circuit.

The previous section explains the function of the interface circuit for the gate modeled as at fixed capacitor. This analysis can be

modified to account for the gate charge characteristics where Vf*Cg can be replaced with the gate charge associated with the turn

off (Qg). Replacing Qg and Ciss into Equation 8 gives Equation 12 which gives a solution for Vr in terms of the transistor physical

properties in Equation 13. From this Ct and Vin can be adjusted to give the desired Vr. Qgt is the total gate charge and should be

adjusted according to the in circuit switching behavior.

𝐶𝑡 ∙ (𝑉𝑖𝑛 − 𝑉𝑓 + 𝑉𝑟𝑖) = 𝑄𝑔𝑡 − 𝐶𝑖𝑠𝑠 ∙ 𝑉𝑟𝑖 (12)

𝑉𝑟𝑖 =𝑄𝑔𝑡

𝐶𝑡+𝐶𝑖𝑠𝑠 +

(𝑉𝑓−𝑉𝑖𝑛) ∙𝐶𝑡

𝐶𝑡+𝐶𝑖𝑠𝑠 (13)

The GaN Totem Pole Half Bridge

As mentioned in the introduction, NexGen Vertical GaNTM has no body diode and Qrr= 0. In a totem pole configuration (Figure 11), one

device acts as a diode or freewheeling device and the other as a control device. The control device drives the inductor tied to the

switch node and the freewheeling “diode” device clamps the switching node and provides a current path for the inductor during the

dead time (after the control device has turned off and prior to the freewheeling device turning on). When a MOSFET is used for the

freewheeling device the body diode can conduct during the dead time and a large Qrr current can flow through the control device

when it turns on.

For a bridgeless Power Factor Corrected (PFC) boost the high side device is the “diode” during the positive AC half-cycle, and for a

synchronous buck the low side device is the “diode” (assuming the output is sourcing current). For NexGen’s Vertical GaNTM the

reverse current of the freewheeling “diode” conducts through the channel and when the control FET turns on there is no Qrr, only

current required to charge Coss of the freewheeling device. This GaN Totem Pole performance reduces switching losses and opens the

door to a higher switching frequency and reduced component size over MOSFET designs. Consequently, we will focus on the gate drive

characteristics of various Totem pole half bridge applications.


GaN Totem Pole Gate Drive Interface Network

For the typical totem configuration associated with most all GaN applications the high side and low side turn-off scenarios are

different. Figure 11 is a bridgeless PFC boost totem pole schematic. Figure 12 illustrates the differences in turn-off for the high side

and low side transistors in the totem pole PFC circuit. For J1 turn off during t1, Cgs-Ciss is discharged from the gate diode forward

voltage Vf to the negative bias voltage (Vr1). The drain to source voltage of J1 does not significantly change until J2 turns on after the

dead time. During the dead time the LX node is clamped to the output voltage through J1. For J2 turn-off, the drain voltage changes

as soon as the gate voltage reaches the plateau. For these two turn-off conditions the total gate charge (Qg) will be different and

result in a different gate reverse voltage after turn-off.

J1

J2

IL

Lx

Vout

Vin

Figure 11: Boost PFC Totem Pole Power Stage

Vth

Vp

Vf

Vds

td

Id

Vri1

t1

Vrf1

J1Vd

Id

t

V

Vg

t

Vth

Vp

Vf

Vri2

Vds

t1t2

Id

J2

t3

Vrf2

Vd

Id

Vg

t

t

𝑉𝑟𝑖1 =𝑄𝑔𝑠

𝐶𝑡 + 𝐶𝑖𝑠𝑠

+ (𝑉𝑓 − 𝑉𝑖𝑛) ∙ 𝐶𝑡


𝑉𝑟𝑖2 =𝑄𝑔𝑡


+ (𝑉𝑓 − 𝑉𝑖𝑛) ∙ 𝐶𝑡


Qgs=0.6nC Qgt=10nC Figure 12a: J1 Turn-off. Figure 12b: J2 Turn-off.

Figure 12: Totem Pole Boost Turn-off.


𝑉𝑟𝑖1 =𝑄𝑔𝑠



𝐶𝑡+𝐶𝑖𝑠𝑠 (a) 𝑉𝑟𝑖2 =

𝑄𝑔𝑡



𝐶𝑡+𝐶𝑖𝑠𝑠 (b)

Figure 13: Reverse Voltage vs. Vin and Ct

Idealized Circuit Simulation The following simulation results demonstrate the circuit behavior for the initial pulses to a simplified model of the transistor. The

waveforms in Figure 15 show how the off voltage and peal gate current varies during the initial gate pules. Note that prior to any

gate drive pulses there is no reverse bias on the gate. Only after the initial pulse has a charge built up on Ct and a reverse voltage

seen at Vgs after turn-off. Until Ct charges to Vin-Vf, the diode current is limited by Rt at which time the diode current is then limited

by Rd. The initial reverse voltage decays during the off-time as Ct discharges through Rd. Rd is sized to limit the steady state current

into Vf and reduce the reverse voltage prior to the subsequent dead time.

Cgs

VfRt

Rd

CtVin

Vgs

Interface

Transistor

Driver

Figure 14a: Simple gate charge circuit.

Figure 14b: Simulation Schematic.


Figure 15: Simulation results of simple circuit. Rt=4.7 Ohms, Ct=3.3nF, Vf=3.5V, and Rd=1kΩ, and Cgs=95pF, Vin=12V.

Applications /Simulations Totem pole applications can be hard switched, soft ZVS switched, or have a combination of both types of transitions. The optimum

gate drive interface solution will depend on the application and the characteristic of switching.

Simulation schematics are shown in Figures 16 and 20. An Inductor/transformer is assumed to be tied to the switch node and is

modeled by a constant current source flowing either into or out of the switch node. The direction of the current flow will determine

whether the high side or low side device is acting as the “control” switch while the other device is acting as the freewheeling or “diode”

clamp. Current flowing into the switch node will drive the source of the high side device high, forward biasing the transistor (J2) during

the dead time.

Totem Pole PFC Boost Simulation The simulation below continues to examine the differences in initial reverse voltage seen at turn-off for totem pole transistors in a

boost configuration as explained in Figure 12.

For the low side device, Cgd is charged at turn-off as seen by the extended gate to source plateau for V(lg) in figure 18. As a result,

the low side gate (V(lg)) reverse gate voltage after turn-off is less than 5V. This contrasts with the high side reverse gate voltage

(V(hg)-V(lx)) shown in Figure 19. In this case, the LX node is clamped near the drain voltage after the high side device turns off. Cgd

does not see a large swing in voltage and the reverse voltage after turn-off is close to 7V, more than 2V greater than the initial

reverse bias seen for the low side device.

Figure 17 waveforms show that after turn-off of the high side “diode” device (J2) there is no immediate large swing in the drain

voltage until after the dead time. The result is a spike in the gate voltage (V(Hg)) after the dead time for the freewheeling “diode”

switch. For the control switch (J1), the drain voltage transition is simultaneous with the gate turn-off (V(Lg)). Since the drain voltage

of the two devices behaves differently in this circuit, there will be characteristically different gate voltage waveforms.


Figure 16: Totem Pole Boost Simulation Schematic.

Figure 17: Totem Pole Boost Simulation Waveforms.


Figure 18: Expanded LG turn off from Figure 17.

Figure 19: Expanded HG turn off from Figure 17.


Hard Switch Totem Pole False Turn on vs. Component Variation Simulations and gate drive waveforms

Figure 20 shows a schematic for a totem pole PFC boost with stray inductance included.

Simulating with stray inductance is important for verifying gate drive interface component values, initial pulse behavior, and potential

false turn on issues associated with totem pole circuit. Excessive stray inductance and fast switching (fast di/dt) can also lead to energy

stored in the stray inductance and ringing at both the drain and gate. The series resistance (Rt in Figure 8) can be adjusted to slow

down the transistor in this case but care must be taken to avoid increases in switching losses.

Simulation results are shown in Figures 21-23 for the interface circuit series capacitor ranging from 3.3nF to 6.8nF.

Figure 20: Totem Pole Boost.

Figure 21: PFC totem pole simulations result.


Figure 22: High side turn off, Ct=3.3nF, 4.7nF, and 6.8nF.

Figure 22 details the high side turn-off followed by the dead time and the subsequent turn on of the low side device. As LX

transitions the high side transistor gate is pulled above the threshold level causing a spike in the current in the high side drain

current (Id(J2)). The three solutions show how the reverse bias and false turn-on current varies with Ct (which is varied from 3.3nF,

4.7nF to 6.8nF) with the source voltage at 12V.

Figure 23. Low side turn-off, Ct=3.3nF, 4.7nF, and 6.8nF

Figure 23 details the low side turn off followed by the dead time and the subsequent turn on of the high side device. The LX node

transitions simultaneously with the turn-off of the low side device as evidenced in the extended miller plateau (V(LG)) as the drain to

gate capacitance of the low side transistor is charged. In this case there is very little change in switching behavior as a Ct is varied

from 3.3nF to 6.8nF.


Reverse Bias effect on Dead time reverse conduction losses

Although reverse bias gate drive helps to prevent or limit the false turn on effects discussed in previous sections, it also increases the

reverse voltage clamp level during the dead time where both totem pole transistor are off, and current is driven into the source of the

freewheeling device. When the transistor is acting as a clamp during the dead time, the gate to drain voltage increases to the threshold

level and the transistor channel conducts. When the gate voltage is driven negative with respect to the source voltage the source to

drain voltage necessary for conduction must increase by the same amount. The schematic and simulation results shown in Figure 24

and 25 demonstrate the reverse conduction voltage vs. the negative voltage applied to the gate. The source to drain voltage necessary

for conduction increases by the sum of the Vt+Vgateoff. This increases losses during the half bridge dead time.

The initial reverse bias after the “turn-off” of the high side transistor in the PFC half bridge must be enough to reduce the false turn-

on effect. The reverse bias that proceeds the subsequent high side turn on can be reduced by adjusting the resistor Rt in Figure 6. Rt is

in parallel with Ct and Cgs during the high side off time with the time constant shown in Equation 11. This discharge of Ct via Rt helps

to reduce the deadtime losses during the deadtime immediately preceding the next high side turn on. This is seen in figure 15 as the

gate reverse (Vgs) voltage decays from -8V to -5V during the off time.

Figure 24: Reverse conduction voltage vs. negative gate voltage.

Figure 25: Reverse conduction voltage vs. reverse gate drive bias.


Initial Pulse Bias in a Totem Pole Boost

As shown in Figure 15, the gate drive interface capacitor (Ct) is not charged until after the first gate pulse, leaving no

negative pre-bias for the initial gate pulse. This can potential result in a false turn and very high shoot-thru current during

the first gate pulse at start up on during recovery from a fault condition. In Figure 26, the same gate drive interface circuit

is used except it is placed in series with the source and stray inductances are removed to focus on the initial pulse shoot

through current behavior. In Figure 26a the initial gate pulse is on the low side and since there is no negative bias on the

high side gate where there is a large shoot through current in Id(J2). In Figure 26b the first gate pulse is on the high side

and the LX node is at a high voltage. In this case a limited shoot thru current is seen when the low side device turns on.

The schematic in Figure 27 shows the same interface circuit with an additional pre-bias through a Zener connection to the

gate side on the ac coupling capacitors C2, and C3. The Zener is tied to a 12V supply rail to provide negative bias to the

gate to source at the initial pulse. The results in figure 27a and b demonstrate the elimination of the shoot through current

that was seen without the Zener connected pre-bias during the initial gate pulse.

Figures 28a and 28b detail the pre-bias improvement when the low side device turns on first.

The initial pulse condition can occur at start up and at any time there has been an absence of pulses over a sufficient time

to totally discharge Ct. This can happen during a recovery from a fault condition or any other temporary shut-down.

(a)


(b)

(c) Figure 26. AC coupling interface with no Pre-bias.

(a) Low side initial pulse (b) High side initial pulse


(a)

(b)

(c) Figure 27: Pre-biased AC coupling capacitor.

(a) Low side initial pulse. (b) High side initial pulse.


(a) High side pulse first shoot-thru with no pre-bias (schematic 25a)

(b) High side pulse first shoot-thru with pre-bias (schematic 25b)

Figure 28. Shoot-thru comparison with low side pulse first

ZVS Resonant Switching LLC Application In ZVS resonant switching converters, the drain voltage transition is driven by the inductance connected to the switch node, presenting

a current source during the dead time when both totem pole transistors are off. The dv/dt is slower than the hard switching dv/dt and

hence less susceptible to false turn-on conditions. Figure 29 shows the extended plateau for both the high side and low side gate

drive during the dead time. This is like the behavior of the low side turn-off gate drive of the bridgeless boost previously discussed. In

this case, since the dv/dt is limited and false turn on not expected, the primary purpose of the gate drive AC coupling capacitor is to

limit the gate diode current when the gate Vf is exceeded.

Figure 29. LLC Gate Drive Simulation Results.


Figure 30. LLC Gate Drive Schematic.

Component Selection for Driver Interface Design 1. Review Figure 3 graphs and the respective equations to select a drive voltage and series capacitance to obtain a desired

reverse voltage. The optimum reverse voltage and series capacitance will limit the gate voltage to less than the threshold during switching transitions.

2. The series resistance (Rd in Figure 7) should sufficiently dampen the PCB gate drive loop. A ‘q’ of 0.5 eliminates ringing. Assuming a 5nH loop inductance and series capacitance totaling 1nF to 6.8nF a rough estimate of the series resistance necessary to dampen the network can be derived from Equation 14. Minimum values for damping will range from 2.3Ω to 6Ω depending on the series capacitance (Ct+Cgs) and layout. For package versions that have a higher stray inductance this resistance may need to be further increased to limit the drain to source di/dt and reduce ringing.

𝑄 =𝑅𝑜

𝑅 = √

𝐿

𝐶 (13)

𝑅 ≥ 2 ∙ √𝐿

𝐶 (14)

3. Due to the high dv/dt during hard switching transitions, more reverse bias will be necessary than in a resonant soft switching

power stage. 4. Minimize loop area/inductance for gate drive and power path. Additional increase in the gate series resistance may be

necessary to limit switching speed and ringing. 5. Typical values for Rt range from 1 Ω to 20Ω and 1nF to 10nF for Ct. 6. Nominal Rd values range from 500 to 2k. Rd limits the gate diode forward current and discharges Ct during the off-time to limit

the dead time losses immediately prior to the next turn-off. Rd must also guarantee a minimum of 1mA gate diode drive current.


NexGen Gate Drive Evaluation Board NexGen offers an evaluation board that demonstrates methods for adapting a typical isolated drive IC to NexGen’s GaN

transistors. The NexGen driver board has two DC-DC converters that provide isolated 15V bias for both the high side and

low side of a totem pole power transistor stage. The drive bias can be adjusted from +15V to positive rail and 0V negative

rail for MOSFET drive, to a 0V positive rail to a -15V negative rail for a depletion mode JFET transistor drive. Figure 31 show

the complete driver board schematic with options for of reverse bias. Negative bias rails can be generated by splitting the

bias rails with a capacitive divider and Zener (D7 and D8) network or with a unipolar bias rail and driving the source of the

power transistor high with through a Zener connected to the positive bias rail (see D9 and D14).

The layout accepts both TO247 and DFN 8x8 packaged power transistors and the power connections include a capacitive

divider with an input voltage range of up to 1kV. The switch node of the totem pole stage ties to a 128uH inductor with a

1.5A saturation current connected to the input power divider. High current power connections are available for high power

external passive components for either buck or boost application.

The 5V bias, PWM and enable inputs are supplied externally via the J1 connector. The PWM pulse with and dead time can

also be adjusted to evaluate both soft and hard switching.

Figure 32 schematic shows is reduced to only those components necessary for a depletion mode JFET drive.

Figure 33 shows waveforms with the gate drive set up for zero to -15V bias to drive depletion mode JFET UJ3N120070K3S.

In summary the NexGen totem pole evaluation demonstrates the simplicity of adapting a typical isolated gate drive IC to

drive NexGen’s depletion or enhancement mode devices with device gate thresholds ranging from -10V to +10V.

Figure 31. Driver Board schematic complete

1

1

2

2

3

3

4

4

5

5

6

6

D D

C C

B B

A A

Title

Number RevisionSize

B

Date: 2/20/2020 Sheet ofFile: C:\Users\..\TI bias GaN Gate Drive Test Board.SchDocDrawn By:

25V10uF

C8

R751.1k

AGND

En

5V

VoA

VoBGL

Drive

0R2

R1120

PVin

PWM+

rtnEN

5V

630V0.47uFC6

D11

Vcc2

D23

GND4

EN5

CLK6

U2

SN6505BDBVT

Wurth

760390014

1

2

34

5

6

T1

D1MBR0520LT1G

D2MBR0520LT1G

TDKACM2520-601-2P-T002

1

2

4

3L1

16V

D325V

10uFC1

25V10uFC9

25V10uFC10

50V0.1uF

C7

10kR10

630V0.01uFC12

100V47pF

C13

25V10uF

C17

AGND

D11

Vcc2

D23

GND4

EN5

CLK6

U3

SN6505BDBVT

Wurth

760390014

1

2

34

5

6

T2

D4MBR0520LT1G

D6MBR0520LT1G

TDKACM2520-601-2P-T002

1

2

4

3

L2

16VD5

25V10uF

C15

25V10uFC18

25V10uFC19

AGND

DT

PWM

50V220pF

C20

630V0.01uFC11

630V0.47uFC14

4.7nF

C25

1kR6

Vddhs

LX

Vddls

GH

Vsshs Vssls

PVin/2

PWRrtn

Vddls

Vddhs

Vssls

Vsshs

LX

Vddls

VddhsVssls

Vsshs

3 54

1

2

Q4MAN2

3 54

1

2

Q6MAN2

5V5V

2.2

R16

Q1UJC1210K

Q2

UJC1210K

2

10

14 3

9 6 7

5

L3

Net Tie

NT1

Jumper

PWRrtn

LX

1kV1uFC27

1MegR8

1MegR11

1MegR17

1MegR18

1MegR19

1MegR20

2kV220pFC28

10R21

2kV220pFC29

10R22

GL

LX

LSS LSS

EN5

GNDI4

VDDA16

PWM1

DT6

VDDI3

VOA15

GNDA14

VDDB11

VOB10

GNDB9

VDDI8

NC2

NC7

NC13

NC12

U1

SI8274

Vinrtn

Vin

HS2HS1

3

12

45

J1

PWM-

5V5V

6.2V

D14

16VD10

16VD12

Vin/2

Vin

Vinrtn

0

FB1

0

FB2

2.2

R15

2.2

R14

6.2V

D9

6.2VD11

6.2VD13

4.7nF

C26

10kR9

10kR5

1kR4

1k

R13

1k

R12

50V0.1uF

C16

6.2VD7

6.2VD8

2.2

R3

50V1uF

C2

50V1uFC4

50V1uF

C5

50V1uFC3

50V1uF

C22

50V1uF

C23

50V1uF

C21

50V1uF

C24


Figure 32. Depletion mode driver schematic.

Totem Pole Half Bridge Driver Board Top Side Totem Pole Half Bridge Driver Board Bottom Side

Figure 33. Driver Board

1

1

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2

3

3

4

4

5

5

6

6

D D

C C

B B

A A

Title

Number RevisionSize

B

Date: 2/20/2020 Sheet ofFile: C:\Users\..\Copy of TI bias GaN Gate Drive Test Board rev 2 trimmed.SchDocDrawn By:

25V1uFC4

25V10uF

C8

R751k

AGND

10kR9

10kR5

En

5V

VoA

VoB

GL

PWM+

0R2

R1120

25V1uFC3

PVin J2

Vin

PWM+

rtnEN

5V

630V0.47uFC6

D11

Vcc2

D23

GND4

EN5

CLK6

U2

SN6505BDBVT

Wurth

760390014

1

2

34

5

6

T1

D1MBR0520LT1G

D2MBR0520LT1G

TDKACM2520-601-2P-T002

1

2

4

3L1

16V

D3MMSZ4703T1G25V

10uFC1

25V10uFC9

25V10uFC10

25V0.1uF

C7

10kR10

25V47pF

C13

25V10uF

C17

AGND

D11

Vcc2

D23

GND4

EN5

CLK6

U3

SN6505BDBVT

Wurth

760390014

1

2

34

5

6

T2

D4MBR0520LT1G

D6MBR0520LT1G

TDKACM2520-601-2P-T002

1

2

4

3

L2

16V

D5MMSZ4703T1G25V

10uFC15

25V10uFC18

25V10uFC19

AGND

DT

PWM

25V220pF

C20

25V0.1uF

C16

630V0.47uFC14

GH

PVin/2

PWRrtn

Vddls

Vddhs

Vssls

VsshsLX

Vddls

VddhsVssls

Vsshs

5V 5V

2.2

R3

2.2

R16

Q1UJC1210K

Q2

UJC1210K

2

10

1 43

967

5

L31uFC2

1uFC5

J7Vin/2

J8

Vinrtn

J6

LX

1kV1uFC27

1MegR8

1MegR11

1MegR17

1Meg

R18

1MegR19

1MegR20

J11GL

J9LX J10

rtn

J5

Vin

3

12

45

J1

PWM-

EN5

GNDI4

VDDA16

PWM1

DT6

VDDI3

VOA15

GNDA14

VDDB11

VOB10

GNDB9

VDDI8

NC2

NC7

NC13

NC12

U1

SI8274

PWRrtn

IsL

J14

PWM-

5V 5V


Figure 33. Fsw=400kHz, Vdcin=500V Typical Driver board Waveforms. Blue Switch Node Voltage, Yellow Gate Voltage, Green Drain Current

Summary The NexGen Vertical GaNTM JFET transistor gate drive interface must account for the characteristics of the transistor that

differentiate it from the Isolated Gate MOSFET. The transistor has a gate diode with a forward voltage of 3.5V, a very low

threshold voltage 1.25V, and very fast switching speeds. An interface circuit is proposed that allows the use of standard

highspeed gate drive ICs.

The AC coupled / DC blocking interface network limits the current at the gate when the voltage exceeds the gate diode

forward voltage. This network also forces a negative gate bias voltage during turn-off, thus making the transistor more

immune to false turn-on due to the gate to drain capacitance coupling charge to the gate at turn-off. The interface network

does this with a single bias rail with optimum network values and bias supply voltage varying with application.

With the network there is no negative gate bias protection during the initial pulse, leaving the potential for a false turn-

on at the initial pulse in a totem pole configuration. An additional refinement to the network pre-biases the gate-to-

source voltage negatively prior to the initial gate drive.

The reverse conduction characteristics combined with zero reverse recovery make NexGen’s Vertical GaNTM JFETs an ideal

fit for a totem pole circuit where one of the two transistors function as a freewheeling diode. Characteristic gate drive

behavior with the suggested interface circuit is presented for both a totem pole boost and LLC power stage.

A high voltage totem pole board that demonstrates the implementation of the simple gate drive interface network is also

presented.

NexGen Vertical GaN Enhancement Mode Gate Drive Interface ...€¦ · © Copyright 2020 NexGen Power Systems Inc. | Proprietary and Confidential 1 NexGen Vertical GaN™ Enhancement

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