MANAGEMENT SYSTEMS FOR LATERAL SUPPORT IN VECHILE INTRODUCTION Cars and autos converting to gas could be the only solution to our pollution problem. But time and again scares are raised about the safety of this. However, none of the nine reported explosions in vehicles in the city has been caused by an LPG blast, point out the members of the Indian Autogas Association. They add that there has not been a single accident caused by conversion from petrol to gas in city cars or autos LP Gas Leakage can be very dangerous because it increases the risk of Fire or deadly Explosion. Therefore we have planned to develop a system that warns by providing information and sounds an alarm as soon a leakage is detected. But unfortunately those detectors are pretty much expensive. This detector will turn buzzer to corresponding persons as soon as a leakage takes place. Detector will warn you Buzzer that a sound as long as the leakage occurs, stopping only when the problem disappears. This detector is calibrated to detect gas up to 10% of the L.E.L (Low Explosion Limit). Small gas quantities coming out from the left open tank for some MINUTES do not cause the gas detector alarm signaling even if it is clearly nose perceptible; in fact the quantity of gas presents in the environment can be under the alarm threshold.
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MANAGEMENT SYSTEMS FOR LATERAL SUPPORT
IN VECHILE
INTRODUCTION
Cars and autos converting to gas could be the only solution to our pollution problem. But time
and again scares are raised about the safety of this. However, none of the nine reported
explosions in vehicles in the city has been caused by an LPG blast, point out the members of the
Indian Autogas Association. They add that there has not been a single accident caused by
conversion from petrol to gas in city cars or autos LP Gas Leakage can be very dangerous
because it increases the risk of Fire or deadly Explosion. Therefore we have planned to develop a
system that warns by providing information and sounds an alarm as soon a leakage is detected.
But unfortunately those detectors are pretty much expensive. This detector will turn buzzer to
corresponding persons as soon as a leakage takes place. Detector will warn you Buzzer that a
sound as long as the leakage occurs, stopping only when the problem disappears. This detector is
calibrated to detect gas up to 10% of the L.E.L (Low Explosion Limit). Small gas quantities
coming out from the left open tank for some MINUTES do not cause the gas detector alarm
signaling even if it is clearly nose perceptible; in fact the quantity of gas presents in the
environment can be under the alarm threshold.
Drunk driving is very dangerous. Alcohol causes one to not be as aware. It also slows one's
reflexes. This is a real problem when one is driving. Drunk drivers get into car accidents because
they cannot tell what is happening around them or they cannot react fast enough.Drunk driving is
dangerous to many different people. When one drives an automobile while under the influence of
alcohol they put themselves in danger. Because one cannot react as fast to actions happening
around them and their automobile accidents happen and people are killed. Many times it is not
the driver that dies. When this happens not only do the drivers have to go to jail but they have to
live with the fact that they killed someone because of their irresponsibility. The driver obviously,
is not the only person affected by drunk driving. When a drunk driver kills someone the family
and friends of the victim are affected.
Drunk Driving is becoming a major concern in our society today. Drunk driving is not a funny
thing. It has killed many people and ruined the lives of many others.
So we came with a new idea to avoid these problems by developing a system which is located in
the vehicle which detects the alcoholics by breath and switch of the ignition system of the
vehicle.
Only one in every 20 road accidents is caused by the driver breaking the speed limit, the
Government has admitted.
Critics said the research, based on official police reports, destroyed the case for speed cameras.
It came amid a separate row over the accuracy of the Government's figures for the number of
people being injured or killed on the roads, which showed a three per cent fall last year.
Humans tend to blame somebody or something else when a mistake or accident occurs. A recent
European study concluded that 80% of drivers involved in motor vehicle accidents believed that
the other party could have done something to prevent the accident. A miniscule 5% admitted that
they were the only one at fault. Surveys consistently reveal that the majority consider themselves
more skillful and safer than the average driver. Some mistakes occur when a driver becomes
distracted, perhaps by a cell phone call or a spilled cup of coffee. Very few accidents result from
an 'Act of God,' like a tree falling on a vehicle.
Speed Kills - The faster the speed of a vehicle, the greater the risk of an accident. The forces
experienced by the human body in a collision increase exponentially as the speed increases.
Smart Motorist recommends that drivers observe our 3 second rule in everyday traffic, no matter
what your speed. Most people agree that going 100 mph is foolhardy and will lead to disaster.
The problem is that exceeding the speed limit by only 5 mph in the wrong place can be just as
dangerous. Traffic engineers and local governments have determined the maximum speeds
allowable for safe travel on the nation's roadways. Speeding is a deliberate and calculated
behavior where the driver knows the risk but ignores the danger. Fully 90% of all licensed
drivers speed at some point in their driving career; 75% admit to committing this offense
regularly.
Consider this example: a pedestrian walks out in front of a car. If the car is traveling at just 30
mph, and the driver brakes when the pedestrian is 45 feet away, there will be enough space in
which to stop without hitting the pedestrian. Increase the vehicle speed by just 5 mph and the
situation changes dramatically. At 35 mph, with the pedestrian 45 feet away and the driver
braking at the same point, the car will be traveling at 18 mph when it hits the pedestrian. An
impact at 18 mph can seriously injure or even kill the pedestrian.
Who are the bad drivers? They are young, middle-aged, and old; men and women; they drive
luxury cars, sports cars, SUVs and family cars. Almost every qualified driver I know admits to
some type of risky driving behavior, most commonly speeding.
Aggressive Drivers - As we've described, modern cars are manufactured to very safe standards,
and the environment they're driven in is engineered to minimize the injuries suffered during an
accident. The most difficult area to change is aggressive driver behavior and selfish attitudes. A
1995 study by the Automobile Association in Great Britain found that 88% of the respondents
reported at least one of the behaviors listed below directed at them (in order of descending
frequency):
Aggressive tailgating
Lights flashed at them because the other motorist was annoyed
Aggressive or rude gestures
Deliberate obstruction -- preventing them from moving their vehicle
Verbal abuse
Physical assault
The same group was then asked about aggressive behavior they had displayed towards other
drivers. 40% indicated that they had never behaved aggressively towards another driver. A
further 60% of the survey respondents admitted to one or more of the following behaviors (listed
in order of descending frequency):
Flashed lights at another motorist because they were annoyed with them
Gave aggressive or rude gestures
Gave verbal abuse
Aggressively tailgated another motorist
Deliberately obstructed or prevented another from moving their vehicle
Physically assaulted another motorist (one positive response)
These behaviors are probably under-reported, since most people are not willing to admit to the
more serious actions, even if no penalty exists. The majority of these incidents happened during
the daylight hours (70%), on a main road (not freeway or divided highway).
BLOCK DIAGRAM
LPC 2129 ARMMICROCONTROLLER
ALCOHOL BREATH ANALYZER
IGNITION CUT
OFF
OP-AMP
LPG/CNG
SENSORACCELERATION/
DE-ACCELERATION
LCD 16X2
BLOCK DIAGRAM DESCRIPTION:
This system consists of 8-bit microcontroller which acts as a heart of the system, which will be
monitoring the sensor continuously and sends the information to the hardware which will switch
of the ignition system of the vehicle. Alcohol detection is a tin dioxide semiconductor gas sensor
which has a high sensitivity to alcohol with quick response speed. this model is suitable for
alcohol detection such as portable breath alcohol checker or ignition locking system in
automobiles Ignition cut off system is a solid state electro mechanical relay which is connected
to microcontroller and ignition unit when microcontroller provides the information this will turn
on or off depending on the condition
Ideal sensor for use to detect the presence of a dangerous LPG leak in your storage tank. This
unit can be easily incorporated into an alarm unit, to sound an alarm or give a visual indication of
the LPG concentration. The sensor has excellent sensitivity combined with a quick response
time. The sensor can also sense iso-butane, propane, LNG and smoke.
CIRCUIT DIAGRAM
ARM7TDMI
3.1 ADVANCED RISC MACHINE
• T - Thumb architecture extension(16)
• D - Core has debug extensions
• M - Enhanced multiplier
• I - Embedded ICE macro cell
• S - Fully Synthesizable
3.2 FEATURES OF ARM7
• CPU at the heart of LPC2000 family is an ARM7.
• ARM7 is a RISC computer with a small instruction set and consequently with a small
gate count.
• It had high performance
• Low power consumption.
• It takes small amount of Silicon die area.
• Heart of ARM7 CPU is the instruction pipeline.
3.3 INTRODUCTION
The ARM7TDMI is a member of the Advanced RISC Machines (ARM) family of general
purpose 32-bit microprocessors, which offer high performance for very low power consumption
and price. The ARM architecture is based on Reduced Instruction Set Computer (RISC)
principles, and the instruction set and related decode mechanism are much simpler than those of
micro programmed Complex Instruction Set Computers. This simplicity results in a high
instruction throughput and impressive real-time interrupt response from a small and cost-
effective chip.
Pipelining is employed so that all parts of the processing and memory systems can operate
continuously. Typically, while one instruction is being executed, its successor is being decoded,
and a third instruction is being fetched from memory. The ARM memory interface has been
designed to allow the performance potential to be realized without incurring high costs in the
memory system. Speed-critical control signals are pipelined to allow system control functions to
be implemented in standard low-power logic, and these control signals facilitate the exploitation
of the fast local access modes offered by industry standard dynamic RAMs.
3.4 ARM ARCHITECTURE
The ARM7TDMI processor employs a unique architectural strategy known as THUMB, which
makes it ideally suited to high-volume applications with memory restrictions, or applications
where code density is an issue.
3.4.1 Thumb Concept
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM7TDMI processor has two instruction sets:
• The standard 32-bit ARM set
• A 16-bit THUMB set
The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard
ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit
processor using 16-bit registers. This is possible because THUMB code operates on the same 32-
bit register set as ARM code.
The major advantage of a 32-bit (ARM) architecture over a 16-bit architecture is its ability to
manipulate 32-bit integers with single instructions, and to address a large address space
efficiently. When processing 32-bit data, a 16-bit architecture will take at least two instructions
to perform the same task as a single ARM instruction.
THUMB also has a major advantage over other 32-bit architectures with 16-bit instructions. This
is the ability to switch back to full ARM code and execute at full speed. Thus critical loops for
applications such as
• Fast interrupts
• DSP algorithms
Can be coded using the full ARM instruction set, and linked with THUMB code.
Various portions of a system can be optimized for speed or for code density by switching
between THUMB and ARM execution as appropriate.
3.5 ARM7 FUNCTIONAL DIAGRAM
Fig 3.1 Functional block diagram of ARM7
3.6 SIGNAL DESCRIPTION
3.6.1 Transistor sizes
For a 0.6 m ARM7TDMI:
INV4 driver has transistor sizes of
p = 22.32 m/0.6 m
N = 12.6 m/0.6 m
INV8 driver has transistor sizes of
p = 44.64 m/0.6 m
N = 25.2 m/0.6 m
3.6.2 Key to signal types
IC Input CMOS thresholds
P Power
O4 Output with INV4 driver
O8 Output with INV8 driver
3.7 PROGRAMMER’S MODEL PROCESSOR OPERATING STATES
From the programmer’s point of view, the ARM7TDMI can be in one of two states:
ARM state which executes 32-bit, word-aligned ARM instructions.
THUMB state which operates with 16-bit, half word-aligned THUMB instructions. In
this state, the PC uses bit 1 to select between alternate half words.
Note Transition between these two states does not affect the processor mode or the contents of
the registers.
3.7.1 Switching State
Entering THUMB state:
Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0)
set in the operand register. Transition to THUMB state will also occur automatically on return
from an exception (IRQ, FIQ, UNDEF, ABORT, SWI etc.), if the exception was entered with the
processor in THUMB state.
Entering ARM state:
Entry into ARM state happens:
1. On execution of the BX instruction with the state bit clear in the operand register.
2. On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.).
In this case, the PC is placed in the exception mode’s link register, and execution commences at
the exception’s vector address.
3.8 MEMORY FORMATS
ARM7TDMI views memory as a linear collection of bytes numbered upwards from zero. Bytes
0 to 3 hold the first stored word, bytes 4 to 7 the second and so on. ARM7TDMI can treat words
in memory as being stored either in Big Endian or Little Endian format.
3.8.1 Big Endian Format
In Big Endian format, the most significant byte of a word is stored at the lowest numbered byte
and the least significant byte at the highest numbered byte. Byte 0 of the memory system is
therefore connected to data lines 31 through 24.
Fig 3.2 Big Endian Format
3.8.2 Little Endian Format
In Little Endian format, the lowest numbered byte in a word is considered the word’s least
significant byte, and the highest numbered byte the most significant. Byte 0 of the memory
system is therefore connected to data lines 7 through 0.
Fig 3.3 Little Endian Format
3.8.3 Instruction Length
Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).
3.8.4 Data Types
ARM7TDMI supports byte (8-bit), half word (16-bit) and word (32-bit) data types. Words must
be aligned to four-byte boundaries and half words to two-byte boundaries.
3.8.5 Operating Modes
ARM7TDMI supports seven modes of operation:
User (usr): The normal ARM program execution state
FIQ (fiq): Designed to support a data transfer or channel process
IRQ (irq): Used for general-purpose interrupt handling
Supervisor (svc): Protected mode for the operating system
Abort mode (abt): Entered after a data or instruction prefetch abort
System (sys): A privileged user mode for the operating system
Undefined (und): Entered when an undefined instruction is executed
Mode changes may be made under software control, or may be brought about by external
interrupts or exception processing. Most application programs will execute in User mode. The
non-user modes - known as privileged modes - are entered in order to service interrupts or
exceptions, or to access protected resources.
3.9 REGISTERS
ARM7TDMI has a total of 37 registers - 31 general-purpose 32-bit registers and six status
registers - but these cannot all be seen at once. The processor state and operating mode dictate
which registers are available to the programmer.
3.9.1 The Arm State Register Set
In ARM state, 16 general registers and one or two status registers are visible at any one time. In
privileged (non-User) modes, mode-specific banked registers are switched in. Register
organization in ARM state shows which registers are available in each mode: the banked
registers are marked with a shaded triangle. The ARM state register set contains 16 directly
accessible registers: R0 to R15. All of these except R15 are general-purpose, and may be used to
hold either data or address values. In addition to these, there is a seventeenth register used to
store status information
Register 14 is used as the subroutine link register. This receives a copy of R15 when a Branch
and Link (BL) instruction is executed. At all other times it may be treated as a
general-purpose register. The corresponding banked registers R14_svc, R14_irq,
R14_fiq, R14_abt and R14_und are similarly used to hold the return values of
R15 when interrupts and exceptions arise, or when Branch and Link instructions
are executed within interrupt or exception routines.
Register 15 holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are zero and bits
[31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain the
PC.
Register 16 is the CPSR (Current Program Status Register). This contains condition code flags
and the current mode bits. FIQ mode has seven banked registers mapped to R8-14
(R8_fiq-R14_fiq). In ARM state, many FIQ handlers do not need to save any
registers. User, IRQ, Supervisor, Abort and Undefined each have two banked
registers mapped to R13 and R14, allowing each of these modes to have a private
stack pointer and link registers.
3.9.2 The Thumb State Register Set
The THUMB state register set is a subset of the ARM state set. The programme has direct access
to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register
(SP), a link register (LR), and the CPSR. There are banked Stack Pointers, Link Registers and
Saved Process Status Registers (SPSRs) for each privileged mode.
Fig 3.4 Thumb State Register Set
3.10 THE RELATIONSHIP BETWEEN ARM AND THUMB STATE REGISTERS
The THUMB state registers relate to the ARM state registers in the following way:
THUMB state R0-R7 and ARM state R0-R7 are identical
THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical
THUMB state SP maps onto ARM state R13
THUMB state LR maps onto ARM state R14
The THUMB state Program Counter maps onto the ARM state Program Counter (R15).
Fig 3.5
Mapping of THUMB state registers onto ARM state registers.
3.10.1 Accessing Hi Registers In Thumb State
In THUMB state, registers R8-R15 (the Hi registers) are not part of the standard register set.
However, the assembly language programmer has limited access to them, and can use them for
fast temporary storage. A value may be transferred from a register in the range R0-R7 (a Lo
register) to a Hi register and from a Hi register to a Low register, using special variants of the
MOV instruction. Hi register values can also be compared against or added to Lo register values
with the CMP and ADD instructions.
3.10.2 The Program Status Registers
The ARM7TDMI contains a Current Program Status Register (CPSR), plus five Saved Program
Status Registers (SPSRs) for use by exception handlers. These registers
hold information about the most recently performed ALU operation
control the enabling and disabling of interrupts
set the processor operating mode.
3.10.3 Program Status Register Format
Fig 3.6 Program Status Register Format
3.10.4 The Condition Code Flags
The N, Z, C and V bits are the condition code flags. These may be changed as a result of
arithmetic and logical operations, and may be tested to determine whether an instruction should
be executed.
3.10.5 The Control Bits
The bottom 8 bits of a PSR (incorporating I, F, T and M[4:0]) are known collectively as the
control bits. These will change when an exception arises. If the processor is operating in a
privileged mode, they can also be manipulated by software. The T bit This reflects the operating
state. When this bit is set, the processor is executing in THUMB state, otherwise it is executing
in ARM state. This is reflected on the TBIT external signal. Note that the software must never
change the state of the TBIT in the CPSR. If this happens, the processor will enter an
unpredictable state.
Interrupt disable bits the I and F bits are the interrupt disable bits. When set, these disable the
IRQ and FIQ interrupts respectively. The mode bits The M4, M3, M2, M1 and M0 bits (M[4:0])
are the mode bits. Not all combinations of the mode bits define a valid processor mode. Only
those explicitly described shall be used. The user should be aware that if any illegal value is
programmed into the mode bits, M[4:0], then the processor will enter an unrecoverable state. If
this occurs, reset should be applied.
Table 3.1: For control bits
Reserved bits the remaining bits in the PSRs are reserved. When changing a PSR’s flag or
control bits, you must ensure that these unused bits are not altered. Also, your program should
not rely on them containing specific values, since in future processors they may read as one or
zero.
CHAPTER 4
LPC2129
4.1 GENERAL DESCRIPTION
The LPC2119/2129/2194/2292/2294 are based on a 16/32 bit ARM7TDMI-STM CPU with real-
time emulation and embedded trace support, together with 128/256 kilobytes (kB) of embedded
high speed flash memory. A 128-bit wide internal memory interface and unique accelerator
architecture enable 32-bit code execution at maximum clock rate. For critical code size
applications, the alternative 16-bit Thumb Mode reduces code by more than 30% with minimal
performance penalty. With their compact 64 and 144 pin packages, low power consumption,
various 32-bit timers, combination of 4-channel 10-bit ADC and 2/4 advanced CAN channels or
8-channel 10-bit ADC and 2/4 advanced CAN channels (64 and 144 pin packages respectively),
and up to 9 external interrupt pins these microcontrollers are particularly suitable for industrial
control, medical systems, access control and point-of-sale.
Number of available GPIOs goes up to 46 in 64 pin package. In 144 pin packages number of
available GPIOs tops 76 (with external memory in use) through 112 (single-chip application).
Being equipped wide range of serial communications interfaces, they are also very well suited
for communication gateways, protocol converters and embedded soft modems as well as many
other general-purpose applications.
4.2 FEATURES
• 16/32-bit ARM7TDMI-S microcontroller in a 64 or 144 pin package.
• 16 KB on-chip Static RAM
• 128/256 KB on-chip Flash Program Memory (at least 10,000 erate/write cycles over the whole
temperature range). 128-bit wide
Interface/accelerator enables high speed 60 MHz operation.
• External 8, 16 or 32-bit bus (144 pin packages only)
• In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot-loader
software. Flash programming takes 1 ms per 512 byte line. Single sector or full chip erase takes
400 ms.
• Embedded ICE-RT interface enables breakpoints and watch points. Interrupt service routines
can continue to execute whilst
the foreground task is debugged with the on-chip Real Monitor software.
• Embedded Trace Macrocell enables non-intrusive high speed real-time tracing of instruction
execution.
• Two/four interconnected CAN interfaces with advanced acceptance filters.
• Four/eight channel (64/144 pin package) 10-bit A/D converter with conversion time as low as
2.44 ms.
• Two 32-bit timers (with 4 capture and 4 compare channels), PWM unit (6 outputs), Real Time
Clock and Watchdog.
• Multiple serial interfaces including two UARTs (16C550), Fast I2C (400 kbits/s) and two
SPIs™.
• 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked Loop.
• Vectored Interrupt Controller with configurable priorities and vector addresses.
• Up to forty-six (64 pin) and hundred-twelve (144 pin package) 5 V tolerant general purpose I/O
pins. Up to 12 independent external interrupt pins available (EIN and CAP functions).
• On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
• Two low power modes Idle and Power-down.
• Processor wake-up from Power-down mode via external interrupt.
• Individual enable/disable of peripheral functions for power optimization.
• Dual power supply.
- CPU operating voltage range of 1.65V to 1.95V (1.8V +/- 8.3%).
- I/O power supply range of 3.0V to 3.6V (3.3V +/- 10%).
4.3 APPLICATIONS
• Industrial control
• Medical systems
• Access control
• Point-of-sale
• Communication gateway
• Embedded soft modem
• General purpose applications
4.4 DEVICE INFORMATION
Table 4.1: LPC2119/2129/2194/2292/2294 device information
4.5 BLOCK DIAGRAM
Fig 4.1 Block diagram of LPC2129
4.6 ARCHITECTURAL OVERVIEW
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance
and very low power consumption. The ARM® architecture is based on Reduced Instruction Set
Computer (RISC) principles, and the instruction set and related decode mechanism are much
simpler than those of micro programmed Complex Instruction Set Computers. This simplicity
results in a high instruction throughput and impressive real-time interrupt response from a small
and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems can
operate continuously. Typically, while one instruction is being executed, its successor is being
decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb,
which makes it ideally suited to high-volume applications with memory restrictions, or
applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM set.
• A 16-bit Thumb set.
The Thumb set’s 16-bit instruction length allows it to approach twice the density of standard
ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit
processor using 16-bit registers. This is possible because Thumb code operates on the same 32-
bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of
ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit
memory system.
4.6.1 On-Chip Flash Memory System
The LPC2119/LPC2129 incorporates a 128 kB and 256 kB Flash memory system respectively.
This memory may be used for both code and data storage. Programming of the Flash memory
may be accomplished in several ways. It may be programmed In System via the serial port. The
application program may also erase and/or program the Flash while the application is running,
allowing a great degree of flexibility for data storage field firmware upgrades, etc. When on-chip
boot loader is used, 120/248 kB of Flash memory is available for user code.
The LPC2119/LPC2129 Flash memory provides a minimum of 100,000 erase/write cycles and
20 years of data retention. On-chip boot loader (as of revision 1.60) provides Code Read
Protection (CRP) for the LPC2119/LPC2129 on-chip Flash memory. When the CRP is enabled,
the JTAG debug port and ISP commands accessing either the on-chip RAM or Flash memory are
disabled. However, the ISP Flash Erase command can be executed at any time (no matter
whether the CRP is on or off). Removal of CRP is achieved by erasure of full on-chip user Flash.
With the CRP off, full access to the chip via the JTAG and/or ISP is restored.
4.6.2 On-Chip Static Ram
The LPC2119/2129/2194/2292/2294 provides a 16 kB static RAM memory that may be used for
code and/or data storage. The SRAM supports 8-bit, 16-bit, and 32-bit accesses.
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during
back-to-back writes. The write-back buffer always holds the last data sent by software to the
SRAM. This data is only written to the SRAM when another write is requested by software (the
data is only written to the SRAM when software does another write). If a chip reset occurs,
actual SRAM contents will not reflect the most recent write request
(i.e. after a "warm" chip reset, the SRAM does not reflect the last write operation). Any software
that checks SRAM contents after reset must take this into account. Two identical writes to a
location guarantee that the data will be present after a Reset. Alternatively, a dummy write
operation before entering idle or power-down mode will similarly guarantee that the last data
written will be present in SRAM after a subsequent Reset.
4.6.3 System Control
The oscillator supports crystals in the range of 1 MHz to 30 MHz. The oscillator output
frequency is called fosc and the ARM processor clock frequency is referred to as cclk for
purposes of rate equations, etc. fosc and cclk are the same value unless the PLL is running and
connected.
4.6.4 Crystal Oscillator
While an input signal of 50-50 duty cycle within a frequency range from 1 MHz to 50 MHz can
be used by LPC2119/2129/2194/2292/2294 if supplied to its input XTAL1 pin, this
microcontroller’s onboard oscillator circuit supports external crystals in the range of 1 MHz to
30 MHz only. If on-chip PLL system or boot-loader is used, input clock frequency is limited to
exclusive range of 10 MHz to 25 MHz. The oscillator output frequency is called Fosc and the
ARM processor clock frequency is referred to as cclk for purposes of rate equations, etc.
elsewhere in this document. Fosc and cclk are the same value unless the PLL is running and
connected. Refer to the PLL description in this chapter for details and frequency limitations.
Onboard oscillator in LPC2119/2129/2194/2292/2294 can operate in one of two modes: slave
mode and oscillation mode. In slave mode the input clock signal should be coupled by means of
a capacitor of 100 pF (Cc in Figure , drawing a), with an
Amplitude of at least 200 mVrms. X2 pin in this configuration can be left not connected. If slave
mode is selected, Fosc signal of 50-50 duty cycle can range from 1 MHz to 50 MHz.
External components and models used in oscillation mode are shown in Figure, drawings b and
c. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1
and CX2 need to be connected externally in case of fundamental mode oscillation (the
fundamental frequency is represented by L, CL and RS). Capacitance Cp in Figure, drawing c,
represents the parallel package capacitance and should not be larger than 7 pF. Parameters FC,
CL, RS and CP are supplied by the crystal manufacturer. Choosing an oscillation mode as an on-
board oscillator mode of operation limits Fosc clock selection to 1 MHz to 30 MHz.
Fig 4.2
Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation)
external crystal model used for CX1/X2 evaluation
4.6.5 PLL (Phase Locked Loop)
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz The input
frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier
value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit
of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional
divider in the loop to keep the CCO within its frequency range while the PLL is providing the
desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the
output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a
50 % duty cycle. The PLL is turned off and bypassed following a chip Reset and may be enabled
by software. The program must configure and activate the PLL, wait for the PLL to Lock, then
connect to the PLL as a clock source. The PLL settling time is 100 ms.
Fig 4.3 PLL Block Diagram
4.6.7 Reset and Wakeup Timer
Reset has two sources on the LPC2119/LPC2129: the RESET pin and Watchdog Reset. The
RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip Reset
by any source starts the Wake-up Timer (see Wake-up Timer description below), causing the
internal chip reset to remain asserted until the external Reset is de-asserted, the oscillator is
running, a fixed number of clocks have passed, and the on-chip Flash controller has completed
its initialization. When the internal Reset is removed, the processor begins executing at address
0, which is the Reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This is
important at power on, all types of Reset, and whenever any of the aforementioned functions are
turned off for any reason. Since the oscillator and other functions are turned off during Power-
down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up
Timer. The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event
Caused the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on many
factors, including the rate of VDD ramp (in the case of power on), the type of crystal and its
electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g.
capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.
4.6.8 External Interrupt Inputs
The LPC2119/LPC2129 include up to nine edge or level sensitive External Interrupt Inputs as
selectable pin functions. When the pins are combined, external events can be processed as four
independent interrupt signals. The External Interrupt Inputs can optionally be used to wake up
the processor from Power-down mode.
4.6.8 Memory Mapping Control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning
at address 0x00000000. Vectors may be mapped to the bottom of the on-chip Flash memory, or
to the on-chip static RAM. This allows code running in different memory spaces to have control
of the interrupts.
4.6.9 Power Control
The LPC2119/LPC2129 support two reduced power modes: Idle mode and Power-down mode.
In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs.
Peripheral functions continue operation during Idle mode and may generate interrupts to cause
the processor to resume execution. Idle mode eliminates power used by the processor itself,
memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The
processor state and registers, peripheral registers, and internal SRAM values are preserved
throughout Power-down mode and the logic levels of chip output pins remain static. The Power-
down mode can be terminated and normal operation resumed by either a Reset or certain specific
interrupts that are able to function without clocks. Since all dynamic operation of the chip is
suspended, Power-down mode reduces chip power consumption to nearly zero.
A Power Control for Peripherals feature allows individual peripherals to be turned off if they are
not needed in the application, resulting in additional power savings.
4.6.10 VPB bus
The VPB divider determines the relationship between the processor clock (CCLK) and the clock
used by peripheral devices (PCLK). The VPB divider serves two purposes. The first is to provide
peripherals with the desired PCLK via VPB bus so that they can operate at the speed chosen for
the ARM processor. In order to achieve this, the VPB bus may be slowed down to 1¤2 to 1¤4 of
the processor clock rate. Because the VPB bus must work properly at power-up (and its timing
cannot be altered if it does not work since the VPB divider control registers reside on the VPB
bus), the default condition at reset is for the VPB bus to run at 1¤4 of the processor clock rate.
The second purpose of the VPB divider is to allow power savings when an application does not
require any peripherals to run at the full processor rate. Because the VPB divider is connected to
the PLL output, the PLL remains active (if it was running) during Idle mode.
4.6.11 Emulation and Debugging
The LPC2119/LPC2129 support emulation and debugging via a JTAG serial port. A trace port
allows tracing program execution. Debugging and trace functions are multiplexed only with
GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on
Port 0 are available during the development and debugging phase as they are when the
application is run in the embedded system itself.
4.6.12 Embedded ICE
Standard ARM Embedded ICE® logic provides on-chip debug support. The debugging of the
target system requires a host computer running the debugger software and an Embedded ICE