New Design and Development of On board Computer of Micro LEO … · 2017. 12. 6. · PNSS-1 falls into the category of Micro Low earth orbit satellites, the satellite comprises of

Design and Development of On board

Computer of Micro LEO Satellite

Submitted by:

M. Azeem Awan 2013-EE-111

Umair Ahmed 2013-EE-113

M. Huzaifa Bashir 2013-EE-125

M. Nabeel Tahir 2013-EE-139

Supervised by: Prof. Dr Muhammad Tahir

Department of Electrical Engineering

University of Engineering and Technology Lahore

Design and Development of On board

Computer of Micro LEO Satellite

Submitted to the faculty of the Electrical Engineering Department

of the University of Engineering and Technology Lahore

in partial fulfillment of the ments for the Degree of

Bachelor of Science

in

Electrical Engineering.

Internal Examiner External Examiner

DirectorUndergraduate Studies

Department of Electrical Engineering

University of Engineering and Technology Lahore

i

Declaration

I declare that the work contained in this thesis is my own, except where explicitly stated

otherwise. In addition this work has not been submitted to obtain another degree or

professional qualification.

Signed:

Date:

ii

Acknowledgments

Indeed Allah is the most merciful and benevolent who gave us the courage to surpass the

arduous yet fruitful journey of our undergraduate studies at Department of Electrical

Engineering, UET Lahore. To the enormous support and blessings of our parents which

kept us still during the challenging times. In the end we are most thankful to SUPARCO

officials as they awarded us the opportunity of working on a project as prestigious as

this and our project adviser, Dr M. Tahir for his support throughout the last one and a

half year.

iii

Dedicated to the Creator of both worlds and our respectivefamilies. . .

iv

Contents

Acknowledgments iii

List of Figures viii

List of Tables x

Abbreviations xi

Abstract xii

1 Introduction 1

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Structure of the Satellite . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Structure of ACS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.4 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.5 Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Design of Onboard Computer 5

2.1 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.4 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.5 External Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.5.1 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.5.2 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.5.3 FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.5.4 EDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.6 Sensors and Actuators Interfacing . . . . . . . . . . . . . . . . . . . . . . . 10

2.6.1 RS422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.6.1.1 AM26LV31I/AM26LV32I . . . . . . . . . . . . . . . . . . 11

2.6.1.2 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.6.2 RS485 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.6.3 Magnetometer Interfacing . . . . . . . . . . . . . . . . . . . . . . . 13

2.6.4 Sun Sensors Interfacing . . . . . . . . . . . . . . . . . . . . . . . . 14

2.7 CAN Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.7.1 TJA1055/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.7.2 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.8 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

v

vi

3 PCB Design 17

3.1 Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.1 Dimensionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.2 Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.3 Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2 Layered Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.1 Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.2 Thermal Ground Planes . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2.3 Routing Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 Space Compatible Design 20

4.1 Power Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.1 Ultra-Low Power Components . . . . . . . . . . . . . . . . . . . . 20

4.1.2 Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2.1 EMI Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2.2 Latch Up Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3 Fault Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3.1 Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3.1.1 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . 23

4.3.2 Fault Tolerant Module . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Implementation of the Onboard Computer 28

5.1 PCB Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.2 Simulation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2.1.1 Solar Tracking . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2.1.2 Telemetry and Tele-command . . . . . . . . . . . . . . . 29

5.2.2 Internal Structure of Simulation Platform . . . . . . . . . . . . . . 29

5.3 Graphical User Interface for Telemetry and Tele-command . . . . . . . . . 30

5.4 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6 Results 33

6.1 SUPARCO Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.1.1 Requirements Compliance . . . . . . . . . . . . . . . . . . . . . . . 34

6.2 Prototype Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7 Conclusions 36

7.1 Budget Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.2 Timeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

A Latchup Protection 39

B Schematics 41

B.1 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

B.2 EDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

B.3 RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

vii

B.4 CAN Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

B.5 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

B.6 Power and EMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

B.7 Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

B.8 Reset and Fault Tolerant Module . . . . . . . . . . . . . . . . . . . . . . . 45

References 46

List of Figures

1.1 PNSS-1 System Architecture [10] . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Block Diagram of Attitude Control Subsystem of PNSS-1 [10] . . . . . . . 3

2.1 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Interface of RTC with Microcontroller . . . . . . . . . . . . . . . . . . . . 6

2.3 JTAG header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4 Connection Scheme for Memories . . . . . . . . . . . . . . . . . . . . . . . 8

2.5 Block Diagram of EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.6 Block Diagram of SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.7 Block Diagram of FLASH. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.8 Interfaces of OBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.9 RS422 Driver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.10 RS422 Reciever Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 12

2.11 Reaction Wheels interfacing with OBC . . . . . . . . . . . . . . . . . . . . 12

2.12 SN65HVD1780 RS485 Transceiver . . . . . . . . . . . . . . . . . . . . . . 13

2.13 Magnetometer interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.14 Sun Sensors Interfacing Scheme. . . . . . . . . . . . . . . . . . . . . . . . 14

2.15 Block Diagram of CAN Bus . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.16 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 Layering Scheme of PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1 5V to 3.3V regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2 LT1086: 5V to 3.3V linear regulator . . . . . . . . . . . . . . . . . . . . . 21

4.3 Circuit Diagram for EMI Filter . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4 Latch Up Protection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.5 Block Diagram for Watchdog Timer . . . . . . . . . . . . . . . . . . . . . 23

4.6 MAX6370 Internal Structure . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.7 Flow Chart of Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.8 Flow Chart of Switching To Redundant OBC . . . . . . . . . . . . . . . . 26

4.9 Reset and FTM Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.10 Reset and Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1 3D Layout of PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.2 Solar Tracking mode of Operation . . . . . . . . . . . . . . . . . . . . . . 29

5.3 Telemetry and Telecommand mode of Operation . . . . . . . . . . . . . . 30

5.4 Internal and External Structures of the Simulation Platform . . . . . . . . 30

5.5 Bluetooth module connected to PC via UART to USB converter . . . . . 31

5.6 GUI developed for Telemetry and Tele-command . . . . . . . . . . . . . . 31

viii

List of Figures ix

6.1 Breakdown of Requirements enforced by SUPARCO . . . . . . . . . . . . 34

6.2 Requirements Compliance Pie Chart . . . . . . . . . . . . . . . . . . . . . 35

7.1 Project Timeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

A.1 Parasitic transistors in a CMOS circuit . . . . . . . . . . . . . . . . . . . . 39

B.1 Schematics of SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

B.2 Error detection and Correction module . . . . . . . . . . . . . . . . . . . . 42

B.3 RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

B.4 CAN Transceiver and Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

B.5 Schematics of Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . 43

B.6 Power and EMI Filtration Circuit . . . . . . . . . . . . . . . . . . . . . . . 44

B.7 Quadruple Differential Line Receiver . . . . . . . . . . . . . . . . . . . . . 44

B.8 Reset and FTM Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

List of Tables

2.1 Pins Description RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Pins Description of SN65HVD1780 Transceiver . . . . . . . . . . . . . . . 12

7.1 Detailed breakdown of cost of OBC . . . . . . . . . . . . . . . . . . . . . . 37

x

Abbreviations

DHU Data Handling Unit

OBC On Board Computer

GPS Global Positioning System

CAN Controller Area Network

I2C Inter Integrated Circuit

PWM Pulse Width Modulation

URD Unit Requirement Document

EMI Electro Magnetic Interference

NASA National Aeronautics and Space Administration

ISRO Indian Space Rresearch Organization

IC Integrated Circuit

UART Univeral Asynchronous Reciever Transmitter

ADC Analog to Digital Converter

MGM Magnetometer

FTM Fault Tolerant Module

PDU Power Distribution Unit

EMF Electro Motive Force

PCB Printed Circuit Board

RTC Real Time Clock

EEPROM Electrically Erasable Programmable Readonly Memory

SRAM Static Random Access Memory

EDAC Error Detection And Correction

FMC Flexible Memory Controller

xi

Abstract

This thesis elaborates the design and implementation of the onboard computer (OBC) of

a Micro LEO satellite which is to be installed as part of the Attitude Control Subsystem

(ACS) of PNSS-1 (Pakistan National Student Satellite). PNSS-1 is a joint collaboration

of SUPARCO with academia, initiated in 2014 to design and fabricate the first ever stu-

dent made satellite of Pakistan and is envisioned to be launched in Space in 2018. The

satellite falls into the category of Micro Low Earth Orbit Satellites weighing a total of

50 Kg and carrying an experimental payload into the space. Our project deals only with

the onboard computer of the satellite which is considered to be the brain of the Satel-

lite. The OBC units primary function is the attitude control, fault detection isolation

and recovery (FDIR) and health telemetry of the Attitude Control Subsystem (ACS).

In this document, we discuss the complete hardware design of the OBC, selection of

components keeping in view the compatibility with the stringent space conditions such

as extended temperature range, redundancy and power budget minimization. We also

propose the schematic design of the various sub-modules of the OBC and their intercon-

nections. Furthermore the budget analysis of the selected components is performed and

their conformity with the design requirements of SUPARCO is verified. In the end we

also provide the details of the hardware and software testbed designed to simulate the

behavior of onboard computer as installed in the satellite. The designed hardware for

the onboard computer has been fabricated after detailed verifications from SUPARCO

officials. Our project is the first of its kind promising a linkage between the industry and

academia of Pakistan from which the future generation of engineers can seek inspiration.

Chapter 1

Introduction

1.1 Motivation

In the era of lightning fast advancements, the success of a nation is predicated upon its

ability to stand and survive at the cutting edge of technology. The area of space tech-

nology is one such whose importance towards the development of any country cannot

be ignored in the current age. Pakistan being a developing country has a very nascent

Space Program when compared to the neighboring countries such as China and India.

Foreign space agencies and companies such as NASA, SpaceX and ISRO have set new

standards through successful interplanetary missions. These satellites have been em-

ployed in numerous applications ranging from earth observation to other business [6] In

order to ensure our survival in the space industry, the need of the hour is to promote

radical advancements in the local space industry of Pakistan.

The SUPARCO, Pakistan’s premier institution focused towards the development of Pak-

istan’s space program has recently initiated the goal of advancing the indigenous space

industry. Pakistan National Student Satellite Project (PNSS-1) is one such project

which plans to bridge the gap between the academia and space industry to keep the

future generation of engineers abreast with the research and development in modern

space technologies. The project aims to instill in students, the knowledge and the ex-

posure necessary to set foot in the field of Space and Upper Atmosphere research and

development.

Our prime motive of opting this project was to get ourselves familiar with the current de-

velopment threads in the space industry and apply the skills and concepts learnt during

our undergraduate education for our very own space agency. We have worked tirelessly

over the past one and a half year to meet the challenges set by the SUPARCO and are

hopeful that the successful launch of our designed satellite will have a pivotal impact in

inspiring the future students to show interest in the Space sector.

1

Chapter 2. Introduction 2

1.2 Structure of the Satellite

PNSS-1 falls into the category of Micro Low earth orbit satellites, the satellite comprises

of different peripherals and subunits interconnected to perform the overall functioning

of the satellite. The figure 2.1 shows the various modules of PNSS-1 and their intercon-

nections. The satellite is divided into the following subunits:

• EPS (Electrical Power Subsystem)• ACS (Attitude Control System)• CDHS (Command and Data Handling Subsystem)• TCS (Thermal Control Subsystem)• TTCS (Telemetry and Tele command System)

Figure 1.1: PNSS-1 System Architecture [10]

1.3 Structure of ACS

The ACS (Attitude Control Subsystem) is the pivotal subunit of the satellite responsible

for the complete attitude control of the satellite. The ACS being the primary unit of

the satellite involves a complex and detailed design [1] The OBC in turn is the central

components of the OBC responsible for the following functions:

1. Sensor Data Acquisition:

The OBC using RS-422, interfaces with different sensors of the satellite such as Sun

Sensors, Magnetometer, Earth Sensor and GPS. It is responsible for the periodic

acquisition of the data from these sensors.

2. Data Processing:

The data as collected from these sensors is then processed by the OBC using


attitude control algorithms such as Kalman Filter and Linear Quadratic Regula-

tor. The OBC then determines the current attitude of the satellite and the most

suitable action.

3. Actuation:

Depending upon the attitude of the satellite, the OBC then instructs the different

actuators of the satellite such as Reaction Wheels and Magnetorquers to correct

the satellite position.

Figure 2.2 shows the internals of the Attitude Control Subsystem.

Figure 1.2: Block Diagram of Attitude Control Subsystem of PNSS-1 [10]

1.4 Problem Statement

The designed OBC must meet the following set of requirements to become an integral

part of PNSS-1. These requirements are enforced by the SUPARCO [10] and must be

satisfied by the designed OBC:

• Only Commercial off the shelf comments be incorporated into the design.• Total mass of the unit must be less than 2.3 kg and the mass of the electronics

must be less than 1.5 kg.

• Power consumption of the designed hardware must be less than 2 Watts.• The hardware must be EMC compatible.• Redundancy should be provided for each component and cross-strapping must be

ensured.

• No single point failure should occur at any point in the satellite failing the completemission.


• Supply voltages of 3.3V/5V and 12V must exist in the design.

Apart from this, following are the set of requirements that must be met by the simulation

platform of the satellite:

• Demonstrate the concept of Attitude control of the satellite.• Sun tracking should be demonstrated using Sun sensors made from Light Depen-

dent Resistors.

• Communication mechanism of the satellite with the base station should be demon-strated.

1.5 Challenges

The challenges met by the designed OBC are as follows:

• Resistant to spaces temperature range of -40 to 125 degrees centigrade.• Must be able to handle all single point failures and faults.• Resist other harsh space environments such as Micro-gravity.• Protection from radiations.• Availability and procurement of space grade components.

The simulation platform itself brought the following challenges along with its design:

• Proper tuning of the control algorithms according to the inertia of motors.• Proper placement of Sun sensors for the detection of the Sun.• Stable communication link between the platform and the base station(Desktop

PC)

Chapter 2

Design of Onboard Computer

2.1 Microcontroller

The microcontroller used in OBC design is STM32F27IIT6. It has ARM 32-bit Cortex

M4F based architecture. We are using LQFP176 pin package microprocessor. The

reason behind selection of this microcontroller is that it satisfies all the requirements

specified by suparco. The processor has following features.

• Maximum clock frequency is 180MHz.• Program memory size 2MB.• Data ram size 256kB.• Temperature range -40C to 85C.• Low power sleep, stop and standby modes• Internal 16MHz factory trimmed RC (with 1% error).• Internal 32KHz oscillator for RTC.• It has up to 21 communication interfaces.• Up to 3x IC interfaces• Up to 4 USARTs/4 UARTs• 2 x CAN

2.2 Oscillator

As required by SUPARCO, the use of discrete components was preferred to deal with

strange environment of space. As redundancy is very important, external clock crystals

are used. Although the processor has its internal oscillator, but UARTs require highly

accurate clock due to which external crystal is used.

The selected crystal is DSC1001CL008.00 which is a CMOS technology based crystal

oscillator and provides extraordinary noise immunity with wide range of voltage and

temperature. The output varies from 1MHz to 150MHz and operates between 1.7 to

3.3V.

The figure below shows the pinout diagram and connection scheme of oscillator.

5

Chapter 3. Design of Onboard Computer 6

Figure 2.1: Crystal Oscillator

2.3 Real Time Clock

The purpose of the RTC is to provide redundancy to the RTC inside the microprocessor

and is preferred to be external because of higher reliability. The DS17887-3IND+ is low

power extremely accurate real time clock. It has internally battery backup, 32.768KHz

crystal oscillator and 8KB of internal memory to keep track of time. Address and data is

transferred parallelly to microcontroller. This integrated circuit provides six mask able

interrupts and a programmable square wave output is available. It can operate either in

24-hour or 12-hour with AM/PM indicator and provides 1 minute per month accuracy

at 25◦C [4]. The interface of DS17887-3IND+ with microcontroller is shown in figure

below.

Figure 2.2: Interface of RTC with Microcontroller

The following table shows the description of pins of RTC interfaced with microcontroller.


Table 2.1: Pins Description RTC

PIN DESCRIPTION

AD0-AD7 Multiplexed bidirectional address/data bus. Direction can be controlled by software.

IRQ Active low interrupt input to microcontroller configured to set alarms.

CS This is active low chip select pin. This pin must be active for WR and RD operations

ALE This is active high input pin used to demultiplex address/data bus.

WR This pin is active low write enable.

RD This pin is active low read enable.

2.4 JTAG

STM32F427 provides two debugging interfaces. The debugging interface that is used in

OBC’s PCB design is JTAG. The reason behind using this interface is that STM32F427

provides internal pull up and pull down resistors which avoids floating condition at

JTAG Pins. Moreover, the JTAG header which is used to connect PCB to external

programmer also has pull up and pull down resistors which provide the redundancy to

internal pull up and pull down resistors. The resistors in series are also connected with

every outgoing connection to reduce the effect of electrical serge. The following picture

explains the implemented scheme for JTAG header.

Figure 2.3: JTAG header

2.5 External Memories

As per requirements by suparco OBC shall provide enough memory to store the critical

spacecraft telemetry data and data obtained from sensors. STM32F427 has built in

2MB flash and 256KB SRAM which fulfills suparco requirements. For the purpose of

redundancy and protection external EEPROM, SRAM and Flash memories are used in

design. The EEPROM is used for external booting and to store the code. External

SRAM is used for the execution of programs. At all times the data of EEPROM and

SRAM is stored in Flash memory to avoid memory failure in case of unit failure. Since

every integrated circuit is vulnerable to electrical signal noise in space environment so are


external memories. To ensure reliable data delivery between SRAM and microcontroller

external error detection and correction circuitry is used in unit design. It was unit

requirement by suparco that all memories should have 32bit data bus. Since memories

with 32bit data bus were not available in market so we have used two 16 bit memories

of each memory type in OBC’s design. Since STM32F427 operate at 3.3V but memories

operate at 5V so level translators are used between microcontroller and memories. The

picture below shows the design approach for connection circuitry of memories. The

components used in memories and error detection and correction circuitry are described

in the subsections below.

Figure 2.4: Connection Scheme for Memories

2.5.1 EEPROM

As per unit requirement document provided by suparco PROM should be used to store

code and external booting. Since PROM can only be programmed once so it cannot

be used in testing phase. So, we have selected that EEPROM whose pin compatible

PROM was available in market hence EEPROM will be replaced by PROM in final

flight model. The EEPROM that is used in OBC’s design is AT28C1024-25LC. The

pin compatible PROM that will be used in final flight model is AT27C1024-25LC. The

AT28C1024-25LC is high performance 1Mbit memory which operates at ultralow power.

It is accessed parallelly through 16bit address bus and 16bit data bus. It has chip enable

and output enable features. These features helped to reduce the power consumption by

EEPROM. The picture below shows the schematics of EEPROM.

2.5.2 SRAM

SRAM in OBC is used for execution of code. The SRAM that is used in OBC’s design

is LY62W25616. It is a 4Mbit low power CMOS static random access memory. It is

accessed parallelly through 16bit address bus and 16bit data bus. It has very small

access time i-e 55/70ns. The figure below shows the schematics of SRAM used on OBC

hardware design.


Figure 2.5: Block Diagram of EEPROM

Figure 2.6: Block Diagram of SRAM.

2.5.3 FLASH

At all times codes and data is kept in flash to avoid memory failure in case of unit failure.

The flash memory that is used in OBC’s design is AM29F400B by AMD technologies. It

is 4Mbit ,5V flash memory. It is also accessed through 16bit address bus and 16bit data

bus. Its data polling and toggle bits provide a software, detecting program and erase

operation. It has very small access time 70ns. And it has very small stand by current

1uA. The figure below shows the schematics of Flash memory in OBC.

Figure 2.7: Block Diagram of FLASH.

2.5.4 EDAC

IDT49C465APQFB is EDAC used in OBC’s design. This 32bit flow through EDAC is

placed on data lines between microcontroller and SRAM. Whenever, we write data to

SRAM, the EDAC also generates parity bits which are stored in parity SRAM. While

in read case, EDAC checks the integrity of data and if it is valid, it outputs the data

without any interrupt on ”ERR” pin for single pin error or ”MERR” pin for multiple bit


errors. If there is single bit error in data, it corrects the data with interrupt on ”ERR”

pin. If there is double bit error, it can’t correct nut can detect the error by giving1

interrupt on ”MERR” pin. However, there will be no data on O/P lines.

Since there is no chip enable signal in EDAC, all read and write operations are done

through combination of FMC NE3, FMC NWE and FMC NOE.

2.6 Sensors and Actuators Interfacing

The OBC is involved in communication with sensors, actuators and DHU. Different

sensors and actuators connected to OBC include Gyroscope, Star-tracker, Sun-sensor,

GPS, Magnetometer, Magnetorquer and Reaction-Wheels. In OBC, the communication

interfaces for different peripherals and modules, as specified by SUPARCO, are:

• RS-422• I2C• RS-485

RS422 is used for communication with some of sensors such as GPS, Gyroscope, Star-

tracker, RS485 bus is used to interface Reaction Wheels. Dual CAN bus is the main

mode of communication with DHU for relaying of telemetry data. Sun sensors and

Magnetometers are on analog channels where they are interfaced using ADCs with OBC.

Magnetorquer is driven by a driver circuit by PWM from OBC.

To make sure the reliability of these channels because the flight of satellite is totally

responsible on these sensors and actuators, redundancy is deployed at component level

where redundant transceivers are used. Redundant transceivers and redundant OBC

module are cross strapped to make connection.

All the interfaces are shown in figure 10. [10].

Figure 2.8: Interfaces of OBC


2.6.1 RS422

Gyroscope, GPS and Star-tracker are interfaced on a RS422 link, which is a requirement

of SUPARCO and the module of these sensors we are going to use also has interface

options of RS422. The requirement by SUPARCO is 38.4kbps data rate.

RS422, with the standard TIA/EIA-422, is a full duplex communication protocol with

differential signals of UART that has advantages like:

• Less subject to noise due to differential signals and twisted pair of wires• Longer cable lengths up to 1500m• High data rates

There are three sensors on RS422, so we need driver and receiver level-shifters with

maximum channels. The transceivers selected are AM26LV31I driver and AM26LV32I

receiver.

2.6.1.1 AM26LV31I/AM26LV32I

The AM26LV31I driver and AM26LV32I receiver pair are pin to pin compatible with

each other and can be interfaced with 3.3V Microcontroller. AM26LV31I has following

features [12]:

• Ultra-Low power dissipation• Temperature range of -40◦C to +85◦C• 4 driver channels in an IC

The 4 driver channels are an advantage when there are many devices. The features of

AM26LV32I are [13]:

• High noise immunity• Low power dissipation• Temperature range of -40◦C to +85◦C• Internal fail-safe circuitry for protection• 4 receivers per IC

Twisted wire is used with these drivers and receivers to make it immune to noise.

2.6.1.2 Schematic

The differential signal at receiver is connected via a bias network with termination

resistor to make sure some voltage difference between the differential lines. A series

resistor is placed for protection with the signals. The schematic is show in figure below:

The micro controller uses built-in UART controller that produces only Tx and Rx pins

that are level-shifted using these drivers and receivers.


Figure 2.9: RS422 Driver Block Dia-gram

Figure 2.10: RS422 Reciever BlockDiagram

2.6.2 RS485

Reaction wheels which SUPARCO is using for this satellite are interfaced on RS485, so a

bus of RS485 is required to interface 4 reaction wheels. Reaction wheels are the actuators

of the satellite for attitude control and for precise rotations. They are connected on a

bus like in figure 14.

Figure 2.11: Reaction Wheels interfacing with OBC

It works on UART that uses differential signals. We are using only half-duplex mode of

communication. We are using SN65HVD1780 transceiver that has one driver and one

receiver in the same IC. It is fully compliant with the ANSI TIA/EIA 485-A standard.

It has following features [11]:

• Can work with 3.3V supply for low power applications• Temperature range of -40◦C to +85◦C• Protection against bus-shorts• Noise immunity

The table 3.2 shows the function of each pin of the RS485 transceiver.

Table 2.2: Pins Description of SN65HVD1780 Transceiver


Figure 2.12: SN65HVD1780 RS485 Transceiver

PIN DESCRIPTION

A Driver output/Receiver input

B Driver output/Receiver input

D Driver data input

R Receive data output

DE Driver enable high

RE Receiver enable low

Vcc +5V supply

GND Ground

2.6.3 Magnetometer Interfacing

The Magnetometer module which SUPARCO is using in PNSS-1 project has analog

outputs and there are two Magnetometers in the satellite. The analog output of the

module is ranging from -10V to +10V which can be interfaced using an ADC with the

microcontroller.

The main difficulty was in the selection of the ADC due to negative analog output of

the Magnetometer. We chose AD7366 ADC as it provides the required input range and

it has two ADC channels that can accommodate both Magnetometers in a single IC.

Figure 2.13: Magnetometer interfacing

Both of the magnetometer inputs are fed to ADC via a driver amplifier which is imple-

mented using an op-amp. AD7366 has following features [2]

• Operating temperature range of -40◦C to +85◦C• 12-bit resolution• 2 channels• -10V to +10V input range


It has programmable input range that is configured using RANGE1 and RANGE0

pins. VA1, VA2 and VB1, VB2 are input pins of channel A and B respectively. It

has serial digital output DOUTA and DOUTB from where data is accessed using a

clock signal at SCLK pin. This digital output is fed to OBC where the data is processed.

2.6.4 Sun Sensors Interfacing

ACS unit contains total 8 sun sensors. Out of these 8 sun sensors 4 are connected to

primary OBC unit and other 4 are connected to redundant OBC unit. These sensors

have analogue outputs. Each sensor has four analogue outputs so there are total sixteen

different analogue outputs which are to be connected to each OBC. Due to unavailability

of 16 ADC channels in microcontroller an external ADC is used to digitize the analogue

signals. To simplify the design and to reduce the ADC circuitry a digitally controlled

analogue multiplexer is used in OBC unit design. This scheme reduced the number of

pins required to interface the sun sensors from 16 to 5. Four out of these Five are used

to control the multiplexer and one pin is the output of ADC. To access the data from a

sun sensor a control sequence is generated by microcontroller for multiplexer and then

it selects an output according to sequence. To eliminate noise and loading effects at

input of ADC an operational amplifier as voltage follower is placed between multiplexed

output and ADC’s input. The picture below depicts the scheme used in design of ADC

circuitry used for sun sensors.

Figure 2.14: Sun Sensors Interfacing Scheme.

2.7 CAN BusDedicated dual-CAN bus is used for communication between OBC and DHU. CAN

bus has already its heritage in space and military industry. In STM32F427, two CAN

controllers are available and both of them are used. The selection of CAN transceiver

is taken by considering the factors such as low power, fault tolerance and availability.

The basic requirement of CAN bus was reliability and fault-tolerance because its failure

can lead to mission failure. The transceiver chosen is TJA1055/3 [8]

2.7.1 TJA1055/3

It is a low power, fault-tolerant CAN transceiver with the following features:

• It is ISO11898-3 compliant transceiver which was a requirement by SUPARCO.


• Low current consumption in sleep mode.• Baud rate up to 125kBd.• Very high Electro Magnetic Immunity (EMI) in normal operating mode and in

low power modes.

• Switch to single-wire transmitter/receiver in error condition

2.7.2 Schematic

The CAN controllers used are already in STM32F427 microcontroller that produces Tx

and Rx signals. Two CAN transceivers are used with the OBC to make redundancy.

Both CAN buses are hot redundant; both are functional at the same time. The CANH

and CANL connections are connected to connectors, that will be connected to the main

CAN bus of satellite using a daisy-chain module. The schematic of the circuit is shown

in figure 3.19

Figure 2.15: Block Diagram of CAN Bus

When an error occurs, TJA1055 switches to single wire transmission/reception and the

CANH and CANL wires terminate with a predefined impedance connected via RTH

and RTL pins respectively. It comes with the extended temperature range of -40◦C to

+125◦C which is suitable for space temperature.


2.8 I2CFrom the requirements of SUPARCO, there is a link between DHU and OBC via I2C bus

which is redundant in case CAN bus fails. The STM32F427 has three I2C controllers

built-in. I2C is a multi-master bus used in serial interfaces with simple and ease. It is

a two-wire bus with standard speed of 100kbit/s. Dual I2C bus is used for redundancy.

The bus contains of:

• Two wires of SCL (Serial Clock) and SDA (Serial Data)• Termination resistors that are used to pull up the lines.• Devices; OBC and DHU.

Figure 2.16: I2C Bus

Chapter 3

PCB Design

The PCB design involved transfer of circuits from paper to software in the form of

schematics and then transforming the schematics to PCB. The platform that is used

for schematic development and PCB design is Altium Designer. PCB of OBC falls into

category of multilayer rigid PCB. PCB design meets all the requirements specified by

suparco. This chapter is divided into two parts. First part explains the constraints

and approaches to keep the design in specified constraints and second part explains the

design approach for routing, power and thermal planes.

3.1 Constraints

3.1.1 Dimensionality

While designing the PCB of OBC dimensionality was biggest challenge because the

envelop size of OBC was 208mm x 160mm so PCB size should have been less than these

dimensions. The OBC’s PCB is of 200mm x 152mm size so to keep the design with

in these constraints all Integrated circuits are placed at upper layer and all resistors

and capacitors are placed at bottom layer. This approach made the design simple and

debugging easy and reduced the size of PCB.

3.1.2 Component Placement

Component placement was another challenge with PCB design because there were 900

interfaces which should have been mapped with microcontroller, connectors and other

integrated circuits. So, components are placed in such a way that direct connection

establishes between adjacent integrated circuits. Voltage regulation circuitry is placed

near power connectors to minimize the power line inductance and series resistance. To

optimize the connections, the components having large number of connections with

connectors are placed near connectors.

3.1.3 Standards

As the standards are made to ensure viability of a circuit. OBC’s PCB design meets

international space standards[7] and standards specified by Pakistan Space and Upper

17

Chapter 4. PCB Design 18

atmosphere research commission, which are as follows:

• MIL-STD-55110• MIL-PRF-31032• ECSS-Q-ST-70-10C• IPC A-600• IPC-6011

3.2 Layered ApproachOne of the key feature of OBC’s PCB is its multilayer approach to solve the problems

regarding routing, power and thermal grounding planes. This approach has several

advantages which are as follows.

• Weight and size reduction• Better management of interfaces• Thermal layer for heat dissipation• Multiple functionality implementation

Keeping in mind advantages of multilayer approach OBC’s PCB has been divided into 8

layers which are explained in subsections below. The following figure shows the layered

approach employed in the PCB Design of OBC.

Figure 3.1: Layering Scheme of PCB

3.2.1 Power Planes

As per requirements by suparco OBC shall have power consumption less than 2W so

5V was regulated to 3.3V but some of the components were not available with ultra

low power consumption so two power supplies are used in design. To keep the design

simple, to reduce power line inductance and resistances two different power planes were

used one for 3.3V and other for 5V.

3.2.2 Thermal Ground Planes

OBC’s PCB contains 2 thermal ground planes. Adding ground planes has several ad-

vantages which are as follows:

• Reduction in number of connections

Chapter 4. PCB Design 19

• Reduction in signal noise• Reduction in interference through ground loops• Provides heat dissipation path from PCB to external structure through mounting

holes

• Combination of power and ground planes provides parallel plate decoupling ca-pacitor which prevents the noise from being coupled from one integrated circuit to

another

• Reduction in impedance of conduction path

3.2.3 Routing Layers

As the routing layers are used for interconnection between components, OBC’s PCB has

4 routing layers two of which are external layers and other two are inner layers. Adding

these layers simplified the design and reduced the complexity of connections between

integrated circuits.

Chapter 4

Space Compatible Design

4.1 Power RegulationPower utilization is very important in a space mission. Satellite can only draw power

from its solar panels, when its panel face the sun. For the rest of the time, all the units

will be provided power from the batteries. So, it is very important that all units in

satellite must use as low power as possible. In this way, power will be available for the

maximum time and operations of satellites will not be affected due to power failure.

As per URD [10] of SUPARCO, the power consumption should not exceed 2W. To reduce

the power consumption, two steps are taken:

1. Use of ultra-low power components.

2. Voltage regulation of 5V to 3.3V.

4.1.1 Ultra-Low Power Components

During component selection process, special care has been taken that those versions

of components should be selected which must consume as low power as possible. In

this way, it will be possible for us to save the power and fulfill requirement to keep the

power consumption below 2W.

4.1.2 Voltage Regulation

OBC is provided with two supply lines, i-e 5V and 12V. Other than few, most of the

components used in design, can operate at low voltages, even at 3.3V. To reduce power

consumption, +5V line is converted to +3.3V.

20

Chapter 5. Space Compatible Design 21

Figure 4.1: 5V to 3.3V regulation

The regulator chosen for this purpose is LT1086-3.3. It is a linear regulator havingnegligible output noise and has ripple rejection capability in it. Following figure showssimple scheme to convert 5V to 3.3V.

Figure 4.2: LT1086: 5V to 3.3V linear regulator

4.2 Protection

4.2.1 EMI Filter

The environment of space is very different from that of the earth. Due to the presence

of various radiations, many problems can occur in a space mission. The presence of elec-

tromagnetic waves can cause serious damage to the electronic equipment in a satellite.

Following problems may arise due to the electromagnetic interference:

• Electric surge in current lines.• Degradation of an electrical component.• Data loss.• Short circuit in whole module.

It is very important to protect On Board Computer from all these problems. In case

of no protection, some component or whole module may start malfunctioning and this

would cause a sure failure to the space mission.

There are some components available that can control EMI but they can increase overall

power loss. To keep the design simple, an inductor can cater our need. We all know

that, inductor stores energy in its magnetic field. In case of DC, inductor acts as a short

circuit and constant supply is provided. However, when current varies, a magnetic filed

is produced around inductor; this magnetic field produces another current in a direction


opposite to that of initial current. This induced current opposes its cause according

to Lenzs law, which was the variation in current. Hence the components will remain

protected since variations in current have been opposed. Capacitors can be connected

to eliminate the noise element.

This R-L filter is placed at the start of power rails coming into the module. Supply

to all the components is provided afterwards. The original circuit used in the design,

including voltage regulator and EMI filter is shown in the figure.

Figure 4.3: Circuit Diagram for EMI Filter

4.2.2 Latch Up Protection

Due to presence of cosmic rays, photons and free ions in space environment, single event

upset may occur causing a latch-up 1. To protect the components from degradation a

simple approach has been used. The scheme is shown in figure below.

Figure 4.4: Latch Up Protection Circuit

1Refer to Appendix A


Whenever the high surge of current comes, the resistors limit the current and allow the

limited current to pass through the component. The parallel combination of resistance

is used in such a way the total current must always be less than the maximum current

rating of an IC. This is done by carefully studying the data sheets of components.

In case of open circuit of one of the resistors, the current must be greater than the

minimum current requirement. So, for all the components used in the design, these

calculations are performed separately. The capacitors are used for noise rejection.

4.3 Fault Tolerance

4.3.1 Reset Circuitry

In a software, errors may occur during run time or the system may hang. Elimination

of errors or causes of system hang is very important, because one error may lead to

another error and this chain may lead to a mission failure. Since it is a space mission, it

is not possible to know the exact cause of problem. Therefore, the best way to overcome

this problem is to reset the overall system. Resetting of processor can eliminate the

problem, as it will start the code again from the very beginning. Say, if the software

has hung in hard fault handler because of some unknown reasons during runtime, this

resetting will solve the problem. This resetting of processor is achieved with the help

of watchdog timer.

4.3.1.1 Watchdog Timer

Watchdog timer is basically a hardware timer which is used for resetting the processors

in case of hardware and software faults [3]. It works in such a way that, if a task is

accomplished in its prescribed time, then a single is sent to its input which indicates to

the watchdog timer that the task has been accomplished properly and system is working

fine. If the watchdog timer does not receive any input signal in prescribed time, then it

means that there is some problem in the execution of task or the code might have hung.

In this case watchdog timer will output an active low signal which will be sent to the

processor to reset it.

Figure 4.5: Block Diagram for Watchdog Timer


The watchdog timer chosen in our hardware design is MAX6370. It is fully compatible

for a space mission. One of the best features it has is the selection of different timing

periods. We can choose different periods for different tasks [5].The internal structure of

this watchdog timer is shown in figure below [5]

Figure 4.6: MAX6370 Internal Structure

For example, in one of our tasks, we request data from a sensor, process it and command

an actuator accordingly. In normal execution, assume that the task is completed in 1

millisecond. For this task let the watchdog timer be set for 2 milliseconds. When the

task is completed properly, a signal will be sent to watchdog timer and watchdog timer

will be reset and hence no reset command will be generated by it. Now assume that

somehow watchdog timer does not receive command within 2 milliseconds. This will

indicate to the watchdog timer that the task has not been performed correctly or the

system has hung. Now MAX6370 will produce an output signal and it will reset the

processor. The reset process is summarized in the flow chart below.

This scheme is to solve only problems like code hanging or some small runtime error in

code. However, there are some problems which are permanent and cannot be solved by

just resetting the processor. To solve such problems, Fault Tolerant Module (FTM) is

used which is discussed next.

4.3.2 Fault Tolerant Module

Fault Tolerant Module is the upgraded form of reset circuit. It is used in the design to

eliminate the problems which are impossible for the reset sequence to remove. In case

of some fault that is not possible for reset circuit to remove, FTM transfers the control

to redundant OBC. Redundant OBC, which was otherwise off, is turned and performs

all the tasks. Fault tolerant Module works as follows:

1. First of all the problem is tried to be solved through watchdog timer reset tech-

nique.

2. Every time the processor is reset, a counter is incremented.


Figure 4.7: Flow Chart of Reset Sequence

3. When the counter reaches a particular value, it is assumed that fault is perma-

nent and it cannot be solved by just resetting the processor. The control is then

transferred to redundant OBC.

To understand the working of this module, assume the example of fetching data

from sensor and sending command to actuator again. Consider that due to some

malfunctioning, watchdog timer does not receive any signal from processor. Processor

will be reset by the watchdog and also a counter will be updated. Counter used in our

design is CD74HC393M. It is a 4 bit counter. Now the code will rerun from the start

and assume that reaching that particular point in code, watchdog timer does not receive

the signal again. Again the processor will be reset by watchdog timer and counter will

be incremented also. In our design, if the problem is not solved by resetting four times

then it is considered to be a permanent fault. Assume that the problem is not solved

and the counter reaches the value 4. At this point it will be assumed that now it is not

possible to solve the issue and hence the control should be transferred to the redundant

OBC. The control is to be transferred through DHU. A signal from the counter is sent

to the DHU and DHU then sends command to PDU of satellite to turn off the supply

to current OBC and turn on supply for redundant OBC. The working is shown in flow

chart below.


Figure 4.8: Flow Chart of Switching To Redundant OBC

Consider a case when the problem is solved by resetting the processor less than

four times and the code starts running again properly. In this case, we must clear

the counter. If it is not done, and again some fault occurs, the counter will start

incrementing from the previous value and hence it will send the request to switch OBC

before resetting the processor four times. Hence it is important to clear the counter

after resetting the processor.

To achieve this target, another 4 bit counter is used. This counter is updated every time

a task is completed. On completion of task processor sends signal to both, watchdog

timer and this second counter. Assume that there are total 8 tasks in the code. If all

the tasks are completed properly then it means that there is no fault in code anymore

and a cycle of task is completed. When the second counter is updated to value 8 on the

completion of last task, it will send a signal to clear the first counter and itself. In this

way, redundant OBC will only be turned on at correct time. The schematic diagram of

reset and FTM circuits are shown in figure below.

The figure shows two OR gates, SN74LVC1G32, output of which are used to reset the

two counters separately. Actually, the counters are to be cleared at the start when OBC

is switched on so that they should not have any random values. For this purpose, a

simple RC reset circuit is used. It works in such a way that when the power is turned

on, capacitor is initially short circuit and then slowly the capacitor discharges and thats

how a pulse is generated and is fed to the counter to clear it.

So, to reset the counters initially and then to reset them afterwards through second

counter, the OR gates are used.


Figure 4.9: Reset and FTM Schematics

Figure 4.10: Reset and Pulse Generator

Chapter 5

Implementation of the Onboard

Computer

The designed onboard computer is implemented in the following ways in order to

demonstrate its working and operation:

5.1 PCB HardwareThe 8-layer PCB housing all the telemetries and components is currently in its final

stages of component placement and design verification. Once the design is verified,

it will be sent for fabrication. After the fabrication the following tests [9] are to be

performed on the PCB before component placement and soldering:

1. Thermal Testing

2. Radiation Testing

3. Supervisory Testing

4. Redundancy Testing

5. EMI/EMC Testing

The final designed PCB hardware is shown in the following figure:

Figure 5.1: 3D Layout of PCB

28

Chapter 6. Implementation of the Onboard Computer 29

5.2 Simulation PlatformSince the final hardware of the OBC is yet to be completely fabricated and cannot be

made available for the application level development of OBC hence we had to choose a

standard Microcontroller board to write the firmware and deploy attitude control algo-

rithms. The microcontroller chosen was STM32F303 Discovery board. The simulation

platform designed has the following capabilities:

1. Light Dependent Resistors used as Sun Sensors on the prototype.

2. Complete 3D rotation ability.

3. Ability to track the Sun (simulated by a light source)

4. Communicating with the base station (Desktop PC) using Bluetooth communica-

tion.

5.2.1 Modes of Operation

The following functionalities have been currently implemented in the simulation

platform of the satellite:

5.2.1.1 Solar Tracking

We have been able to design the algorithms which can use the data from the sun sensors

to track the sun and orient the satellites solar panel towards it. This is one functionality

which is crucial for the satellite to maintain a constant power source. The sun is currently

being simulated by a light source.

The solar tracking mode is elaborated with the following block diagram:

Figure 5.2: Solar Tracking mode of Operation

5.2.1.2 Telemetry and Tele-command

The OBC streams the data collected from the sun sensors to the base station where

it is displayed visually on a GUI platform (demonstrate by figure). The GUI platform

also provided the user the functionality to send a command to the satellite to tilt itself

at a particular angle. The two way communication is currently being carried through

Bluetooth protocol.

5.2.2 Internal Structure of Simulation Platform

The figures 6.5 show the internal and external structures of the simulation platform:


Figure 5.3: Telemetry and Telecommand mode of Operation

Figure 5.4: Internal and External Structures of the Simulation Platform

5.3 Graphical User Interface for Telemetry and Tele-

commandIn order to demonstrate the communication of the simulation platform, a GUI interface

was developed in processing software. The software reads the values from the serial port,

to which a Bluetooth module is connected via UART to USB converter.

The Bluetooth module is synched with the Bluetooth module of the simulation platform

placed away from the base station (Desktop PC). The simulation platform sends its

current orientation in the form of angles of x and y axes. These values are then displayed

on the GUI. The GUI also provides control to direct the satellite platform to form a

specific orientation hence depicting the attitude control functionality. The figure below

shows the GUI developed for the mentioned operations:


Figure 5.5: Bluetooth module connected to PC via UART to USB converter

Figure 5.6: GUI developed for Telemetry and Tele-command

5.4 Theory of OperationThe process of attitude control of the satellite can be summarized in the following steps:

• The microcontroller board receives the desired orientation in the form of x and yangles from the Desktop PC over Bluetooth communication.

• It calculates the error based upon the desired orientation and the current orienta-tion angles.

• The calculated error is fed to multiple PID controller algorithms for each axis.• The PID controller then instructs the actuators to direct the satellite towards the

required orientation.

The Solar Tracking algorithm can be summarized as follows:

• The microcontroller measures the values of each of the four sun sensors simulta-neously.

• The algorithm calculates the difference of readings between each pair of parallelsun sensors.


• If the difference is positive between the upper and lower sun sensor it means thatthe sun is located downwards to the satellite otherwise it is upwards.

• Similarly the location of the sun towards right or left is determined by checkingthe difference between the values of the right and left sun sensors.

• After the position of the sun is determined, the satellite is tilted towards the sun.

Chapter 6

Results

In this chapter we shed light on the requirements that were to be satisfied by our design.

These requirements can be broadly split down into the two types; one enforced by

SUPARCO and the second that were meant to be satisfied in our developed prototype

which demonstrated the working of the satellite.

6.1 SUPARCO RequirementsInitially SUPARCO had given us a target of fulfilling as much as 153 different require-

ments [10]. These requirements are split into the following subcategories:

1. General Requirements: Requirements that specify notations, conventions, en-

gineering standards, life and other general constraints.

2. Functional Requirements: Requirements that specify the functions which are

intended or required form the units

3. Interface Requirements: Requirements that specify or define all types of elec-

trical interfaces, cabling and connections.

4. Performance Requirements Requirements that specify the desired performance

parameters of the unit.

5. Software Requirements: Requirements that specify software and firmware de-

sign practices and interface standards.

6. EMI/EMC Requirements: Requirements that define EMI/EMC specifications

for which the unit is to be designed.

7. Mechanical Design Requirements: Requirements that specify the constraints

for mechanical design of units housing/structure.

8. Thermal Design Requirements: Requirements that specify thermal design

constraints/limits for the unit.

9. PA Requirements: Requirements that specify requirements related to Product

Assurance and Quality Assurance.

33

Chapter 7. Results 34

10. Test Requirements: Requirements that specify constraints for hardware and

software test and verification.

11. Parts Selection Requirements: Requirements that specify the constraints and

guidelines for EEE parts selection for the unit.

Figure 6.1: Breakdown of Requirements enforced by SUPARCO

6.1.1 Requirements Compliance

The requirements met through our design are broken down in the pie chart below. Only

5% of the requirements are not met. The majority of the requirements not met are

related to the software part and since the complete software requirements are not yet

defined, there is no feasible way to test these requirements. Another reason being, the

non-availability of certain hardware peripherals due to their high cost and sensitivity

such as Magnetometers, Reaction Wheels and Star trackers. As these hardware compo-

nents cannot be procured so their software support remains incomplete.

The 20% of the requirements include thermal and mechanical requirements which cannot

be judged by us as they require sophisticated lab facilities and testing environment

which can only be provided by SUPARCO officials as we do not possess the required

authorization.

Chapter 7. Results 35

Figure 6.2: Requirements Compliance Pie Chart

6.2 Prototype RequirementsAs part of the final demonstration of our project, we were asked to build a working

prototype of the satellite. Since majority of the sensors and peripherals such as Sun

Sensors, Magnetometer and Star trackers cannot be procured due to their cost and

sensitivity, we faced the challenge of simulating the satellite behavior using off the shelf

components.

Sun Sensors were fabricated using commonly found Light Dependent Resistors, the

sun was simulated using a light source such as a bulb. Four such sun sensors were

installed in parallel to each other, one on each side of the square shaped satellites side.

Whenever light falls on an LDR, its resistance decreases and hence the orientation of

the sun (or the light source) based upon the values of each sensor can be determined.

The orientation of these sun sensors was crucial as LDRs mostly detect the light in one

direction but in our application the sun could be anywhere in the 3D space. Careful

orientation of the sun sensors on the satellite and calibration of ADC values made the

precise localization of sun possible.

Another requirement was the precise motion of the motors for the orientation of the

satellite towards the sun, as we used off the shelf DC motors and motor drivers to

control their speed and motion. The precise control of these motors was very challenging

as most of the time the motors over sped or failed to carry the weight of the satellites

platform. To overcome this issue, multiple PID controllers were employed for each axis

of the motion and their careful tuning resulted into a near perfect tracking motion.

Finally, a robust and continuous communication channel between the platform and the

satellite needed to be maintained to continuously stream the data between the two. This

requirement was achieved using the master slave communication between HC-06 acting

in Slave mode and HC-06 acting in Master mode.

Chapter 7

Conclusions

After one and a half year of arduous efforts, it brings us much satisfaction to meet

the expectations of the first of its kind collaboration between industry and academia

initiated by SUPARCO. The area of Space Technology which was completely alien to

us before the inception of this project, has now become an integral part of the learning

during our undergraduate education.

The successful completion of this project and the set of requirements posed corroborates

the hypothesis that the linkage between academia and industry should grow stronger to

improve the standard of higher education in Pakistan.

The table above shows the cost and quantity of each component to be installed on the

final hardware of the Onboard Computer. The components are completely funded by

the SUPARCO.

36

Chapter 10. Conclusion 37

7.1 Budget Analysis

Table 7.1: Detailed breakdown of cost of OBC

Component Quantity Unit Price ($) Total Price($)

STM32F427IIT6 1 15.85 15.85

DSC1001CL 1 1.58 1.58

MAX6370 1 3.62 3.62

SN74LVC1G32 4 0.36 1.44

CD74HC393M 1 0.71 0.71

LT1086CM-3.3 1 5.07 5.07

TJA1055T/3 2 1.6 3.2

DS17887-3 1 22.8 22.8

SN74LVC16T245 4 2.28 9.12

SN74HC245DW 1 0.52 0.52

AM26C32QD 2 1.59 3.18

AM26C31QD 2 1.77 3.54

SN65HVD1780 1 4.5 4.5

LM158JG 1 7.65 7.65

AD7820 1 25.7 25.7

CD74HC4067 1 0.85 0.85

AD7366 1 11.23 11.23

AD8021 2 3.66 7.32

PCB fabrication 1 700 700

AM29F400B 2 3.3 6.6

AT28C1024 2 22 44

LDT49C465 1 15 15

SNLVCC3245 4 1.2 4.8

LY62W25616 3 4.5 13.5

Total 911.78($)

94825 PKR

Chapter 10. Conclusion 38

7.2 TimelineThe total time span of one and a half year spent on the development of Onboard Com-

puter of PNSS-1 can be split down into multiple phases from the inception of the project

to the final project sign-off. The different milestones and their description is define in

the figure 1.

Figure 7.1: Project Timeline

Appendix A

Latchup Protection

A latch up is a type of short circuit which can occur in an integrated circuit (IC). More

specifically it is the inadvertent creation of a low-impedance path between the power

supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper

functioning of the part, possibly even leading to its destruction due to overcurrent. Latch

up caused by a SEU is known as single event latch up. The thyristor in an integrated

circuit is formed due to parasitic transistors.

Figure A.1: Parasitic transistors in a CMOS circuit

A parasitic thyristor of this kind in an integrated circuit can be triggered in various

ways:

• If there is a voltage at the input or output of a circuit that is more positive thanthe supply voltage, or more negative than the ground connection (or, to be precise,

more negative than the connection to the substrate), current flows into the gate

of the thyristor. If the amplitude and duration of the current are sufficient, the

thyristor is triggered. The transit frequency of the parasitic transistors is only

about 1 MHz. For this reason, overvoltages and undervoltages with durations of

only a few nanoseconds, such as result from line reflections along the connections

39

Appendix A. Lenz’s Law 40

on circuit boards, usually are not able to trigger the thyristor. With lines of

several meters in length and overshoots of correspondingly longer duration, the

probability that the thyristor might be triggered must be taken into account. This

applies also at the interfaces between a circuit and the outside world; unacceptable

overvoltages also often occur at this point.

• An electrostatic discharge can trigger the parasitic thyristor. Even if the electro-static discharges have a duration of only a few tens of nanoseconds, when this

happens, the complete chip may be flooded with charge carriers, which then flow

away slowly, resulting in the triggering of the thyristor.

• Also, latch-up can be initiated by ionizing radiation. This is important with com-ponents that operate close to a source of high-energy radiation

After the triggering of the thyristor, various reactions can be observed:

• The parasitic thyristor triggers very rapidly and enters a very low-resistance state.The source of the supply voltage is short circuited as a result of the circuit that

has been affected. A very high current flows, which, in a very short time, leads

to destruction of the component. The thyristor can be switched off again only by

switching off the supply voltage. Therefore, the recommendation in the literature

is that a resistor should be placed in series with the supply voltage connection to

the integrated circuit. If the thyristor does trigger, this resistor limits the current

to a value that no longer poses any danger to the device. If possible, the resistor

should limit the current to a value below the holding current of the thyristor such

that, after the end of the conditions that led to its being triggered, the thyristor

automatically switches off.

Appendix B

Schematics

First step to the proper hardware design of OBC was the designing of schematics s:

of various modules. Schematics were made in Altium software. Some of the schematic

diagrams are shown here.

B.1 SRAM

Figure B.1: Schematics of SRAM

41

Appendix B. Schematics 42

B.2 EDAC

Figure B.2: Error detection and Correction module

B.3 RTC

Figure B.3: RTC


B.4 CAN Bus

Figure B.4: CAN Transceiver and Bus

B.5 Flash

Figure B.5: Schematics of Flash Memory


B.6 Power and EMI

Figure B.6: Power and EMI Filtration Circuit

B.7 Differential Line Receiver

Figure B.7: Quadruple Differential Line Receiver


B.8 Reset and Fault Tolerant Module

Figure B.8: Reset and FTM Circuit

References

[1] Design of Attitude Control Systems for Cubesat-class Nanosatellite, 2013.

[2] AD7366 Datasheet. Analog Devices, 2016.

[3] ARM. Watchdog timer, 2017. URL https://developer.mbed.org/cookbook/

WatchDog-Timer.

[4] Maxim Integrated. Real time clock/ds17885-ds17887, janaury 2017. URL https:

//datasheets.maximintegrated.com/en/ds/DS17285-DS17887.pdf.

[5] Pin Selectable Watchdog Timers. Maxim Integrated, 2016.

[6] Norma Crosby Michael J Rycroft. Smaller Satellites: Bigger Business? Springer,

2002.

[7] NASA. Printed circuit boards, janaury 2017. URL https://nepp.nasa.gov/

index.cfm/27505.

[8] TJA1055 Datasheet. NXP Semiconductors, 2016.

[9] SUPARCO. Obc unit test plans. 2015.

[10] SUPARCO. Obc unit requirements document. 2015.

[11] SN65HVD1780 Datasheet. Texas Instruments, 2016.

[12] AM26LV31 Datasheet. Texas Instruments, 2016.

[13] AM26LV32 Datasheet. Texas Instruments, 2016.

46

https://developer.mbed.org/cookbook/WatchDog-Timerhttps://developer.mbed.org/cookbook/WatchDog-Timerhttps://datasheets.maximintegrated.com/en/ds/DS17285-DS17887.pdfhttps://datasheets.maximintegrated.com/en/ds/DS17285-DS17887.pdfhttps://nepp.nasa.gov/index.cfm/27505https://nepp.nasa.gov/index.cfm/27505

AcknowledgmentsList of FiguresList of TablesAbbreviationsAbstract1 Introduction1.1 Motivation1.2 Structure of the Satellite1.3 Structure of ACS1.4 Problem Statement1.5 Challenges

2 Design of Onboard Computer 2.1 Microcontroller2.2 Oscillator2.3 Real Time Clock2.4 JTAG2.5 External Memories2.5.1 EEPROM2.5.2 SRAM2.5.3 FLASH2.5.4 EDAC

2.6 Sensors and Actuators Interfacing2.6.1 RS4222.6.1.1 AM26LV31I/AM26LV32I2.6.1.2 Schematic

2.6.2 RS4852.6.3 Magnetometer Interfacing2.6.4 Sun Sensors Interfacing

2.7 CAN Bus2.7.1 TJA1055/32.7.2 Schematic

2.8 I2C

3 PCB Design3.1 Constraints3.1.1 Dimensionality 3.1.2 Component Placement3.1.3 Standards

3.2 Layered Approach 3.2.1 Power Planes 3.2.2 Thermal Ground Planes3.2.3 Routing Layers

4 Space Compatible Design4.1 Power Regulation4.1.1 Ultra-Low Power Components4.1.2 Voltage Regulation

4.2 Protection4.2.1 EMI Filter4.2.2 Latch Up Protection

4.3 Fault Tolerance4.3.1 Reset Circuitry4.3.1.1 Watchdog Timer

4.3.2 Fault Tolerant Module

5 Implementation of the Onboard Computer5.1 PCB Hardware5.2 Simulation Platform5.2.1 Modes of Operation5.2.1.1 Solar Tracking5.2.1.2 Telemetry and Tele-command

5.2.2 Internal Structure of Simulation Platform

5.3 Graphical User Interface for Telemetry and Tele-command5.4 Theory of Operation

6 Results6.1 SUPARCO Requirements6.1.1 Requirements Compliance

6.2 Prototype Requirements

7 Conclusions7.1 Budget Analysis7.2 Timeline

A Latchup ProtectionB SchematicsB.1 SRAMB.2 EDACB.3 RTCB.4 CAN BusB.5 FlashB.6 Power and EMIB.7 Differential Line ReceiverB.8 Reset and Fault Tolerant Module

References

New Design and Development of On board Computer of Micro LEO … · 2017. 12. 6. · PNSS-1 falls into the category of Micro Low earth orbit satellites, the satellite comprises of

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