Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06 Silicon Neural Systems Neuromorphic Engineering “in silico” neural systems design VLSI Microchips Neuromorphic Engineering Neural Systems Learning & Adaptation g 1 g 0 g 2 g 0 g 0 g 2 g 2 g 1 g 1
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Neuromorphic Engineering“in silico” neural systems design
VLSIMicrochips
Neuromorphic Engineering
NeuralSystems
Learning&
Adaptation
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g2
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g0
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Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Today’s Hottest MicrochipIntel’s Itanium 2
The numbers …– 0.5 billion transistors in
120nm CMOS– 1.6GHz clock, 64-bit
instruction, 9MB L3 cache, 6.4GB/s I/O
– 2553 SPECfp_base2000 (30% faster than 2.8GHz P4)
– 130 Watts
Source: IEEE ISSCC’2002
… and what they meanFaster/cooler:
• Scientific computing• Database search• Web surfing• Video games
but your PC is still dumb!
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Chips and Brains• Itanium:
– 3 109 floating op/s• 5 108 transistors• 2 109 Hz clock
– 1010 Hz memory I/O• 128-b data bus @ 400MHz
– 130 Watts
• Human brain:– 1015 synaptic op/s
• 1015 synapses• 1 Hz average firing rate
– 1010 Hz sensory/motor I/O• 108 nerve fibers
– 25 Watts
• Silicon technology is approaching the raw computational power and bandwidth of the human brain.
• However, to emulate brain intelligence with chips requires a radical paradigm shift in computation:– Distributed representation in massively parallel architecture
• Local adaptation and memory• Sensor and motor interfaces
– Physical foundations of computing
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Physics of ComputationCMOS Silicon Technology
p- Si substrate
n+ n+
poly SiSource
SiO2GateDrain
n-Channel
Gate
Source Drain
nMOS transistor circuit symbol
Ene
rgy
Gat
e vo
ltage
Cross-section of nMOS transistor in 0.18µm CMOS process (Intel, 2002)
poly
Si
Channel
Source Drain
Gate
Voltage-dependent n-channel– Electron transport between source and drain– Gate controls energy barrier for electrons
across the channel– Boltzmann distribution of electron energy
produces exponential increase in channel conductance with gate voltage
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Physics of ComputationCMOS Silicon Technology
poly SiSource
SiO2GateDrain
Ene
rgy
Gat
e vo
ltage
Gate
Voltage-dependent p-channel– Hole transport between source and drain– Gate controls energy barrier for holes
across the channel– Boltzmann distribution of hole energy
produces exponential decrease in channel conductance with gate voltage
Sourcep- Si substrate
p-Channelp+ p+
n- well Drain
pMOS transistor circuit symbol
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Physics of Neural ComputationSilicon and Lipid Membranes
Voltage-dependent p-channel– Hole transport between source and drain– Gate controls energy barrier for holes
across the channel– Boltzmann distribution of hole energy
produces exponential decrease in channel conductance with gate voltage
poly SiSource
SiO2GateDrain
Ene
rgy
Gat
e vo
ltage
p- Si substrate
p-Channelp+ p+
n- well
Squid giant axon (Hodgkin and Huxley, 1952)
Voltage-dependent conductance– K+/Na+ transport across lipid bilayer– Membrane voltage controls energy barrier
for opening of ion-selective channels– Boltzmann distribution of channel energy
produces exponential increase in K+/Na+
conductance with membrane voltage
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Physics of Neural ComputationSilicon and Biochemical Synapses
Voltage-dependent p-channel– Hole transport between source and drain– Gate controls energy barrier for holes
across the channel– Boltzmann distribution of hole energy
produces exponential decrease in channel conductance with gate voltage
poly SiSource
SiO2GateDrain
Ene
rgy
Gat
e vo
ltage
p- Si substrate
p-Channelp+ p+
n- well
(from Shepherd 1979)
Voltage-dependent quantal release– K+/Na+ through postsynaptic membrane– Presynaptic membrane voltage controls
energy barrier for neurotransmitter release– Boltzmann distribution in quantal release
energy produces exponential dependence of postsynaptic K+/Na+ conductance
Presynaptic membrane potential
Mea
n po
stsy
napt
ic m
embr
ane
curre
nt
Presynaptic cell
Postsynaptic cell
Synaptic cleft
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Why Develop “Neural” Silicon Chips?Biology Motives:
– In silico emulation of neural and sensory-motor systems• Real-time computational power• Accounts for noise and imprecision in neural elements
– Analysis by synthesis• Emulating form and structure of neural systems provides better
understanding, accounting for physical and architectural constraints– Interfacing silicon with neurons and synapses in vivo
• Allows to observe and control neural and synaptic activityEngineering Motives:
– Efficiency of implementation• Lower power, smaller size
– Real-world interface• Integrated sensors and actuators• Analog, continuous-time dynamics• Intelligent brain-machine interfaces!
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Neuromorphic Systems Design Flow
Neural Model
Microchip(s)
Neuromorphic System
Circuit Design and Simulation
Microfabrication
System Integration
Chip Layout
Chip Testinghttp://www.mosis.org
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Example: Silicon Model of Visual Processing in V1
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C0
C+z C+y
C+xC-x
C-y C-z
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I0I0
I0
I0I+yI+z
I-x
I+x
I-y I-zLGN
V2
6
4
3
2
6
V1
Optic Nerve
Bipole cells(diffusive network)
Complex and hypercomplex
cells(lateral
inhibition)
88 transistors/pixel(including photodetector)
Single-chip focal-plane implementation (Cauwenberghs and Waskiewicz, 1999)Neural model of boundary contour representation
in V1, one orientation shown (Grossberg, Mingolla, and Williamson, 1997)
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Reconfigurable Synaptic Connectivity and PlasticityFrom Microchips to Large-Scale Neural Systems
Multi-Chip Systems
Address-Event Representation
Neural Systems
Synaptic Plasticity &
Wiring
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Biochemical Synapse Mechanisms• It is infeasible to
implement networks of detailed synaptic models on a single silicon chip.
• Hybrid approach:– Analog silicon chips
model continuous-time membrane dynamics
– Action potentials are encoded as ‘address-events’.
– A look-up table indexed by address-events implements synaptic connectivity and plasticity in the address domain
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Address-Event Representation (AER)Mahowald, 1994; Lazzaro et al., 1993
– AER emulates extensive connectivity between neurons by communicating spiking events time-multiplexed on a shared data bus.
– Spikes are represented by two values:• Cell location (address)• Event time (implicit)
– All events within ∆t are “simultaneous”
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Address-Event Synaptic ConnectivityGoldberg, Cauwenberghs and Andreou, 2000
– ‘Virtual’ synapses• Dynamically reconfigurable• Arbitrary connectivity
– Quantal release: R = n p q• n: multiplicity (repeat event)• p: probability of release (toss a coin)• q: quantity released (set amplitude) IFAT2 (2000)
transceiver (IFAT)
1
2
Sender
Receiver
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Reconfigurable Silicon Large-Scale Neural Emulator
Sender
Receiver
IFAT3 (Vogelstein, Mallik and Cauwenberghs, 2004)
• 9,600 neurons– 4 silicon membrane chips (IFAT)
• 4 million, 8-bit “virtual” synapses– 128MB (32bX4M) non-volatile RAM
• 1 million synaptic updates per second– 200MHz Spartan II Xilinx FPGA “MCU”
• Dynamically reconfigurable– Rewiring and synaptic plasticity (STDP etc.)– Driving potential (DAC) and conductance (IFAT)
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Silicon Membrane Array TransceiverVogelstein, Mallik and Cauwenberghs, 2004
60 x 40IFATArray
Event Arbitration
Even
t Cod
ing/
Dec
odin
g
IFAT3 (2004)
– Voltage-controlled membrane ion conductance
• Event-driven activation• Dynamically reconfigurable:
– conductance g– driving potential E
– Address-event encoding of pre-and post-synaptic action potentials
Na+ K+ Na+(strong)
AP
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Silicon Membrane Circuit
gi(t) ion-specific membrane conductance
Ei ion-specific driving potential
Synapse Synapse subcircuitsubcircuit Action potential generation and Action potential generation and AER handshakingAER handshaking
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Spike Timing-Dependent Plasticity
Bi and Poo, 1998
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Spike Timing-Dependent Plasticityin the Address Domain
Causal Anti-Causal
Gert Cauwenberghs UCSD BGGN260, 1/31-2/2/06Silicon Neural Systems
Spike Timing-Dependent Plasticity on the IFATVogelstein et al, NIPS*2002