Network Syncronization

Politecnico di MilanoDipartimento di Elettronica e Informazione

Piazza Leonardo da Vinci 32, 20133 Milano MITel. 02-2399.3503 - Fax 02-2399.3413

E-mail: [email protected]

Stefano Bregni

Synchronization of Digital Telecommunications Networks

Distinguished Lecturers Program

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Introduction

Lecture Outline

Synchronization processes in telecommunications

A historical perspective on network synchronization

Synchronization networks

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Synchronization Processes in Telecommunications

1


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Carrier Synchronization

coherent demodulation of an amplitude-modulated signal is based on the recovery of the carrier, i.e. on the recovery of a signal with coherent phase and frequency with the original carrier

x t s t f t( ) ( ) cos= ⋅ 2 0π

x t t s t ts t

t( ) cos ( ) cos( )

cos⋅ = ⋅ = +ω ω ω02

0 021 2b g

βcos2

)(tsphase error frequency error

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recovery of the timing signal associated to a received digital signal

Symbol SynchronizationClock Recovery

channel equalization

filter

symbol decision

r(t)

sampler

r(kT) 1011

t=kT

symbol synchronizer(clock recovery)

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Timing Signal and Significant Instants

T = 1/ν0

dt

tdt

ttAts

)(

2

1)(

)(sin)()(

Φ=

Φ=

πν

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Frame Synchronization

once that the received bits have been identified, it is necessary to determine the beginning and the end of code words or of groups of code words (frames)

bit semantics

101011010001010100101011011110101010110010010101110110001011101001101100101

t

frame frame

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Bit Synchronization

synchronization of an asynchronous bit stream according to a local clock

mapping of tributaries into a PDH multiplex signal (with bit justification)mapping of tributaries into SDH VCs (with or without bit justification)synchronization and frame boundary alignment of PCM multiplex signals at inlets of a digital switching exchange (with slip buffering)

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Bit Synchronizerscheme of principle

any frequency offset between writing and reading yields, sooner or later, to buffer underflow (⇒ bit repetition) or overflow (⇒ bit loss)

slip

slips are deadly!

input signal to synchronize circular

buffer

clock recovery

write counter

read counter

write address

read address

equipment clock

f w f r

output signal synchronized

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Packet Switchingpeculiarities

packet switching can be efficient to integrate real-time and data traffic (e.g., ATM, IP)

packets are delivered with random inter-arrival timespackets can be even delivered out of sequence at the receiver, it is not possible to recover exactly the source frequency, based only on the received bit flow

1 2 3 4 5 6 7 8 9

1 2 3 5 4 6 8 9 7

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Packet Synchronization

effective transport of voice and video and circuit emulation are possible by means of equalization of random packet delivery delays (packet jitter)

techniques to rebuild the original bit rate from the received packet sequence

asynchronous networknodes are timed by independent clocksroundtrip delay measurementadaptive strategies

synchronous networknodes are timed by some network synchronization facilitySynchronous Residual Time Stamp (SRTS) is standardized for ATM circuit emulation (AAL-1) (ATM is not suited for an asynchronous environment!)

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Network Synchronization

distribution of time and frequency over a network of clocks, spread over an even wide geographical area, by using the communication links among them

goal: to make all network elements to operate synchronously

possible applicationssynchronization of transmission and switching networkssynchronization of networks based on some form of TDMAarray antennas

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network synchronization is ubiquitous

Examples of Synchronization of a Large Number of Oscillators in Nature

synchronous fireflies (W. C. Lindsey, J. Buck and E. Buck)they flash their light organs at regular but individual and independent intervals if they are not close togetherif many of them are placed in a relatively close proximity, they exhibit a synchronization of their light organs until they flash in unison

synchronization of individual fibers in heart muscles to produce the familiar heartbeat

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Synchronization of Real-Time Clocks

a different kind of network synchronization

real-time clocks supply the system time within equipmentexample: date and time in a PC

the distribution of the national standard time is to the purposes of network control and management

all events reported to the equipment monitoring system (faults, defects, BER threshold overflowing, line alarms, etc.) must be accompanied by their recording time to allow their correlation

example: 23 Dec 1998, 01.32.04 AM

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Multimedia Synchronization

integration of heterogeneous elements such as text, images, audio and video in a multimedia communications

time-dependency of data sequences may be simply linear, as in the case of an audio file played on a sequence of images (slide presentation with soundtrack), but other modes of data presentation are also viable, including reverse, fast-forward, fast-backward and random access

when non-sequential storage, data compression and random communication delays are introduced, the provision of such capabilities can be very difficult

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A Historical Perspective on Network Synchronization


1

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Single-Side-Band demodulation must be coherent

carrier synchronization can follow a point-to-point strategy (i.e., limited to each single transmission system) in simple networks

AT&T made up the first synchronization network of history for its long-distance FDM analog transmission network in the '70s

locally, PLL-based carrier supplies generated all reference frequencies used by multiplexers and demultiplexers at all hierarchical levelscarrier supplies were synchronized by distributing pilot frequencies derived from a network master clockfree-run frequency accuracy requested to limit distortion in the demodulated signals was in the order of 1e-7

Synchronization in Analog FDM Networks

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Advent of Digital MultiplexingPlesiochronous Digital Hierarchy (PDH)

plesiochrony means synchronization anarchyall clocks are autonomousonly the frequency offset tolerance is specifiedasynchronous digital multiplexing allows multiplexing of asynchronous tributaries with substantial frequency offsets

bit justification

PDH networks do not need synchronization

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Advent of Digital Switchingthe advent of digital TDM techniques yielded a progressive integration of transmission and switching

the PCM frame allows switching time slots (TS)

moving octets from one TS to another is possible only if PCM signals are exactly synchronized with frame starts aligned

bit synchronizationat inputs of digital

switching exchangesswitching

fabric

bit andframe

synchronizer

input asynchronous PCM frames

PCM frames synchronized

output PCM frames

synchronized and switched

equipment clock

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Impact of Slips on Digital Servicesstudies reported throughout the '70s and the '80s describe

the effects of slips on services of various kind

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uncompressed voice (POTS) only a little percentage of slips leads to occasional audible clicks in the reproduced audio

compressed voice a slip leads an audible clickgroup 3 facsimile a slip can wipe out several scan linesdata transmitted on POTS channel (voiceband modem)

a slip may cause a drop out lasting from 10 ms to 1.5 s

digital video transmission a slip may cause segments of the picture to be distorted or frames to freeze for periods of up to 6 s

data transport protocols slips reduce transmission throughputencrypted services a slip may result in the loss of the encryption key

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PDH systems are transparent to the timing of transported signals

Timing Transfer through a PDH Transmission Chain


5

8Mb/s

34Mb/s 140

Mb/s

8Mb/s

34Mb/s

2Mb/s

2Mb/s

PDH transmission chain

clock

timing transfer

asynchronous multiplex signal with timing signal embedded

other digital signals

PDH MUX

PDH MUX

PDH MUX

PDH MUX

PDH MUX

PDH MUX

masterclock

Digital Exchange

Fundamental Law of Digital Transmission

ChainsALL BITS THAT GET IN ON ONE SIDE MUST GET OUT FROM THE OTHER

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Synchronization of Digital Switching Exchanges across PDH Links

point-to-point timing transfer

Digital Exchange

2Mb/s


PDH MUX

PDH MUX

2Mb/sDigital

Exchange

masterclock

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Synchronization of Digital Switching Exchanges Served by SASE Clocks across PDH Links

Digital Exchange

2Mb/s


2MHz

SASE

PDH MUX

PDH MUX

2Mb/sDigital

Exchange

SASEmasterclock

2MHz

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Synchronization and SDH/SONET Digital Transmission

SDH networks are usually synchronized to avoid any pointer action

pointer adjustments can yield excessive jitter on demapped tributariessome equipment is designed to minimize this issue

enhanced pointer processorenhanced synchronizer/desynchronizer

it is anyhow advisable to synchronize SDH networks to avoid problems in multi-vendor PDH/SDH networks

SDH technology allows a more effective timing transfer between offices

contrary to PDH, in SDH networks timing should not be carried on signals mapped in STM-N frames

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Synchronization of Digital Switching Exchanges Served by SASE Clocks across SDH Links

Digital Exchange

2Mb/s

SDH transmission chain

2MHz

SASE

SDH MUX

SDH MUX

2Mb/sDigital

Exchange

SASEmasterclock

2MHz

2MHz

STM-N

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Is ATM Really Asynchronous?

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popular misunderstanding

Asynchronous Transfer Mode refers to how information is transferred, not to the physical network

Asynchronous Transfer

Mode(ATM)

source #1

source #2

source #3

source #4

source #5

source #6

Synchronous Transfer

Mode(STM)

source #1

source #2

source #3

source #4

source #5

source #6

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Synchronization in ATM Transport Networks

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synchronization plays an essential role in ATM networksin particular in the integration of ATM equipment into existing telecommunications networks

ATM equipment requires synchronizationto support Constant Bit Rate (CBR) services, based on AAL type 1 (SRTS cell synchronization)to support synchronous physical interfaces

PCM (E1: 2.048 Mb/s, DS1: 1.544 Mb/s)SDH/SONET (155.520 Mb/s and higher)

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Synchronization of ATM Equipment

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synchronization of modern ATM equipment is accomplished through dedicated ports (2.048 MHz, ITU-T G.703/13)

the most straightforward way of synchronizing an ATM NE is to integrate it into a synchronization network

ATM equipment should take the timing from SASE/BITSaccuracy of timingno burden of avoiding timing loops (duty of the synchronization network manager)

if no synchronization network is available, then line-timing is the only feasible way of synchronizing

synchronization is supplied via SDH, E1 or DS1 signalscare must be taken to avoid timing loops

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Synchronization of Cellular Mobile Wireless Telephone Networks

wireless networks pose specific synchronization requirements

BTS, BSC and MSC need to be synchronized to ensure slip-free interconnection at trunk linesBTS needs to be synchronized to ensure frequency stability on the on-air wireless channels

GSM and TDMA (USA) systemsfrequency synchronization

CDMA (IS-95 USA) systemalso precise time synchronization

MSC

air interface air interface

air interface air interface

trunk lines

trunk linesBSCtrunk lines

trunklines

to PSTN

BTS BTS

BTS BTS

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CDMA, GSM and TDMA specifications require frequency stability to avoid that centre frequencies of on-air channels drift and thus

no co-channel interferenceno problems at hand-off from one cell to another

CDMA (IS-95 USA) specifications require also time stability to keep pilot sequences in all cells well aligned and thus

no problems at hand-off from one cell to another

new services will require even stricter frequency and time stabilitylocating mobile handsetsthird generation wireless systems (UMTS)

ATM and backhaul radio can be used as transport technology among BTS, BSC and MSCdo not feature a good timing transparency

Synchronization Requirements of Cellular Networks

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Synchronization Networks

1


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to align the absolute time scales of network nodestime synchronization

nodes are synchronous with same total phasesynchronization of real-time clocks for date and time (NTP)

to align the significant instants of timing signals of network nodes aside from a constant phase error

frequency synchronization with phase control but with no need to compensate average delays of synchronization signals

nodes are synchronous but with different total phases (PLL)no pointer actionno slips

to make equal the frequencies of network nodesfrequency synchronization without phase control

nodes are mesochronous (FLL)there may be pointer action and slips (phase random walk)

Network Synchronization Goals

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the facility implementing network synchronization

nodesautonomous clock

stand-alone device able to generate a timing signal, starting from some periodic physical phenomenon

slave clockdevice that generates a timing signal having phase (or much less frequently frequency) locked to a reference timing signal at its input

linkscommunication channels among nodes

digital circuitsanalog channelsconnections at higher OSI levels

Synchronization Network

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Issues of Timing Distribution

tactics of point-to-point timing transfer

how to transfer timing from one node to another

the main techniques have been described presenting the historical evolution of network synchronization

strategy of network synchronization

how to organize timing distribution to all the nodes of the network

higher-level issue

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no-synchronization strategy

anarchy is the easiest form of government, but it relies on the good behavior of the single elements

all network clocks are autonomous

the synchronization of processes in different nodes is entrusted to the accuracy of clocks

Full PlesiochronyAnarchy

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distribution of the timing reference from one master clock to all the other slave clocks of the network

directly or indirectlystar topologytree topology

despotism is generally considered as unethical, but it is certainly effective in ensuring a tight control on the slaves

what happens should the master fail?

Master-Slave SynchronizationDespotism

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based on the direct, mutual control among clocks

meshed topology

complexity of the dynamic system control

extremely reliable

Mutual SynchronizationDemocracy

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mutual synchronization strategy is adopted for a few network core clocks

master-slave strategy is adopted for the peripheral clocks

Mixed Mutual/Master-Slave SynchronizationOligarchy

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generalization of democratic strategy

some count more than others do

each of N network nodes is given a relative weight wi

Hierarchical Mutual SynchronizationHierarchical Democracy

1,10 =≤≤ ∑Ni ii ww

w1

w3

w5

w2

w4

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variant of the pure MS strategyalternate synchronization routes for protectionif the master fails, another clock takes its place according to a hierarchical plan

static pre-selected protection routing tabledynamic protection via Synchronization Status Messages (SSM)

the most widely adopted to synchronize modern digital telecommunications networks

Hierarchical Master-Slave SynchronizationHierarchical Despotism

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it appears how difficult is to lock all Administrations to a supranational timing reference

GPS is not accepted as first-choice primary reference by many national Administrations for political reasons

national synchronous HMS networks are plesiochronous in relation to the others

Mixed Plesiochronous/Synchronous NetworksIndependent Despotic States

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Synchronization NetworkStandard Architectures

ITU-T, ETSI, ANSI

all based on the hierarchical master-slave strategy (HMS)

at level 0one (or more, for reliability) network master clock generates the network reference signal, by running in autonomous mode

at lower levels 1, 2, etc.network slave clocks

are synchronized by the signals coming from the upper levelsynchronize the clocks at lower levels

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Primary Reference Clock (PRC)network master clock: autonomous clock or based on GPS/LORAN-C

Synchronization Supply Unit (SSU) functionrepresents the building clock (network slave clock)accepts synchronization inputs from external sourcesfilters the timing signal derived from this selected sourcemay use an internal timing source (hold-over)distributes the filtered timing signal to other elements within the nodephysical implementation: Stand-Alone Synchronization Equipment (SASE)

SDH Equipment Clock (SEC)

ITU-T/ETSI Reference Architecture

Clock Types in Synchronization Networks

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logical star topology centered on the SSU

within the node, all network element clocks are synchronized by the SSU

short-distance links

ITU-T G.703 signals 2.048 Mb/s2.048 MHz


Intra-Node Timing Distribution within nodes containing a SSU/SASE (e.g., PSTN offices)

SEC

SEC

SEC

SEC

SECSEC

SSU

node

bou

ndar

y

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The BITS/SASE Concept

the clock designated to time all other clocks in the officeITU-T/ETSI: Stand-Alone Synchronization Equipment (SASE)ANSI: Building Integrated Timing Supply (BITS)

some operators rely on clocks equipping large switches or DCXs for the BITS/SSU function, but good practice suggests using dedicated equipment

BITS/SASE should receive two or more references from other locations

intra-node timing distribution dedicated E1/DS1 signals at 2.048/1.544 Mb/s (ITU-T G.703)analog sine-wave 2048 kHz signal (ITU-T G.703)Clock Distribution Unit and Synchronous Clock Insertion Unit (AT&T)other (1544 kHz, 8 kHz, Composite Clock 64 kHz + 8 kHz in USA etc.)

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tree topology

standard HMS architecture

timing is transferred from one node to another along synchronization trails

the facilities of PDH/SDH transmission networks can be usedsynchronization trails may contain SECs


Inter-Node Timing Distribution among nodes containing a SSU/SASE

SSU SSU SSU SSU

PRC

SSU SSU

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up to N=20 SECs cascaded between any two SSUs

up to K=10 SSUs in one chain

total number of SECs in one chain limited to 60


Synchronization Network Reference Chain

PRC SSU SSU SSU

N SECs

1 K-1 K

N SECs N SECs N SECs

transit node transit node transit or local node

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Primary Reference Source (PRS) (analogous to PRC)frequency accuracy better than 1×1e-11GPS or LORAN-CStratum-1 clock (e.g., Cesium-beam atomic clock)

Stratum-2 clock (analogous to transit-node SASE)frequency accuracy better than 1.6×1e-8

Stratum-3 clock (analogous to local-node SASE)frequency accuracy better than 4.6×1e-6Stratum-3E clock (specific for SONET networks with improved short-term stability)

Stratum-4 e Stratum-4E clock (specific for customer-premises equipment)frequency accuracy better than 3.2×1e-5

ANSI Reference Architecture

Clock Hierarchy Based on Performance Levels: Strata

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clocks are duplicated and can recover timing from at least two alternate diversely-routed synchronization trails

clocks recover timing only from clocks of upper or equal level

a priority scheme must be established to select the reference in case of fault

switching criteria:hard failure detection

LOS, AIS, LOF, Ex-BER, LOPsoft failure detection

frequency offsetout-of-mask MTIE/TDEV

Synchronization Network Protection

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Synchronization Status Messages (SSM)

defined by ITU-T, ETSI and ANSI

SSMs are quality-markers embedded within digital signals that are used as synchronization sources

the originating node declares the quality of the synchronization source to which its signal is traceable

SSMs allow clocks to select the best synchronization source (i.e., that one declaring the best quality) among the available references according to a priority scheme

their main purpose is to avoid timing loops

compatible with most network topologiespoint-to-point, linear, mesh or ring topologies

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SSM Defined by ITU-T/ETSI

0000 Quality unknown0010 PRC (ITU-T Rec. G.811)0100 SASE transit node clock (ITU-T Rec. G.812)1000 SASE local node clock (ITU-T Rec. G.812)1011 Synchronous Equipment Timing Source (SETS)

(ITU-T Rec. G.813)1111 Do not use for synchronization

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Transmission of SSM

on PDH systemstransport via E1 signal (2.048 Mb/s)SSMs are inserted in one of TS0 bits 4-8 of odd frames (without alignment word): bit Sa4, Sa5, Sa6, Sa7, Sa8

usually, the bit Sa4 is used over a multiframe of4 basic frames A1 A1 A1 A2 A2 A2 J0

B1

D1 D2 D3

F1E1

AU pointer

B2 B2 B2 K1 K2

D4 D5 D6

D7 D8 D9

D10 D11 D12

S1 Z1 Z1 Z2 Z2 M1 E2

∆ ∆∆∆

∆∆RS

OH

MS

OH

on SDH systemstransport via STM-NSSMs are inserted in bits 5-8 of byte S1 within MSOH

Network Syncronization

Documents

distinguished

etsi reference

synchronization

pdh transmission

point timing

digital exchange

timing signal

digital signals