Network On Chip Cache Network On Chip Cache Coherency Coherency Final presentation – Part A Final presentation – Part A Students: Students: Zemer Tzach Zemer Tzach Kalifon Ethan Kalifon Ethan Instructor: Instructor: Walter Isaschar Walter Isaschar Spring 2008 Spring 2008
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Network On Chip Cache Coherency Final presentation – Part A Students: Zemer Tzach Kalifon Ethan Kalifon…
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Network On Chip Network On Chip Cache CoherencyCache CoherencyFinal presentation – Part AFinal presentation – Part A
Latency of the router is 2 cycles.Throughput of the router is 1 flit per cycle.System’s clock frequency is 100 [MHz].Packets can be routed simultaneously.Packets can by-pass each other.
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Cross TransmitCross Transmit
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Routing two packets simultaneously: port 0 to port 2 and port 3 to port 2.
Traffic avoidance by using VCTraffic avoidance by using VC
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First packet from port 0 to port 1 get blocked in output port.Packet from port 3 to port 1 by-pass it.
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Demonstration DiagramDemonstration Diagram
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General DescriptionGeneral Description
Dummy units transmit packets.Destination is being set by the switch-
buttons.The Dummy port start transmitting
according to its push-button.
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Project Schedule Project Schedule (1(1stst Semester) Semester)Familiarize with design tools – 3 weeks.Familiarize with VirtexII Pro FPGA (application