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Timing Issues and Clock Distribution
Lecture 1018-322 Fall 2003
Textbook: [Sections 7.5, 10.1, 10.3]
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Overview
Timing issues & clock distribution`System Performance Determination`Pipelining`Clock skew. Register timing`Counter clock skew
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Review: Register Timing
Prentice Hall 1995clk-to-Q (propagation) delay (tpFF)
hold time
setup time
Unstable data
cycle time
clk
Q
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Sequential Systems: The Big Picture
PrimaryInputs
PrimaryOutputsCombinational
Logic
Next State
Current State
MemoryElements
(Registers)Clock
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Maximum Clock Frequency
F
F
s
LOGIC
tp,comb
Speed of the sequential machine (how fast can this machine be clocked)
f = 1/T (clock frequency) Example: tp ~ 100ns => 10MHz (limit on performance)
tp,FF + tp,comb + tsetup < T
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Setup Time
Required time for input to be stableBEFORE CLOCK EDGE
Comb.Logic
Data stable herebefore clock here
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Setup Time Fix
Data
This violation can be fixed by stretching the clock cycle
OK
Data
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Setup Time Fix 2
Data
OR by accelerating the combinational logic
OK
Data
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Hold Time
Required time for input to be stableAFTER CLOCK EDGE
Comb.Logic
Data stable hereafter clock here
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Hold Time Violations
Prop Delay: 1 ns Hold Time: 2 ns
Hold time violations are caused by short pathsCannot be fixed by slowing down the clock!!!
Fixed by slowing down fast paths
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Timing Analysis
Look for longest path: clock speed Look for shortest paths: check hold time
Static Timing Analysis:`Attempt to determine longest/shortest path from schematic`Difficult problem
Know the delay of logic elements, but cannot easily reason aboutthe entire design
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False Paths
Example: #4#3
#2 #3
Solutions:SimulationFalse Path Analysis
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Speeding up System Performance: Pipelining
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Non-pipelined version Pipelined version
tp,comb
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How Good Is This?
Tmin,pipe = tp,reg + max(tp,ADD,tp,abs,tp,log ) + tsetup,reg Pipelining is used to implement high-performance data-paths Adding extra pipeline stages only makes sense up to a certain point
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Pipelined version
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Overview
Timing issues & clock distribution9 System Performance Determination9 Pipelining`Clock skew. Register timing`Counter clock skew
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Synchronous Pipelined Data-Path: Clock Skew
Clock Rates as High as 1 GHz in CMOS!
CL1 R1 CL2 R2 CL3 R3Out
t t t
tl,mintl,max
tr,mintr,max
ti
Clock Edge Timing Depends upon Position
A clock line behaves as a distributed RC line
Each register sees a localclock time depending on their distance from the clock source -> clock skew
= t t (> 0 or
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Constraints on Skew
R1 R2
tr,min + tl,min + ti
(a) Race between clock and data.
t t = t +
dataearliest time
If the local clock of R2 is delayed w.r.t. R1, it might happen that the inputs of R2 change before the previous data is latched -> race
tr,min + ti + tl,min
R1 R2
+ T
tr,max + tl,max + ti
(b) Data should be stable before clock pulse is applied.
t t + T =
data
t + T +
worst-case
The correct input data is stable at R2 after the worst-case propagation delay. The clock period must be large enough for the computations to settle.
T tr,max + ti + tl,max -
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Clock Constraints in Edge-Triggered Logic
tr min, ti tl min,+T r max, ti tl max, +
+
+t
(1)
(2)
Maximum Clock Skew Determined by Minimum Delay between Latches (condition 1)Minimum Clock Period Determined by Maximum Delay between Latches (condition 2)
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Positive and Negative Skew
R R RData
The clock is routed in the same direction as data
The skew has to satisfy (1) If it violates (1), then the circuit malfunction independently of the clock period Clock period decreases!!!
(a) Positive skew
CL CLCL
R R RData
(b) Negative skewThe clock is routed in the opposite direction of data (1) is satisfied implicitly. The circuit operates correctly independently of the skew Clock period increases by | |
CL CLCL
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Overview
Timing issues & clock distribution9 Pipelining9 Clock skew. Register timing`Counter clock skew
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Countering Clock Skew
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Clock Distribution
Positive Skew
Negative Skew
Data and Clock Routing
Goal: clock skew between registers is bounded!(What matters is the relative skew between communicating registers.)
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Clock Distribution: H-Trees
clk
Every branch sees the same wire length and capacitance The clock skew is theoretically zero The sub-blocks should be small enough s.t. the skew within the block is tolerable It is essential to consider clock distribution early in the design process
Clock distribution is a major design problem!
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Clock Network with Distributed Buffering
Module
Module
Module
Module
Module
Module
CLOCK
main clock driver
secondary clock drivers
Reduces absolute delay, and makes Power-Down easierSensitive to variations in Buffer Delay
Local Area
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DEC Alpha 21164
Clock Drivers
9.3 M Transistors, 4 metal layers, 0.55mClock Freq: 300 MHzClock Load: 3.75 nFPower in Clock = 20W (out of 50W)Two Level Clock Distribution:
oSingle 6-stage driver at centeroSecondary buffers drive left and right side
o Max clock skew less than 100psecoRouting the clock in the opposite directionoProper timing
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Clock Skew in Alpha
Clock driver
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Timing & Race Conditions: Example
AB
SumCoutCin
AB
SumCoutCin
AB
SumCoutCin
32-bit reg
32-bit reg
vv
32-bit adder
R1
R2
clk driver 150
300fF
SourceDestination
32-bit reg
v
R5
32-bit reg
v
R4
32-bit reg
v
R3
~1mm wire 200, 100fF
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Example (contd)
150 200
600fF 50fF 50fF 900fF
model
t = 0.69 (150) (650) = 67pst = 0.69 [(150) (650) + (150 + 200)(950)] = 297ps = t t = 230ps
Find the skew between the source register clock () and the destination ()
tr,min + ti + tl,min condition (1)thold + tclk-Q + tsum100 + 230 50 + 300 TRUE => No race problem
Check race condition
T tr,max + ti + tl,max - condition (2)T tclk-Q + 31 tcarry + tsum - + tsetupT 50 + 31(250) + 300 230 + 150 => T 8.2 nsFind minimum clock period
Timing Issues and Clock DistributionOverviewReview: Register TimingSequential Systems: The Big PictureMaximum Clock FrequencySetup TimeSetup Time FixSetup Time Fix 2Hold TimeHold Time ViolationsTiming AnalysisFalse PathsSpeeding up System Performance: PipeliningHow Good Is This?OverviewSynchronous Pipelined Data-Path: Clock SkewConstraints on SkewClock Constraints in Edge-Triggered LogicPositive and Negative SkewOverviewCountering Clock SkewClock Distribution: H-TreesClock Network with Distributed BufferingDEC Alpha 21164Clock Skew in AlphaTiming & Race Conditions: ExampleExample (contd)
