NCP1342 - Quasi-Resonant Flyback Controller, High Frequency · 2020-03-02 · mode to manage the power delivery while minimizing acoustic noise. To ensure light load performance with
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NCP1342The NCP1342 is a highly integrated quasi−resonant flyback
controller suitable for designing high−performance off−line powerconverters. With an integrated active X2 capacitor discharge feature,the NCP1342 can enable no−load power consumption below 30 mW.
The NCP1342 features a proprietary valley−lockout circuitry,ensuring stable valley switching. This system works down to the 6th
valley and transitions to frequency foldback mode to reduce switchinglosses. As the load decreases further, the NCP1342 enters quiet−skipmode to manage the power delivery while minimizing acoustic noise.
To ensure light load performance with high frequency designs, theNCP1342 incorporates Rapid Frequency Foldback with MinimumPeak Current Modulation to reduce the switching frequency quickly.To help ensure converter ruggedness, the NCP1342 implementsseveral key protective features such as internal brownout detection, anon−dissipative Over Power Protection (OPP) for constant maximumoutput power regardless of input voltage, a latched overvoltage andNTC−ready overtemperature protection through a dedicated pin, andline removal detection to safely discharge the X2 capacitors when theac line is removed.
Features• Integrated High−Voltage Startup Circuit with Brownout Detection
• Integrated X2 Capacitor Discharge Capability
• Wide VCC Range from 9 V to 28 V
• 28 V VCC Overvoltage Protection
• Abnormal Overcurrent Fault Protection for Winding Short Circuit orSaturation Detection
• Internal Temperature Shutdown
• Valley Switching Operation with Valley−Lockout for Noise−FreeOperation
• Frequency Foldback with 25 kHz Minimum Frequency Clamp forIncreased Efficiency at Light Loads
• Rapid Frequency Foldback for Fast Reduction of SwitchingFrequency at Light Loads
• Skip Mode with Quiet−Skip Technology for Highest PerformanceDuring Light Loads
• Minimized Current Consumption for No Load Power Below 30 mW
• Frequency Jittering for Reduced EMI Signature
• Latching or Auto−Recovery Timer−Based Overload Protection
• Adjustable Overpower Protection (OPP)
• Adjustable Maximum Frequency Clamp
• Fault Pin for Severe Fault Conditions, NTC Compatible for OTP
• 4 ms Soft−Start Timer
PIN CONNECTIONS
(Top Views)
SOIC−9 NBD SUFFIX
CASE 751BP
www.onsemi.com
See detailed ordering and shipping information on page 3 ofthis data sheet.
1 1 Fault The controller enters fault mode if the voltage on this pin is pulled above or below the faultthresholds. A precise pull up current source allows direct interface with an NTC thermistor.
− 2 FMAX A resistor to ground sets the value for the maximum switching frequency clamp. If this pin ispulled above 4 V, the maximum frequency clamp is disabled.
2 3 FB Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.
3 4 ZCD/OPP A resistor divider from the auxiliary winding to this pin provides input to the demagnetization de-tection comparator and sets the OPP compensation level.
4 5 CS Input to the cycle−by−cycle current limit comparator.
5 6 GND Ground reference.
6 7 DRV This is the drive pin of the circuit. The DRV high−current capability (−0.5 /+0.8 A) makes it suit-able to effectively drive high gate charge power MOSFETs.
7 8 VCC This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 17 V andturns off when VCC goes below 9 V (typical values). After start−up, the operating range is 9 V upto 28 V.
− 9 N/C Removed for creepage distance.
8 10 HV This pin is the input for the high voltage startup and brownout detection circuits. It also containsthe line removal detection circuit to safely discharge the X2 capacitors when the line is removed.
ESD CapabilityHuman Body Model per JEDEC Standard JESD22−A114F (All pins except HV)Human Body Model per JEDEC Standard JESD22−A114F (HV Pin)Charge Device Model per JEDEC Standard JESD22−C101F
Latch−Up Protection per JEDEC Standard JESD78E
20008001000±100
VVV
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. Maximum driver voltage is limited by the driver clamp voltage, VDRV(high), when VCC exceeds the driver clamp voltage. Otherwise, the
Characteristics Conditions Symbol Min Typ Max Unit
START−UP AND SUPPLY CIRCUITS
Supply VoltageStartup ThresholdDischarge Voltage During Line RemovalMinimum Operating VoltageOperating HysteresisInternal Latch / Logic Reset LevelTransition from Istart1 to Istart2
Valley ThresholdsTransition from 1st to 2nd valleyTransition from 2nd to 3rd valleyTransition from 3rd to 4th valleyTransition from 4th to 5th valleyTransition from 5th to 6th valleyTransition from 6th to 5th valleyTransition from 5th to 4th valleyTransition from 4th to 3rd valleyTransition from 3rd to 2nd valleyTransition from 2nd to 1st valley
The NCP1342 implements a quasi−resonant flybackconverter utilizing current−mode architecture where theswitch−off event is dictated by the peak current. This IC isan ideal candidate where low parts count and costeffectiveness are the key parameters, particularly in ac−dcadapters, open−frame power supplies, etc. The NCP1342incorporates all the necessary components normally neededin modern power supply designs, bringing severalenhancements such as non−dissipative overpowerprotection (OPP), brownout protection, and frequencyreduction management for optimized efficiency over theentire power range. Accounting for the needs of extremelylow standby power requirements, the controller featuresminimized current consumption and includes an automaticX2 capacitor discharge circuit that eliminates the need toinstall power−consuming resistors across the X2 inputcapacitors.• High−Voltage Start−Up Circuit: Low standby power
consumption cannot be obtained with the classicresistive start−up circuit. The NCP1342 incorporates ahigh−voltage current source to provide the necessarycurrent during start−up and then turns off during normaloperation.
• Internal Brownout Protection: The ac input voltage issensed via the high−voltage pin. When this voltage istoo low, the NCP1342 stops switching. No restartattempt is made until the ac input voltage is back withinits normal range.
• X2−Capacitor Discharge Circuitry: Per theIEC60950 standard, the time constant of the X2 inputcapacitors and their associated discharge resistors mustbe less than 1 s in order to avoid electrical shock whenthe user unplugs the power supply and inadvertentlytouches the ac input cord terminals. By providing anautomatic means to discharge the X2 capacitors, theNCP1342 eliminates the need to install X2 dischargeresistors, thus reducing power consumption.
• Quasi−Resonant, Current−Mode Operation:Quasi−Resonant (QR) mode is a highly efficient modeof operation where the MOSFET turn−on issynchronized with the point where its drain−sourcevoltage is at the minimum (valley). A drawback of thismode of operation is that the operating frequency isinversely proportional to the system load. TheNCP1342 incorporates a valley lockout (VLO) andfrequency foldback technique to eliminate thisdrawback, thus maximizing the efficiency over theentire power range.
• Valley Lockout: In order to limit the maximumfrequency while remaining in QR mode, one wouldtraditionally use a frequency clamp. Unfortunately, thiscan cause the controller to jump back and forth betweentwo different valleys, which is often undesirable. The
NCP1342 patented VLO circuitry solves this issue bydetermining the operating valley based on the systemload, and locking out other valleys unless a significantchange in load occurs.
• Rapid Frequency Foldback: As the load continues todecrease, it becomes beneficial to reduce the switchingfrequency. When the load is light enough, the NCP1342enters rapid frequency foldback mode. During thismode, the minimum peak current is limited anddead−time is added to the switching cycle, thusreducing the frequency and switching operation todiscontinuous conduction mode (DCM). Dead−timecontinues to be added until skip mode is reached, or theswitching frequency reaches its minimum level of 25kHz.
• Minimum Peak Current Modulation (MPCM): Inorder to reduce the switching frequency even faster (forhigh frequency designs), the NCP1342 uses MPCM toincrease the minimum peak current during frequencyfoldback. It also reduces the minimum peak currentgradually as the load decreases to ensure optimum skipmode entry.
• Skip Mode: To further improve light or no−load powerconsumption while avoiding audible noise, theNCP1342 enters skip mode when the operatingfrequency reaches its minimum value. To avoidacoustic noise, the circuit prevents the switchingfrequency from decaying below 25 kHz. This allowsregulation via bursts of pulses at 25 kHz or greaterinstead of operating in the audible range.
• Quiet−Skip: To further reduce acoustic noise, theNCP1342 incorporates a novel circuit to prevent theskip mode burst period from entering the audible rangeas well.
• Internal OPP: In order to limit power delivery at highline, a scaled version of the negative voltage present onthe auxiliary winding during the on−time is routed tothe ZCD/OPP pin. This provides the designer with asimple and non−dissipative means to reduce themaximum power capability as the bulk voltageincreases.
• Frequency Jittering: In order to reduce the EMIsignature, a low frequency triangular voltage waveformis added to the input of the PWM comparator. Thishelps by spreading out the energy peaks during noiseanalysis.
• Internal Soft−Start: The NCP1342 includes a 4 mssoft−start to prevent the main power switch from beingoverly stressed during start−up. Soft−start is activatedeach time a new startup sequence occurs or duringauto−recovery mode.
• Dedicated Fault Input: The NCP1342 includes adedicated fault input. It can be used to sense anovervoltage condition and latch off the controller bypulling the pin above the overvoltage protection (OVP)threshold. The controller is also disabled if the Fault pinis pulled below the overtemperature protection (OTP)threshold. The OTP threshold is configured for use witha NTC thermistor.
• Overload/Short−Circuit Protection: The NCP1342implements overload protection by limiting themaximum time duration for operation during overloadconditions. The overload timer operates whenever themaximum peak current is reached. In addition to this,special circuitry is included to prevent operation inCCM during extreme overloads, such as an outputshort−circuit.
• Maximum Frequency Clamp: The 9−pin version ofNCP1342 includes a maximum frequency clamp. The
clamp can be adjusted via an external resistor from theFMAX Pin to ground. It can also be disabled by pullingthe FMAX pin above 4 V.
HIGH VOLTAGE START−UPThe NCP1342 contains a multi−functional high voltage
(HV) pin. While the primary purpose of this pin is to reducestandby power while maintaining a fast start−up time, it alsoincorporates brownout detection and line removal detection.
The HV pin must be connected directly to the ac line inorder for the X2 discharge circuit to function correctly. Lineand neutral should be diode “ORed” before connecting to theHV pin as shown in Figure 4. The diodes prevent the pinvoltage from going below ground. A resistor in series withthe pin should be used to protect the pin during EMC or surgetesting. A low value resistor should be used (<5 k�) toreduce the voltage offset during start−up.
Figure 4. High−Voltage Input Connection
EMIACCON
HV
Controller
Start−up and VCC ManagementDuring start−up, the current source turns on and charges
the VCC capacitor with Istart2 (typically 6 mA). When Vccreaches VCC(on) (typically 16.0 V), the current source turnsoff. If the input voltage is not high enough to ensure a properstart−up (i.e. VHV has not reached VBO(start)), the controllerwill not start. VCC then begins to fall because the controllerbias current is at ICC2 (typically 1 mA) and the auxiliarysupply voltage is not present. When VCC falls to VCC(off)(typically 10.5 V), the current source turns back on andcharges VCC. This cycle repeats indefinitely until VHVreaches VBO(start). Once this occurs, the current sourceimmediately turns on and charges VCC to VCC(on), at whichpoint the controller starts (see Figure 6).
When VCC is brought below VCC(inhibit), the start−upcurrent is reduced to Istart1 (typically 0.5 mA). This limitspower dissipation on the device in the event that the VCC pinis shorted to ground. Once VCC rises back above VCC(inhibit),the start−up current returns to Istart2.
Once VCC reaches VCC(on), the controller is enabled andthe controller bias current increases to ICC3 (typically2.0 mA). However, the total bias current is greater than thisdue to the gate charge of the external switching MOSFET.The increase in ICC due to the MOSFET is calculated usingEquation 1.
�ICC � fsw � QG � 10−3 (eq. 1)
where �ICC is the increase in milliamps, fsw is the switchingfrequency in kilohertz and QG is the gate charge of theexternal MOSFET in nanocoulombs.
CVCC must be sized such that a VCC voltage greater thanVCC(off) is maintained while the auxiliary supply voltageincreases during start−up. If CVCC is too small, VCC will fallbelow VCC(off) and the controller will turn off before theauxiliary winding supplies the IC. The total ICC current afterthe controller is enabled (ICC3 plus �ICC) must beconsidered to correctly size CVCC.
DRIVERThe NCP1342 maximum supply voltage, VCC(MAX), is
28 V. Typical high−voltage MOSFETs have a maximumgate voltage rating of 20 V. The DRV pin incorporates anactive voltage clamp to limit the gate voltage on the externalMOSFETs. The DRV voltage clamp, VDRV(high) is typically12 V with a maximum limit of 14 V.
REGULATION CONTROL
Peak Current ControlThe NCP1342 is a peak current−mode controller, thus the
FB voltage sets the peak current flowing in the transformerand the MOSFET. This is achieved by sensing the MOSFETcurrent across a resistor and applying the resulting voltageramp to the non−inverting input of the PWM comparatorthrough the CS pin. The current limit threshold is set byapplying the FB voltage divided by KFB (typically 4) to theinverting input of the PWM comparator. When the currentsense voltage ramp exceeds this threshold, the output driveris turned off, however, the peak current is affected by severalfunctions (see Figure 7):
The peak current level is clamped during the soft−startphase. The setpoint is actually limited by a clamp levelramping from 0 to 0.8 V within 4 ms.
In addition to the PWM comparator, a dedicatedcomparator monitors the current sense voltage, and if itreaches the maximum value, VILIM (typically 800 mV), thegate driver is turned off and the overload timer is enabled.This occurs even if the limit imposed by the feedbackvoltage is higher than VILIM1. Due to the parasiticcapacitances of the MOSFET, a large voltage spike oftenappears on the CS Pin at turn−on. To prevent this spike fromfalsely triggering the current sense circuit, the current sensesignal is blanked for a short period of time, tLEB1 (typically275 ns), by a leading edge blanking (LEB) circuit. Figure 7shows the schematic of the current sense circuit.
The peak current is also limitied to a minimum level,VCS(MIN) (0.2 V, typically). This results in higher efficiencyat light loads by increasing the minimum energy deliveredper switching cycle, while reducing the overall number ofswitching cycles during light load.
Zero Current DetectionThe NCP1342 is a quasi−resonant (QR) flyback
controller. While the power switch turn−off is determined bythe peak current set by the feedback loop, the switch turn−onis determined by the transformer demagnetization. Thedemagnetization is detected by monitoring the transformerauxiliary winding voltage.
Turning on the power switch once the transformer isdemagnetized has the benefit of reduced switching losses.Once the transformer is demagnetized, the drain voltagestarts ringing at a frequency determined by the transformermagnetizing inductance and the drain lump capacitance,eventually settling at the input voltage. A QR flybackcontroller takes advantage of the drain voltage ringing andturns on the power switch at the drain voltage minimum or“valley” to reduce switching losses and electromagneticinterference (EMI).
As shown by Figure 13, a valley is detected once the ZCDpin voltage falls below the demagnetization threshold,VZCD(trig), typically 55 mV. The controller will either switchonce the valley is detected or increment the valley counter,depending on the FB voltage.
Overpower ProtectionThe average bulk capacitor voltage of the QR flyback
varies with the RMS line voltage. Thus, the maximumpower capability at high line can be much higher thandesired. An integrated overpower protection (OPP) circuitprovides a relatively constant output power limit across theinput voltage on the bulk capacitor, Vbulk. Since it is ahigh−voltage rail, directly measuring Vbulk will contributelosses in the sensing network that will greatly impact thestandby power consumption. The NCP1342 OPP circuitachieves this without the need for a high−voltage sensingnetwork, and is essentially lossless.
Since the auxiliary winding voltage during the powerswitch on time is a reflection of the input voltage scaled bythe primary to auxiliary winding turns ratio, NP:AUX (seeFigure 9), OPP is achieved by scaling down reflectedvoltage during the on−time and applying it to the ZCD pinas a negative voltage, VOPP. The voltage is scaled down bya resistor divider comprised of ROPPU and ROPPL. Themaximum internal current setpoint (VCS(OPP)) is simply thesum of VOPP and the peak current sense threshold, VILIM1.Figure 8 shows the schematic for the OPP circuit.
The adjusted peak current limit is calculated usingEquation 2. For example, a VOPP of −150 mV results in apeak current limit of 650 mV in NCP1342.
VCS(OPP) � VOPP � VILIM1 (eq. 2)
To ensure optimal zero−crossing detection, a diode isneeded to bypass ROPPU during the off−time. Equation 3 isused to calculate ROPPU and ROPPL.
RZCD � ROPPUROPPL
� �NP:AUX � Vbulk � VOPP
VOPP(eq. 3)
ROPPU is selected once a value is chosen for ROPPL.ROPPL is selected large enough such that enough voltage isavailable for the zero−crossing detection during theoff−time. It is recommended to have at least 8 V applied onthe ZCD pin for good detection. The maximum voltage isinternally clamped to VCC. The off−time voltage on the ZCDPin is given by Equation 4.
VZCD �ROPPL
RZCD � ROPPL� �VAUX � VF
� (eq. 4)
Where VAUX is the voltage across the auxiliary windingand VF is the DOPP forward voltage drop.
The ratio between RZCD and ROPPL is given byEquation 5. It is obtained by combining Equations 3 and 4.
RZCDROPPL
�VAUX � VF � VZCD
VZCD(eq. 5)
A design example is shown below:System Parameters:
VAUX � 18 V
VF � 0.6 V
NP:AUX � 0.18
The ratio between RZCD and ROPPL is calculated usingEquation 5 for a minimum VZCD of 8 V.
RZCDROPPL
�18 V � 0.6 V � 8 V
8 V� 1.2 k�
RZCD is arbitrarily set to 1 k�. ROPPL is also set to 1 k�because the ratio between the resistors is close to 1.
The NCP1342 maximum overpower compensation orpeak current setpoint reduction is 31.25% for a VOPP of−250 mV. We will use this value for the following example:
Substituting values in Equation 3 and solving for ROPPUwe obtain:
ROPPU � 271 � ROPPL � RZCD
ROPPU � 271 � 1 k�� 1 k� � 270 k�
RZCD � ROPPUROPPL
�0.18 � 370 V � (−0.25 V)
−0.25 V� 271
For optimum performance over temperature, it isrecommended to keep ROPPL below 3 k�.
Soft−StartSoft−start is achieved by ramping up an internal reference,
VSSTART, and comparing it to the current sense signal.VSSTART ramps up from 0 V once the controller initiallypowers up. The peak current setpoint is then limited by theVSSTART ramp resulting in a gradual increase of the switchcurrent during start−up. The soft−start duration, tSSTART, istypically 4 ms.
During startup, demagnetization phases are long anddifficult to detect since the auxiliary winding voltage is verysmall. In this condition, the 6 �s steady−state timeout isgenerally shorter than the inductor demagnetization period.If it is used to restart a switching cycle, it can cause operation
in CCM for several cycles until the voltage on the ZCD pinis high enough to prevent the timer from running. Therefore,a longer timeout period, ttout1 (typically 100 �s), is usedduring soft−start to prevent CCM operation.
Frequency JitteringIn order to help meet stringent EMI requirements, the
NCP1342 features frequency jittering to average the energypeaks over the EMI frequency range. As shown in Figure 10,the function consists of summing a triangular wave ofamplitude Vjitter and frequency fjitter with the CS signalimmediately before the PWM comparator. This current actsto modulate the on−time and hence the operation frequency.
Figure 10. Jitter Implementation
FB
VILIM1
CS LEB
KFBVjitter
RFB
VDD
VCS(MIN)
DRV Off
VOPP
Since the jittering function modulates the peak currentlevel, the FB signal will attempt to compensate for this effectin order to limit the output voltage ripple. Therefore, thebandwidth of the feedback loop must be well below the jitterfrequency, or the jitter function will be filtered by the loop.
Due to the minimum peak current, the effect of thejittering circuit will not be seen during frequency foldbackmode.
Maximum Frequency ClampAll 9−pin versions of the NCP1342 include an adjustable
maximum frequency clamp via an external resistor from theFMAX Pin to ground. It can also be disabled by pulling theFMAX pin above 4 V. The maximum frequency can beprogrammed using Equation 6, and is shown in Figure 11.
Valley Lockout OperationThe operating frequency of a traditional QR flyback
controller is inversely proportional to the system load. Inother words, a load reduction increases the operatingfrequency. A maximum frequency clamp can be useful tolimit the operating frequency range. However, when used byitself, such an approach often causes instabilities since whenthis clamp is active, the controller tends to jump (or hesitate)between two valleys, thus generating audible noise.
Instead, the NCP1342 also incorporates a patented valleylockout (VLO) circuitry to eliminate valley jumping. Once
a valley is selected, the controller stays locked in this valleyuntil the output power changes significantly. This techniqueextends the QR mode operation over a wider output powerrange while maintaining good efficiency and limiting themaximum operating frequency.
The operating valley (1st, 2nd, 3rd, 4th, 5th or 6th) isdetermined by the FB voltage. An internal counterincrements each time a valley is detected by the ZCD/OPPPin. Figure 12 shows a typical frequency characteristicobtainable at low line in a 65 W application.
0 20 40 600
2 104
x
4 104
x
6 104
x
8 104
x
1 105
x
Pout (W)
Fsw
(Hz)
1st2nd3rd4th5th6th
VCO
mode
1st2nd3rd4th5th6th
VCO
mode
Figure 12. Valley Lockout Frequency vs. Output Power
When an “n” valley is asserted by the valley selectioncircuitry, the controller is locked in this valley until the FBvoltage decreases to the lower threshold (“n+1” valleyactivates) or increases to the “n valley threshold” + 600 mV(“n−1” valley activates). The regulation loop adjusts the
peak current to deliver the necessary output power. Eachvalley selection comparator features a 600 mV hysteresisthat helps stabilize operation despite the FB voltage swingproduced by the regulation loop.
Table 7. VALLEY FB THRESHOLDS (typical values)
FB Falling FB Rising
1st to 2nd valley 1.400 V 2nd to 1st valley 2.000 V
2nd to 3rd valley 1.200 V 3rd to 2nd valley 1.800 V
3rd to 4th valley 1.100 V 4th to 3rd valley 1.700 V
4th to 5th valley 1.000 V 5th to 4th valley 1.600 V
5th to 6th valley 0.900 V 6th to 5th valley 1.500 V
Valley TimeoutIn case of extremely damped oscillations, the ZCD
comparator may not be able to detect the valleys. In thiscondition, drive pulses will stop while the controller waitsfor the next valley or ZCD event. The NCP1342 ensurescontinued operation by incorporating a maximum timeoutperiod after the last demagnetization detection. The timeout
signal acts as a substitute for the ZCD signal to the valleycounter. Figure 13 shows the valley timeout circuitschematic. The steady state timeout period, ttout2, is set at 6�s (typical) to limit the frequency step.
During startup, the voltage offset added by the OPP diode,DOPP, prevents the ZCD Comparator from accuratelydetecting the valleys. In this condition, the steady state
timeout period will be shorter than the inductordemagnetization period causing CCM operation. CCMoperation lasts for a few cycles until the voltage on the ZCDpin is high enough to detect the valleys. A longer timeoutperiod, ttout1, (typically 100 �s) is set during soft−start tolimit CCM operation.
In VLO operation, the number of timeout periods arecounted instead of valleys when the drain−source voltageoscillations are too damped to be detected. For example, if
the FB voltage sets VLO mode to turn on at the fifth valley,and the ZCD ringing is damped such that the ZCD circuit isonly able to detect:• Valleys 1 to 4: the circuit generates a DRV pulse 6 �s
(steady−state timeout delay) after the 4th valleydetection.
• Valleys 1 to 3: the timeout delay must run twice, andthe circuit generates a DRV pulse 12 �s after the 3rd
valley detection.
Figure 13. Valley Timeout Circuitry
Rapid Frequency Foldback with Minimum PeakCurrent Modulation (MPCM)
As the output load decreases (FB voltage decreases), thevalleys are incremented from 1 to 6. When the sixth valleyis reached and the FB voltage further decreases toVMPCM(entry) (800 mV typical), the controller enters MPCMand begins frequency foldback (FF). At this point, theminimum peak current is increased by VMPCM(delta)(400 mV typical). The increase in peak current serves toforce the switching frequency to a much lower value, thusimproving the efficiency at light loads. During this mode,the controller regulates the power delivery by modulatingthe switching frequency.
Once in frequency foldback mode, the controller reducesthe switching frequency by adding dead−time after the 6th
valley is detected. This dead−time increases as the FBvoltage decreases.
The dead−time circuit is designed to add 0 �s dead−timewhen VFB = 0.4 V and linearly increases the total dead−timeto tDT(MAX) (36 �s typical) as VFB falls down to 0.4 V. The
minimum frequency clamp prevents the switchingfrequency from dropping below 25 kHz to eliminate the riskof audible noise. Note that the dead−time is not added (it isblanked) until MPCM is engaged to ensure valley switchingprior to entering MPCM mode.
In addition to dead−time, the peak current setpoint islinearly reduced as VFB falls down to 0.4 V. This ensures thatthe peak current is not too high during the lightest loads, andhas the effect of reducing the skip entry power level.Figure 14 shows the MPCM with respect to the feedbackvoltage, while Figure 15 shows the VLO to FF operation.
To reduce the output power hysteresis between enteringand exiting MPCM, the exit threshold (VMPCM(exit)) is setslightly below the entry threshold (750 mV typical). A 1 mstimer, tMPCM, is engaged every time MPCM is entered orexited to prevent oscillations during the operating pointtransition. If at any time FB falls to skip mode, or rises to 5th
valley, MPCM will be immediately exited regardless oftMPCM.
Minimum Frequency Clamp and Skip ModeAs mentioned previously, the circuit prevents the
switching frequency from dropping below fMIN (25 kHztypical). When the switching cycle would be longer than40 �s, the circuit forces a new switching cycle. However, thefMIN clamp cannot generate a DRV pulse until thedemagnetization is completed. In other words, it will notcause operation in CCM.
Since the NCP1342 forces a minimum peak current and aminimum frequency, the power delivery cannot becontinuously controlled down to zero. Instead, the circuitstarts skipping pulses when the FB voltage drops below theskip level, Vskip, and recovers operation when VFB exceedsVskip + Vskip(HYS). This skip−mode method provides anefficient method of control during light loads.
Quiet−SkipTo further avoid acoustic noise, the circuit prevents the
burst frequency during skip mode from entering the audiblerange by limiting it to a maximum of 800 Hz. This isachieved via a timer (tquiet) that is activated duringQuiet−Skip. The start of the next burst cycle is preventeduntil this timer has expired.
As the output power decreases, the switching frequencydecreases. Once it hits 25 kHz, the skip−in threshold isreached and burst mode is entered − switching stops as soon
as the current drive pulses ends – it does not stopimmediately.
Once switching stops, FB will rise. As soon as FB crossesthe skip−exit threshold, drive pulses will resume, but thecontroller remains in burst mode. At this point, a 1.25 mstimer, tquiet, is started together with a count−to−3 counter. The next time the FB voltage drops below the skip−inthreshold, drive pulses stop at the end of the current pulse aslong as 3 drive pulses have been counted (if not, they do notstop until the end of the 3rd pulse). They are not allowed tostart again until the timer expires, even if the skip−exitthreshold is reached first. It is important to note that thetimer will not force the next cycle to begin – i.e. if the naturalskip frequency is such that skip−exit is reached after thetimer expires, the drive pulses will wait for the skip−exitthreshold.
This means that during no−load, there will be a minimumof 3 drive pulses, and the burst−cycle period will likely bemuch longer than 1.25 ms. This operation helps to improveefficiency at no−load conditions.
In order to exit burst mode, the FB voltage must rise higherthan 1 V. If this occurs before tquiet expires, the drive pulseswill resume immediately – i.e. the controller won’t wait forthe timer to expire. Figure 16 provides an example of howQuiet−Skip works.
The NCP1342 contains three separate fault modes.Depending on the type of fault, the device will either latchoff, restart when the fault is removed, or resume operationafter the auto−recovery timer expires.
Latching FaultsSome faults will cause the NCP1342 to latch off. These
include the abnormal OCP (AOCP), VCC OVP, and the
external latch input. When the NCP1342 detects a latchingfault, the driver is immediately disabled. The operationduring a latching fault is identical to that of a non−latchingfault except the controller will not attempt to restart at thenext VCC(on), even if the fault is removed. In order to clearthe latch and resume normal operation, VCC must first beallowed to drop below VCC(reset) or a line removal eventmust be detected. This operation is shown in Figure 17.
Non−Latching FaultsWhen the NCP1342 detects a non−latching fault
(brownout or thermal shutdown), the drivers are disabled,and VCC falls towards VCC(off) due to the IC internal currentconsumption. Once VCC reaches VCC(off), the HV currentsource turns on and CVCC begins to charge towards VCC(on).When VCC, reaches VCC(on), the cycle repeats until the faultis removed. Once the fault is removed, the NCP1342 is
re−enabled when VCC reaches VCC(on) according to theinitial power−on sequence, provided VHV is aboveVBO(start). This operation is shown in Figure 18. When VHVis reaches VBO(start), VCC immediately charges to VCC(on).If VCC is already above VCC(on) when the fault is removed,the controller will start immediately as long as VHV is aboveVBO(start).
Auto−recovery Timer FaultsSome faults faults cause the NCP1342 auto−recovery
timer to run. If an auto−recovery fault is detected, the gatedrive is disabled and the auto−recovery timer, tautorec(typically 1.2 s), starts. While the auto−recovery timer is
running, the HV current source turns on and off to maintainVcc between Vcc(off) and Vcc(on). Once the auto−recoverytimer expires, the controller will attempt to start normally atthe next VCC(on) provided VHV is above VBO(start). Thisoperation is shown in Figure 19.
Brownout ProtectionA timer is enabled once VHV drops below its disable
threshold, VBO(stop) (typically 99 V). The controller isdisabled if VHV doesn’t exceed VBO(stop) before thebrownout timer, tBO (typically 54 ms), expires. The timer isset long enough to ignore a two cycle dropout. The timerstarts counting once VHV drops below VBO(stop).
Figure 20 shows the brownout detector waveforms duringa brownout.
When a brownout is detected, the controller stopsswitching and enters non−latching fault mode (seeFigure 18). The HV current source alternatively turns on andoff to maintain VCC between VCC(on) and VCC(off) until theinput voltage is back above VBO(start).
VCC(on)
VCC(off )
DRV
VCC
BrownoutTimer
VHV
VBO(stop )
VBO(start )
time
time
time
time
tdelay (start )
StartsCharging
Immediately
Brownoutdetected
Restarts atnext V CC(on)
FaultCleared
Figure 20. Operation During Brownout
Line Removal Detection and X2 Capacitor DischargeSafety agency standards require the input filter capacitors
to be discharged once the ac line voltage is removed. Aresistor network is the most common method to meet thisrequirement. Unfortunately, the resistor network consumespower across all operating modes and it is a majorcontributor of input power losses during light−load andno−load conditions.
The NCP1342 eliminates the need for external dischargeresistors by integrating active input filter capacitor
discharge circuitry. A novel approach is used to reconfigurethe high voltage startup circuit to discharge the input filtercapacitors upon removal of the ac line voltage. The lineremoval detection circuitry is always active to ensure safetycompliance.
The line removal is detected by digitally sampling thevoltage present at the HV pin, and monitoring the slope.
A timer, tline(removal) (typically 100 ms), is used to detectwhen the slope of the input signal is negative or below theresolution level. The timer is reset any time a positive slope
is detected. Once the timer expires, a line removal conditionis acknowledged initiating an X2 capacitor discharge cycle,and the controller is disabled.
If VCC is above VCC(on), it is first discharged to VCC(on).A second timer, tline(discharge) (typically 32 ms), is used forthe time limiting of the discharge phase to protect the deviceagainst overheating. Once the discharge phase is complete,tline(discharge) is reused while the device checks to see if theline voltage is reapplied. During the discharge phase, if VCC
drops to VCC(on), it is quickly recharged to VCC(X2_reg). Thedischarging process is cyclic and continues until the ac lineis detected again or the voltage across the X2 capacitor islower than VHV(discharge) (30 V maximum). This featureallows the device to discharge large X2 capacitors in theinput line filter to a safe level.
It is important to note that the HV pin cannot beconnected to any dc voltage due to this feature, i.e.directly to the bulk capacitor.
An over temperature protection block monitors thejunction temperature during the discharge process to avoidthermal runaway, in particular during open/short pins safetytests. Please note that the X2 discharge capability is alsoactive at all times, including off−mode and before thecontroller actually starts to pulse (e.g. if the user unplugs theconverter during the start−up sequence).
Dedicated Fault InputThe NCP1342 includes a dedicated fault input accessible
via the Fault pin (8−pin and 9−pin versions only). Thecontroller can be latched by pulling up the pin above theupper fault threshold, VFault(OVP) (typically 3.0 V). Thecontroller is disabled if the Fault pin voltage is pulled below
the lower fault threshold, VFault(OTP_in) (typically 0.4 V).The lower threshold is normally used for detecting anovertemperature fault. The controller operates normallywhile the Fault pin voltage is maintained within the upperand lower fault thresholds. Figure 23 shows the architectureof the Fault input.
The Fault input signal is filtered to prevent noise fromtriggering the fault detectors. Upper and lower fault detectorblanking delays, tdelay(OVP) and tdelay(OTP),are bothtypically 30 �s. A fault is detected if the fault condition isasserted for a period longer than the blanking delay.
OVPAn active clamp prevents the Fault pin voltage from
reaching the upper latch threshold if the pin is open. To reachthe upper threshold, the external pull−up current has to behigher than the pull−down capability of the clamp (set byRFault(clamp) at VFault(clamp)), i.e., approximately 1 mA.
The upper fault threshold is intended to be used for anovervoltage fault using a zener diode and a resistor in seriesfrom the auxiliary winding voltage. The controller is latchedonce VFault exceeds VFault(OVP).
Once the controller is latched, it follows the behavior ofa latching fault according to Figure 17 and is only reset ifVCC is reduced to VCC(reset), or X2 discharge is activated. Inthe typical application these conditions occur only if the acvoltage is removed from the system.
OTPThe lower fault threshold is intended to be used to detect
an overtemperature fault using an NTC thermistor. A pull upcurrent source, IFault(OTP) (typically 45.0 �A), generates a
voltage drop across the thermistor. The resistance of theNTC thermistor decreases at higher temperatures resultingin a lower voltage across the thermistor. The controllerdetects a fault once the thermistor voltage drops belowVFault(OTP_in).
The controller bias current is reduced during power up bydisabling most of the circuit blocks including IFault(OTP).This current source is enabled once VCC reaches VCC(on). Afilter capacitor is typically connected between the Fault andGND pins. This will result in a delay before VFault reachesits steady state value once IFault(OTP) is enabled. Therefore,the lower fault comparator (i.e. overtemperature detection)is ignored during soft−start.
Version A latches off the controller after anovertemperature fault is detected according to Figure 17. InVersion B, the controller is re−enabled once the fault isremoved such that VFault increases above VFault(OTP_out),the auto−recovery timer expires, and VCC reaches VCC(on)as shown in Figure 19.
Overload ProtectionThe overload timer integrates the duration of the overload
fault. That is, the timer count increases while the fault ispresent and reduces its count once it is removed. Theoverload timer duration, tOVLD, is typically 160 ms. Whenthe overload timer expires, the controller detects an overloadcondition does one of the following:
• The controller latches off (version A) or
• Enters a safe, low duty−ratio auto−recovery mode(version B).
Figure 24 shows the overload circuit schematic, whileFigure 25 and Figure 26 show operating waveforms forlatched and auto−recovery overload conditions.
Abnormal Overcurrent Protection (AOCP)Under some severe fault conditions, like a winding
short−circuit, the switch current can increase very rapidlyduring the on−time. The current sense signal significantlyexceeds VILIM1, but because the current sense signal isblanked by the LEB circuit during the switch turn−on, thepower switch current can become huge and cause severesystem damage.
The NCP1342 protects against this fault by adding anadditional comparator for Abnormal Overcurrent Faultdetection. The current sense signal is blanked with a shorterLEB duration, tLEB2, typically 125 ns, before applying it tothe Abnormal Overcurrent Fault Comparator. The voltagethreshold of the comparator, VILIM2, typically 1.2 V, is set50% higher than VILIM1, to avoid interference with normaloperation. Four consecutive Abnormal Overcurrent faultscause the controller to enter latch mode. The count to 4provides noise immunity during surge testing. The counteris reset each time a DRV pulse occurs without activating theFault Overcurrent Comparator.
Current Sense Pin Failure ProtectionA 1 �A (typically) pull−up current source, ICS, pulls up the
CS pin to disable the controller if the pin is left open.Additionally, the maximum on−time, ton(MAX) (32 �s
typically), prevents the MOSFET from staying onpermanently if the CS Pin is shorted to GND.
Output Short Circuit ProtectionDuring an output short−circuit, there is not enough
voltage across the secondary winding to demagnetize the
core. Due to the valley timeout feature of the controller, theflux level will quickly walk up until the core saturates. Thiscan cause excessive stress on the primary MOSFET andsecondary diode. This is not a problem for the NCP1342,however, because the valley timeout timer is disabled whilethe ZCD Pin voltage is above the arming threshold. Since theleakage energy is high enough to arm the ZCD trigger, thetimeout timer is disabled and the next drive pulse is delayeduntil demagnetization occurs.
VCC Overvoltage ProtectionAn additional comparator on the VCC pin monitors the
VCC voltage. If VCC exceeds VCC(OVP), the gate drive isdisabled and the NCP1342 follows the operation of alatching fault (see Figure 17).
Thermal ShutdownAn internal thermal shutdown circuit monitors the
junction temperature of the controller. The controller isdisabled if the junction temperature exceeds the thermalshutdown threshold, TSHDN (typically 140°C). When athermal shutdown fault is detected, the controller enters anon−latching fault mode as depicted in Figure 18. Thecontroller restarts at the next VCC(on) once the junctiontemperature drops below below TSHDN by the thermalshutdown hysteresis, TSHDN(HYS), typically 40°C.
The thermal shutdown is also cleared if VCC drops belowVCC(reset), or a line removal fault is detected. A new powerup sequence commences at the next VCC(on) once all thefaults are removed.
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSIONSHALL BE 0.10mm TOTAL IN EXCESS OF ’b’AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDEMOLD FLASH, PROTRUSIONS, OR GATEBURRS. MOLD FLASH, PROTRUSIONS, ORGATE BURRS SHALL NOT EXCEED 0.15mmPER SIDE. DIMENSIONS D AND E ARE DE-TERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERM-INED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCEFROM THE SEATING PLANE TO THE LOWESTPOINT ON THE PACKAGE BODY.
D
EH
A1A
DIM
D
MIN MAX
4.80 5.00
MILLIMETERS
E 3.80 4.00
A 1.25 1.75
b 0.31 0.51
e 1.00 BSC
A1 0.10 0.25A3 0.17 0.25
L 0.40 1.27
M 0 8
H 5.80 6.20
CM0.25
M
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DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
h 0.37 REF
L2 0.25 BSC
AC0.20
4 TIPS
TOP VIEW
C0.205 TIPS A-B D
C0.10 A-B
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C0.10 A-B
2X
e
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SIDE VIEW END VIEW
DETAIL A
6.50
9X 1.18
9X 0.58 1.00PITCH
RECOMMENDED
1
L
F
SEATINGPLANEC
L2 A3
DETAIL A
D
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