NCP1034 - PWM Buck Controller, Synchronous, 100 V · 13 OCIN 15 14 RT GND SOIC−16 D SUFFIX CASE 751B NCP1034D AWLYWWG A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week

DATA SHEETwww.onsemi.com

© Semiconductor Components Industries, LLC, 2015

August, 2021 − Rev. 141 Publication Order Number:

NCP1034/D

PWM Buck Controller,Synchronous, 100V

NCP1034

DescriptionThe NCP1034 is a high voltage PWM controller designed for high

performance synchronous Buck DC/DC applications with inputvoltages up to 100 V. The NCP1034 drives a pair of externalN−MOSFETs. The switching frequency is programmable from25 kHz up to 500 kHz allowing the flexibility to tune for efficiencyand size. A synchronization feature allows the switching frequency tobe set by an external source or output a synchronization signal tomultiple NCP1034 controllers. The output voltage can be preciselyregulated using the internally trimmed 1.25 V reference voltage forlow voltage applications. Protection features include userprogrammable undervoltage lockout and hiccup current limit.

Features• High Voltage Operating up to 100 V

• Programmable Switching Frequency up to 500 kHz

• 2 A Output Drive Capability

• Precision Reference Voltage (1.25 V)

• Programmable Soft−Start with Prebiased Load Capability

• Programmable Overcurrent Protection

• Programmable Undervoltage Protection

• Hiccup Current Limit Using MOSFET RDS(on) Sensing

• External Frequency Synchronization

• 16 Pin SOIC Package

• This is a Pb−Free Device

Applications• 48 V Non−Isolated DC−DC Converter

• Embedded Telecom Systems

• Networking and Computing Voltage Regulator

• Distributed Point of Load Power Architectures

• General High Voltage DC−DC Converters

1

2

3

4

5

6

7

8

16

12

11

10

9

(Top View)

SYNC

OCset

FB

Comp

SS/SD

PGND

LDRV

DRVCC

UVLO

VCC

VS

VB

HDRV

13 OCIN

15

14

RT

GND

SOIC−16D SUFFIX

CASE 751B

NCP1034DAWLYWWG

A = Assembly LocationWL = Wafer LotY = YearWW = Work WeekG = Pb−Free Package

MARKINGDIAGRAM

PIN CONNECTIONS

See detailed ordering and shipping information in the packagedimensions section on page 24 of this data sheet.

ORDERING INFORMATION

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Figure 1. Typical Application Circuit

12

5

15

4

16

1

14

10

11

13

7

6

2

3

R711k

R620k

C5

220nR53k9

VCC

SYNC

RT

UVLO

OCSET

GND

HDRV

VS

OCIN

LDRV

PGND

FB

COMP

SS/SD

C2

100n

C3

100n

D1

1N4148C4

100n

R4110k

VCC: 12 V

IC1NCP1034

8 9

DRVVCC VB

R34k7

C7

330p

C6

12n

R8

10k

VIN: 48 V

C1A2u2

C9

47�

C9B

47�

Q1NTD3055

Q2NTD24N06

L1

13�

R25k6

R116k9

R91k2

VOUT5 V @ 5 A, 200 kHz

C8

1n8

R10

10k

GND GND GND GND GND

GND

GND

GND

C1B2u2

C9C

47�

(For applications operatingat cold ambient tempera-tures refer to the soft−startsection on Page 15)

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Figure 2. Internal Block Diagram

Bia

sG

ener

ator

PO

R

1.25

V =

Vre

f

VC

C

GN

D

5V =

VB

IAS

Osc

illat

or

SY

NC Rt

Ct

Rt

Vcc

UV

LO

S RR

eset

Dom

Q

Hig

hV

olta

geLe

vel

Shi

ftC

ircui

t

UV

Det

ect

S RUV

Q

Vb

HD

rv

Vs

Drv

VC

C

LD

rv

PG

ND

Clk

DP

OR

0.3V

0.3V

SS

/SD

Com

p

Fb

1.25

V

25kP

OR

VB

IAS

20uA

1uA

64uA

Max

OC

P

VB

IAS

OC

in

Act

ive

Cla

mp

VB

IAS

Err

or A

mp

Err

orC

ompa

rato

rU

VD

etec

t

Del

ayLS

AC

ON

OC

set

AC

ON

Neg

ativ

eO

utpu

t

S RQ

OC

P

OC

P R

eset

SS

/SD

0.25

V

Vre

f

UV

LOV

ref

Iocs

et

0.04

10x

Iocs

et

AC

ON

FAULT

FAU

LTQ

PW

M

FAU

LT

MK

O35

0ns

PW

M

Low

UV

LO

Pos

itive

Cur

rent

OC

P

Low

UV

LO

R

OC

P

0.22

5x Io

cset

Pos

itive

Cur

rent

SS

/SD

TO

NM

INLi

mit

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PIN FUNCTION DESCRIPTION

PIN PIN NAME DESCRIPTION

1 OCset Current limit set point. A resistor from this pin to GND will set the positive and negative current limit threshold

2 FB Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistordivider to set the output voltage and provide feedback to the error amplifier.

3 COMP Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to groundto provide loop compensation.

4 SS/SD Soft−Start / Shutdown. This pin provides user programmable soft−start function. External capacitor connectedfrom this pin to ground sets the startup time of the output voltage. The converter can be shutdown by pulling thispin below 0.3 V.

5 SYNC The internal oscillator can be synchronized to an external clock via this pin and other IC’s can be synchronizedvia this pin to internal oscillator. If it is not used this pin should be connected via 10 k� resistor to ground.

6 PGND Power Ground. This pin serves as a separate ground for the MOSFET driver and should be connected to thesystem’s power ground plane.

7 LDRV Output driver for low side MOSFET.

8 DRVVCC This pin provides biasing for the internal low side driver. A minimum of 0.1 �F, high frequency capacitor must beconnected from this pin to power ground.

9 VB This pin powers the high side driver and must be connected to a voltage higher than input voltage. A minimum of0.1 �F, high frequency capacitor must be connected from this pin to switch node.

10 HDRV Output driver for high side MOSFET

11 VS Switch Node. This pin is connected to the source of the upper MOSFET and the drain of the lower MOSFET.This pin is return path for the upper gate driver.

12 VCC This pin provides power for the internal blocks of the IC. A minimum of 0.1 �F, high frequency capacitor must beconnected from this pin to ground.

13 OCIN Overcurrent sensing input. A serial resistor from this pin to drain of low MOSFET must be used to limit thecurrent into this pin.

14 GND Signal ground for internal reference and control circuitry.

15 RT Connecting a resistor from this pin to ground sets the oscillator frequency.

16 UVLO An external voltage divider is used to set the undervoltage threshold levels.

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ABSOLUTE MAXIMUM RATINGS

Rating Symbol Min Max Unit

FB, VUVLO, RT, OCset −0.3 10 V

COMP, SS/SD, SYNC, OCIN −0.3 6 V

LDRV −0.3 VCC + 0.3 V

DRVVCC, VCC −0.3 20 V

VB VS VS + 20 V

HDRV VS − 0.3 VB + 0.3 V

VS −1.0 150 V

OCin Input Current 20 mA

All voltages referenced to GND

Rating Symbol Value Unit

Thermal Resistance, Junction−to−Ambient R�JA 130 °C/W

Operating Ambient Temperature Range TA −40 to 125 °C

Storage Temperature Range TSTG −55 to 150 °C

Junction Operating Temperature TJ −40 to 150 °C

ESD Withstand Voltage (Note 1)Human Body ModelMachine Model

VESD2000200

VV

Latchup Capability per Jedec JESD78

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. Excluding pins Vb, VS and HDRV.

TYPICAL ELECTRICAL PARAMETERS

RECOMMENDED OPERATING CONDITIONS

Symbol Definition Min Max Unit

VIN Converting Voltage 100 V

VCC Supply Voltage 10 18 V

DRVCC Supply Voltage 10 18 V

VB to VS Supply Voltage 10 18 V

FSW Operating Frequency 25 500 kHz

TJ Junction Temperature −40 125 °C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device reliability.

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ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over VCC = 12 V, DRVVCC = VB = 12 V, −40°C < TJ < 125°C)

Parameter Symbol Test Condition Min Typ Max Unit

REFERENCE VOLTAGE

Feedback Voltage VFB 1.25 V

Accuracy −40°C < TJ < 125°C −1.5 +1.5 %

FB Voltage Line Regulation LREG 10 V < VCC < 18 V (Note 3) 2.0 mV

SUPPLY CURRENT

VCC Supply Current (Stat) ICC(Static) SS = 0 V, No Switching, RT = 10 k�,ROCSET = 10 k�

2.0 3.0 mA

DRVVCC Supply Current (Stat) IC(Static) SS = 0 V, No Switching 0.1 0.3 mA

VB Supply Current (Stat) IB(Static) SS = 0 V, No Switching 0.1 0.3 mA

UNDERVOLTAGE LOCKOUT

VCC−Start−Threshold VCC_UVLO (R) Supply Ramping Up 7.9 8.9 9.8 V

VCC−Stop−Threshold VCC_UVLO (F) Supply Ramping Down 7.3 8.2 9.0 V

VCC−Hysteresis Supply Ramping Up and Down 0.7 V

DRVCC−Start−Threshold DRVCC_UVLO (R) Supply Ramping Up 7.9 8.9 9.8 V

DRVCC−Stop−Threshold DRVCC_UVLO (F) Supply Ramping Down 7.3 8.2 9.0 V

DRVCC−Hysteresis Supply Ramping Up and Down 0.7 V

VB−Start−Threshold VB_UVLO (R) Supply Ramping Up 7.9 8.9 9.8 V

VB−Stop−Threshold VB_UVLO (F) Supply Ramping Down 7.3 8.2 9.0 V

VB−Hysteresis Supply Ramping Up and Down 0.7 V

Undervoltage Threshold Value UUVLO (Rising) 1.19 1.25 1.31 V

Undervoltage Threshold Value UUVLO (Falling) 1.10 1.15 1.20 V

OSCILLATOR

Frequency FS RT = 20 k�RT = 10 k�

170320

200375

230430

kHz

Ramp Amplitude Vramp (Note 3) 2.0 V

Min Duty Cycle Dmin FB = 2 V 0 %

Min Pulse Width Dmin(ctrl) FS = 200 kHz, (Note 3) 200 ns

Max Duty Cycle Dmax FS = 400 kHz, FB = 1.2 V 80 %

SYNC Frequency Range SYNC(FS) 20% Above Free RunningFrequency

500 kHz

SYNC Pulse Duration SYNC(pulse) 200 ns

SYNC High Level SYNC(H) 2.0 V

SYNC Low Level SYNC(L) 0.8 V

SYNC Input Threshold SYNC(Thre) 1.6 V

SYNC Input Hysteresis SYNC(Hyst) 300 mV

SYNC Input Impedance SYNC(ZIN) (Note 3) 16 k�

SYNC Output Impedance SYNC(OUT) (Note 3) 2.5 k�

SYNC Output Pulse Width SYNC(Pulse Width) FS = 500 kHz, (Note 3) 300 ns

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.2. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.3. Guaranteed by design but not tested in production.

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ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over VCC = 12 V, DRVVCC = VB = 12 V, −40°C < TJ < 125°C)

Parameter UnitMaxTypMinTest ConditionSymbol

ERROR AMPLIFIER

Input Bias Current IFB SS = 3 V, FB = 1 V −0.1 −0.4 �A

Source/Sink Current I(Source/Sink) 50 100 120 �A

Bandwidth (Note 3) 4.0 10 MHz

DC gain (Note 3) 55 dB

Transconductance gm (Note 3) 1500 3150 4000 �mho

SOFT−START/SD

Soft−Start Current ISS SS = 0 V 15 20 25 �A

Shutdown Output Threshold SD 0.3 0.4 V

OVERCURRENT PROTECTION

OCSET Voltage VOCSET 1.25 V

Hiccup Current IHiccup (Note 3) 1.0 �A

Hiccup Duty Cycle Hiccup(duty) IHiccup/ISS, (Note 3) 5.0 %

OUTPUT DRIVERS

LO, Drive Rise Time tr(Lo) CL = 1.5 nF (See Figure 3) 17 ns

HI Drive Rise Time tr(Hi) CL = 1.5 nF (See Figure 3) 17 ns

LO Drive Fall Time tf(Lo) CL = 1.5 nF (See Figure 3) 10 ns

HI Drive Fall Time tf(Hi) CL = 1.5 nF (See Figure 3) 10 ns

Dead Band Time tdead (See Figure 3) 30 60 120 ns

LO Output High Short CircuitPulsed Current

tLDRVhigh VLDRV = 0 V, PW � 10 �s,TJ = 25°C (Note 3)

1.4 A

HI Output High Short CircuitPulsed Current

tHDRVhigh VHDRV = 0 V, PW � 10 �s,TJ = 25°C (Note 3)

2.2 A

LO Output Low Short CircuitPulsed Current

tLDRVhigh VLDRV = DRVVCC, PW � 10 �s,TJ = 25°C (Note 3)

1.4 A

HI Output Low Short CircuitPulsed Current

tHDRVhigh VHDRV = VB, PW � 10 �s,TJ = 25°C (Note 3)

2.2 A

LO Output Resistor, Source RLOH Typical Value @ 25°C, (Note 3) 7 12 �

LO Output Resistor, Sink RLOL Typical Value @ 25°C, (Note 3) 2 8 �

HI Output Resistor, Source RHIH Typical Value @ 25°C, (Note 3) 7 12 �

HI Output Resistor, Sink RHIL Typical Value @ 25°C, (Note 3) 2 8 �

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.2. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.3. Guaranteed by design but not tested in production.

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Figure 3. Definition of Rise−Fall Time and Deadband Time

tr tf

tr tf

9 V

2 V

9 V

2 V

High−SideDriver(HDrv)

Low−SideDriver(LDrv)

DeadbandH to L

DeadbandL to H

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TYPICAL OPERATING CHARACTERISTICS

1.2

1.22

1.24

1.26

1.28

1.3

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 4. VFB

VB (

V)

8.0

8.2

8.4

8.6

8.8

9.0

9.2

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 5. UVLOVB

UV

LOV

B (

V)

Rising

Falling

1.1

1.15

1.2

1.25

1.3

1.35

1.4

−40 −20 0 20 40 60 80 100 120

UV

LOV

CC

(V

)

TEMPERATURE (°C)

Figure 6. UVLOVCC

Rising

Falling

7.9

8.0

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

9.0

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 7. UVLODRVVCC

UV

LOD

RV

VC

C (

V)

Rising

Falling

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

9.0

9.1

9.2

−40 −20 0 20 40 60 80 100 120

UV

LO (

V)

TEMPERATURE (°C)

Figure 8. UVLO

Rising

Falling

1.8

1.9

2.0

2.1

2.2

2.3

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 9. ICC (Stat)

I CC

(st

at)

(mA

)

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TYPICAL OPERATING CHARACTERISTICS

180

185

190

195

200

205

210

215

220

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)Figure 10. Switching Frequency @ RT = 20 k�

f SW

(kH

z)

70

72

74

76

78

80

82

84

86

88

90

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)Figure 11. Maximum Duty Cycle @ f = 400 kHz

Dm

ax (

%)

170

175

180

185

190

195

200

205

210

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 12. Minimum on Time

t onm

in (

ns)

1500

2000

2500

3000

3500

4000

4500

−40 −20 0 20 40 60 80 100 120

g m (�m

ho)

TEMPERATURE (°C)

Figure 13. Error Amplifier Transconductance

40

45

50

55

60

65

70

75

80

85

90

−40 −20 0 20 40 60 80 100 120

Low to High

High to Low

TEMPERATURE (°C)

Figure 14. Deadtime

t (ns

)

4

5

6

7

8

9

10

11

12

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 15. Driver Pullup Resistance

R (�

) DRVVCC = VB = 10 V

12 V

18 V

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TYPICAL OPERATING CHARACTERISTICS

1.0

1.5

2.0

2.5

3.0

3.5

4.0

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 16. Driver Pulldown Resistance

R (�

)

DRVVCC = VB = 10 V12 V

18 V

−0.3

−0.29

−0.28

−0.27

−0.26

−0.25

−0.24

−0.23

−0.22

−0.21

−0.2

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 17. OCP @ R8 = 10 k�, ROCIN = 10 k�

VD

SLO

WF

ET (

V)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 18. POSOCP @ R8 = 10 k�,ROCIN = 10 k�

VD

SLO

WF

ET (

V)

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APPLICATION INFORMATION

Undervoltage Lock−outThere are four undervoltage lock−out circuits. Two of

them protect external high−side and low−side drivers, thethird ensures that the IC does not start until VCC is under aset threshold. The last one can be programmed by the user.It has a rising threshold at 1.25 V and a falling threshold at1.15 V, and the user can define the undervoltage level by anexternal resistor divider. If the voltage is not over thethreshold value, the device stops operating. The high−sidedriver UVLO only stops switching the high−side MOSFETProgrammed falling and rising UVLO voltage can becalculated by Equations 1 and 2:

VUVLO,falling � 1.15 � �1 �R4

R5� (eq. 1)

and

VUVLO,rising � 1.25 � �1 �R4

R5� (eq. 2)

ShutdownThe output voltage can be disabled by pulling the

SS/SD pin below 0.3 V. A small transistor can be used to pullit down as shown in Figure 19. During this time, bothexternal MOSFETs are turned off. After the SS/SD pin isreleased, the IC starts its operation with a soft−startsequence.

Figure 19. Shutdown Interface

SS/SDSS/SD

Operating Frequency SelectionThe operating frequency is set by an external resistor

connected from the Rt Pin to ground. The value of thisresistor can be selected from Figure 20, which showsswitching frequency versus the timing resistor value.

Figure 20. Frequency Dependence of Rt Value

0

50

100

150

200

250

300

350

400

450

500

0 50 100 150 200 250

Rt (k�)

f (kH

z)

Frequency SynchronizationThe NCP1034 can be synchronized to an external clock

signal. The input synchronization signal should be a TTLlogic level. The oscillator is synchronized to the rising edgeof the synchronizing signal. When synchronization is used,the free running frequency must be set by the timing resistorto a frequency at least 80% of the external synchronizationfrequency (Example: RT = 20 k� / 200 kHz and externalTTL = 220 kHz).

The NCP1034 can also output synchronization pulses onthe SYNC pin. Pulses are generated when the internaloscillator ramp reaches the high threshold voltage. Thefrequency of these pulses is set by an external RT resistor. Upto five NCP1034 controllers can be connected directly to theSYNC pin, all of which are synchronized to the controllerwith the highest frequency. The lowest frequency must be atleast 80% of the highest one.

The equivalent internal circuit of the Sync pin is shown inFigure 21.

Figure 21. Equivalent Connection of the Sync Pin

Oscillator

SYNC

RtRt

Ct

VBIAS

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Figure 22 shows the part with no synchronization. In thiscircuit the internal clock is fixed by the external timingresistor RT. The SYNC pin can be tied to GND through aseries resistor to prevent false triggering in a noisyenvironment.

Figure 22. Fixed Frequency

SYNC

NCP1034

FSW = 200 kHz

RT

10 k�(optional)

20 k�

Figure 23 shows the part synchronized to an externalclock through the SYNC pin. The synchronizationfrequency can be up to 20% greater then the programmedfixed frequency (Example: RT = 20 k� / 200 kHz and theSYNC input frequency can range from 200−220 kHz). Theclock frequency at the SYNC pin replaces the master clockgenerated by the internal oscillator circuit. Pulling theSYNC pin low programs the part to run freely at thefrequency programmed by RT. When pulling the SYNC pinlow a 4.7 kΩ resistor should be used.

Figure 23. External Synchronization

SYNC

NCP1034

FSW = 220 kHz

RT

4.7 k�(optional)

20 k�

Input: = 220 kHz

TTLLogic

Figure 24 shows the part operating in the master slavesynchronization configuration. In this configuration allthree parts are connected together through the SYNC pin inorder to synchronize the system switching frequency. TheRT timing resistor can be the same value for all three parts(RT = 20 k� / 20 k� / 20 k�) which would make the highestfrequency part the master, or to guarantee one part is themaster the timing resistor can be slightly lower in value. (RT= 20 k� / 22 k� / 22 k�)

Figure 24. Master Slave Synchronization

SYNC

NCP1034(Master #1)

FSW = 200 kHz

RT

20 k�

SYNC

NCP1034(Slave #1)

FSW = 180 kHz

RT

22 k�

SYNC

NCP1034(Slave #2)

FSW = 180 kHz

RT

22 k�

Synchronized SystemFrequency = 200 kHz

Output VoltageOutput voltage can be set by an external resistor divider

according to this Equation 3:

VOUT � Vref � �1 �R1

R2� (eq. 3)

Where Vref is the internal reference voltage 1.25 V. Absolutevalues of resistors R1 and R2 depend on compensationnetwork type. See compensation paragraph for details.

Inductor SelectionThe inductor selection is based on the output power,

frequency, input and output voltage and efficiencyrequirements. High inductor values cause low currentripple, slower transient response, higher efficiency andincreased size. Inductor design can be reduced to desiremaximum current ripple in the inductor. It is good to havecurrent ripple (�ILmax) between 20% and 50% of the outputcurrent.

For buck converter, the inductor should be chosenaccording to Equation 4.

L � � VOUT

f � �ILmax

��1 �VOUT

VINmax

� (eq. 4)

Output Capacitor SelectionThe output voltage ripple and transient requirements

determine the output capacitor type and value. Theimportant parameter for the selection of the output capacitoris equivalent serial resistance (ESR). If the capacitor has lowESR, it often has sufficient capacity for filtering as well asan adequate RMS current rating.

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The value of the output capacitor should be calculatedusing the following equation:

COUT �IL

8 � f � ��VOUT � �IL � ESR�(eq. 5)

For higher switching frequency, it is suitable to usemulti−layer ceramic capacitor (MLCC) with very low ESR.The advantages are small size, low output voltage ripple andfast transient response. The disadvantage of MLCC type isthe requirement to use a Type III compensation network.

Input Capacitor SelectionThe input capacitor is used to supply current pulses while

high−side MOSFET is on. When the MOSFET is off, theinput capacitor is being charged. The value of this capacitorcan be selected with Equation 6:

CIN

IOUT �VOUT

VIN

� �1 �VOUT

VIN

�f � �VIN

(eq. 6)

Where �VIN is the input voltage ripple and therecommended value is about 2% − 5% of VIN. The inputcapacitor must be large enough to handle the input ripplecurrent. Its value should be calculated using Equation 7:

IRMS � IOUT �

VOUT � �1 �VOUTVIN�

VIN

(eq. 7)

Power MOSFET SelectionThe NCP1034 uses two N−channel MOSFET’s. They can

be primary selected by RDS(on), maximum drain−to−sourcevoltage and gate charge. RDS(on) impacts conductive lossesand gate charge impacts switching losses. The low sideMOSFET is selected primarily for conduction losses, andthe high−side MOSFET is selected to reduce switchinglosses especially when the output voltage is less than 30% ofthe input voltages. The drain−to−source breakdown voltagemust be higher than the maximum input voltage. Conductivepower losses can be calculated using the Equations 8 and 9:

PCOND�HIGHFET � I2OUT � RDS(on) �VOUT

VIN

(eq. 8)

PCOND�LOWFET � I2OUT � RDS(on) � �1 �VOUT

VIN

� (eq. 9)

Switching losses are depended on drain−to−sourcevoltage at turn−off state, output current and switch−on andswitch−off time as is shown by Equation 10.

PSW �VDS(off)

2� �tON � tOFF

� � f � IOUT(eq. 10)

tON and tOFF times are dependent on the transistor gate.The MOSFET output capacitance loss is caused by thecharging and discharging during the switching process andcan be computed using Equation 11.

PCOSS �COSS � VIN

2 � f

2(eq. 11)

Where COSS = CDS + CGD.Significant power dissipation is caused by the reverse

recovery charge in the low−side MOSFET body diode,which conducts at dead time. This charge is needed to closethe diode. The current from the input power supply flowsthrough the high−side MOSFET to the low−side MOSFETbody diode. This power dissipation can be calculated usingEquation 12.

PQRR � QRR � VIN � f (eq. 12)

QRR is the diode recovery charge as given in themanufacturer’s datasheet. For some types of MOSFETs, thisdissipation may be dominant at high input voltages. It isnecessary to take care when selecting a MOSFET. Anexternal Schottky diode across the low−side MOSFET canbe used to eliminate the reverse recovery charge power loss.The Schottky diode’s forward voltage should be lower thanthat of the body diode, and reverse recovery time (trr) shouldbe lower then that of the body diode. The Schottky diode’scapacitance loss can be calculated as shown in Equation .

PC(Schottky) �CSchottky � VIN

2 � f

2(eq. 13)

NCP1034

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Figure 25. MOSFETs Timing Diagram

High−SideLogic Signal

Low−SideLogic Signal

High−SideMOSFET

Low−SideMOSFET

RDSmax

RDS(on)min

RDSmax

RDS(on)min

tdead tdead

tftd(on)

tr td(off)

tr tf

td(on)td(off)

MOSFETs delays, turn−on and turn−off times must beshort enough to prevent cross conduction. If not, there willbe cross conduction from the input through both MOSFETsto ground. Due to this fact, the following conditions must betrue:

td(on)high � tdead � td(off)low � tf low (eq. 14)td(on)low � tdead � td(off)high � tf high

Where tdead is the controller dead band time, td(on), tr, td(off)and tf are MOSFETs parameters. These parameters can befound in the datasheet for specific conditions.

It is NOT recommended to add external resistor or othercircuit on MOSFETs’ gates to slow−down their turn−off. Ifgate resistance is a must, please make sure the abovecondition in eq. 14 is still satisfied to avoid cross conduction.

Bootstrap CircuitThis circuit is used to obtain a voltage higher than the

input voltage in order to switch−on high side N MOSFET.The bootstrap capacitor is charged from the IC’s supplyvoltage through D1, when the low side MOSFET isswitched−on up to the IC’s supply voltage. It must haveenough capacity to supply power for the high−side circuitwhen the high−side MOSFET is being switched on. Theminimum value recommended for the bootstrap capacitor is100 nF. Diode D1 has to be designed to withstand a reversevoltage given by the following equation:

D1VRmin � VIN � VCC (eq. 15)

Soft−StartThe soft−start time is set by capacitor connected between

SS/SD Pin and ground. This function is used for controlling

the output voltage slope and limiting startup currents. Thestart−up sequence initiates when Power On Ready (POR)internal signal rises to logic high level. That means the supplyvoltage, low side drive supply voltage and external UVLO areover the set thresholds. The soft−start capacitor is charged by20 �A current source. If POR is low, the SS/SD Pin isinternally pulled to GND, which means that the NCP1034 isin a shutdown state. The SS/SD Pin voltage (0 V to 2.6 V)controls internal current source (64 �A to 0 �A) with negativelinear characteristic. This current source injects current intothe resistor (25 k�) connected between the Fb pin andnegative input of the error amplifier and into the externalfeedback resistor network. Voltage drop on these resistors isover 1.6 V, which is enough to force the error amplifier intonegative saturation state and to block switching.

Note that at cold ambient temperatures (−35°C) the internal25 k� drops up to 25% in value and so does the internal currentsource (64 �A) up to 10%. For those reasons, users mustcompensate for these variations by increasing the external lowerresistive divider value in order to force the error amplifier intonegative saturation at Soft−Start. Here is an example at −35°Cshowing how to select the proper R2 resistor:Rinternal ~ 19 k�Internal Current Source ~ 58 �AVRinternal = 19 k� x 58 �A = 1.1 VSelect R2 such that;VR2 = 1.6 V – 1.1 V = 0.5 V

R2min = 0.5 V58 �A

= 8.6 k�.

The minimum value required for R2 to keep Comp at GNDis 8.6 k�.

NCP1034

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When the soft−start pin reaches around 1.2 V (exact valuedepends on feedback and compensation network and onsoft−start capacitor; a larger soft−start capacitor and a lowercompensation capacity decrease this level) the IC startsswitching. The impact of controlled current sourcedecreases and the output voltage starts to rise. When thesoft−start capacitor voltage reaches 2.6 V, the output voltageis at nominal value.

The soft−start time must be at least 10 times longer thanthe time needed to charge the compensation network fromthe output of the error amplifier. If the soft−start time is notlong enough, the soft−start sequence would be faster than thecharging compensation network and the IC would startwithout slowly increasing the output voltage. The soft−startcapacitance can be calculated using Equation 16.

CSS � 15 � 10−6 � TSS (eq. 16)

Figure 26. Soft−Start

5V~2.6V

~1.2V

0V

SS

POR

VOUT

64�A

IFB

>1.6V

FBVoltage

1.25V

1.25V0V

Start to Prebiased OutputThe NCP1034 is able to startup into a prebiased output

capacitor. The low−side MOSFET does not turn on beforehigh−side MOSFET gets the first turn−on pulse. During this

time, the energy is not discharged by the low−side MOSFETuntil the soft−start sequence crosses the programmed outputvoltage.

Figure 27. Startup to Prebiased Output

~1.2V

~2.6V

LDRV

HDRV

VOUT

~5V

SS

NCP1034

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Overcurrent ProtectionThe voltage drop across the low side MOSFET RDS(on) is

connected through resistor R8 and into the IC though pin 13OCin. Within the IC, this value is compared with the valueprogrammed by resistor R7 to set the overcurrent limit. Theprogrammed current limit is set by selecting the value of R7,which is connected between pin 1 OCset and GND. If thevoltage drop is larger than the set value, the NCP1034 goesinto hiccup mode. During this time, both external MOSFETsare turned off and the soft start capacitor is discharged with

a current equal to 5% of the charging current. The capacitorcontinues to discharge until the voltage reaches 0.25 V, andthen the IC initiates a standard soft start sequence.

The recommended value for the protection resistor R8 is10 k�. The R7 resistance value can be calculated usingEquation 17:

R7 �R8

3.56 � RDS(on) � Ipk(eq. 17)

Figure 28. Overcurrent Protection (Hi−Cup Mode)

SS~1.2V

5V 0.3V ~1.2V~1.9V 0.3V

~1.2V~1.9V0.3V

~1.2V

~2.6V

5V

VOUT

IOUT

ROUT

~2.6V

The NCP1034 provides protection of the low−sideMOSFET against positive overcurrent (from output to thisMOSFET). Its value can be calculated using Equation 18:

IPos �5125 � 0.184 � R8 � 1.25

R7 � RDS(on)(eq. 18)

NCP1034’s overcurrent protection threshold could beaffected by external circuits and PCB layout. Please payattention to the following:

♦ Do not slow down the low−side MOSFETturning−on by any resistance or other circuit on itsgate. About 80 ns after the rising edge of LDRV pin,the NCP1034 overcurrent protection function starts.If the low−side MOSFET hasn’t been fullyturned−on then, the overcurrent protection may befalsely triggered, even at very low load current.

♦ OCin trace layoutThe OCin trace, between OCin pin and R8, is a highimpedance node. Any noise coupling to it mayfalsely trigger overcurrent protection. Please avoidany noise source near this OCin trace, such as VS,VB, HDRV and LDRV nodes. Any capacitance onthe OCin pin impacts the overcurrent protectionthreshold as well. Therefore, it is not recommended.

♦ The voltage difference between PGND pin andlow−side MOSFET source pin affects overcurrentprotection threshold. As shown in Figure 2, theovercurrent comparator input pin OCin is referenceto PGND pin. Therefore, the overcurrent protectionthreshold should factor in the voltage differencebetween the external MOSFET’s source pins and theNCP1034’s PGND pin.

♦ fix R8 = 10 k� As shown in Eq. 17 and Eq. 18, R8 resistance affectsovercurrent limit threshold and positive overcurrentlimit threshold in opposite directions. To simplifythe design, please fix R8 at 10 k� as possible, anduse R7 to program overcurrent limit threshold.

Compensation CircuitThe NCP1034 is a voltage mode buck convertor with a

transconductance error amplifier compensated by anexternal compensation network. Compensation is needed toachieve accurate output voltage regulation and fast transientresponse. The goal of the compensation circuit is to providea loop gain function with the highest crossing frequency andadequate phase margin (minimally 45°).

NCP1034

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The transfer function of the power stage (the output LCfilter) is a double pole system. The resonance frequency ofthis filter is expressed as follows:

fP0 �1

2 � � � L � COUT (eq. 19)

One zero of this LC filter is given by the output capacitanceand output capacitor ESR. Its value can be calculated byusing the following equation:

fZ0 �1

2 � � � COUT � ESR (eq. 20)

The next parameter that must be chosen is the zerocrossover frequency f0. It can be chosen to be 1/10 − 1/5 ofthe switching frequency. These three parameters show thenecessary type of compensation that can be selected fromTable 1.

Table 1. COMPENSATION TYPES

Zero Crossover Frequency Condition Compensation Type Typical Output Capacitor Type

fP0 < fZ0< f0 < fS/2 Type II (PI) Electrolytic, Tantalum

fP0 < f0< fZ0 < fS/2 Type III (PID) Method I Tantalum, Ceramic

fP0 < f0 < fS/2 < fZ0 Type III (PID) Method II Ceramic

Compensation Type II (PI)This compensation is suitable for low−cost electrolytic

capacitor. The zero created by the capacitor’s ESR is a fewkHz and the zero crossover frequency is chosen to be 1/10of the switching frequency. Components of the PIcompensation (Figure 29) network can be specified by thefollowing equations:

Figure 29. PI compensation (II Type)

+

−OTA

R2

R1

Vref

VOUT

RC1

CC1

CC2*

*Optional

RC1 �2 � � � f0 � L � VRAMP � VOUT

ESR � VIN � Vref � gm

(eq. 21)

CC1 �1

0.75 � 2 � � � fP0 � RC1

CC2 �1

� � RC1 � fS

R1 �VOUT � Vref

Vref

� R2

VRAMP is the peak−to−peak voltage of the oscillator rampand gm is the transconductance error amplifier gain.Capacitor CC2 is optional.

Compensation Type III (PID)Tantalum and ceramics capacitors have lower ESR than

electrolytic, so the zero of the output LC filter goes to ahigher frequency above the zero crossover frequency. Thissituation needs to be compensated by the PID compensationnetwork that is show in Figure 30.

+

−

R 1

R 2 V REF

OTA

R C1 C C1

C C2

V OUT

R FB1

C FB1

Figure 30. PID Compensation (III Type)

There are two methods to select the zeros and poles ofcompensation network. The first one (method I) is useablefor tantalum output capacitors, which have a higher ESRthan ceramic, and its zeros and poles can be calculatedshown below:

fZ1 � 0.75 � fP0

(eq. 22)

fZ2 � fP0

fP2 � fZ0

fP3 �fS

2

The second one (method II) is for ceramic capacitors:

NCP1034

www.onsemi.com19

fZ2 � f0 �1 � sin �max

1 � sin �max

(eq. 23)fP2 � f0 �1 � sin �max

1 � sin �max

fZ1 � 0.5 � fZ2

fP3 � 0.5 � fS

The remaining calculations are the same for both methods.

RC1 ��2

gm

(eq. 24)

CC1 �1

2 � � � fZ1 � RC1

CC2 �1

2 � � � fP3 � RC1

CFB1 �2 � � � f0 � L � VRAMP � COUT

VIN � RC1

RFB1 �1

2� � CFB1 � fP2

R1 �1

2 � � � CFB1 � fZ2

� RFB1

R2 �Vref

VOUT � Vref

� R1

To check the design of this compensation network, theequation must be true

R1 � R2 � RFB1 �1

gm(eq. 25)

If it is not true, then a higher value of RC1 must be selected.

Input Power SupplyThe NCP1034 controller and built−in drivers need to be

powered through VCC, DRVVCC and Vb pins with a voltagebetween 10 V – 18 V. The supply current requirement is asummation of the static and dynamic currents. Static currentconsumption can be calculated by the following equation:

ICS � ICC � IC � IB (eq. 26)

Dynamic current consumption is calculated using thefollowing equation, base on the switching frequency andMOSFET gate charge.

ICD � �QG(low) � QG(high)� � f (eq. 27)

To power the device, an external power supply or voltageregulator from VIN can be used. Two options are a linearshunt voltage regulator and a shunt voltage regulator withtransistor, as shown in Figure 31. A voltage regulatorwithout a transistor can be used when the powerconsumption is low and zener diode power dissipation isacceptable. Otherwise, a shunt regulator with transistor canbe used.

Figure 31. Linear ShuntVoltage Regulator

VCCVIN

CD

VCCVIN

CD

Figure 32. Shunt VoltageRegulator with Transistor

R

For the linear shunt voltage regulator (option a) the VCCvoltage is the same as the zener diode reverse voltage VZ.The value of the resistor R can be calculated usingEquation 28, where IZT is the minimum reverse current atVZ. The value selected should be lower than the calculatedvalue. The maximum power losses of resistor R and thezener diode D can be calculated by Equations 29 and 30.

R VINmin � VCC

ICS � ICD � IZT

(eq. 28)

PR � (VINmax � VCC) � (ICS � ICD) (eq. 29)

PD � �VINmax � VCC

R� ICS� (eq. 30)

The shunt voltage regulator with transistor (option b) isadvantageous when the zener diode loss is too high or wheninput voltage varies across a wide range and it is difficult toset a bias point. The output voltage is lower than VZ due tothe VBE of the transistor. The maximum resistor value of Rcan be calculated by Equation 31, where � is the transistorDC current gain. The maximum power dissipation of theresistor, zener diode and transistor are calculated byEquations 32 to 34. The transistor reverse breakdownvoltage must be selected to be able to withstand the voltagedifference between maximum input voltage and VCC.

R VINmin � VZT

ICS�ICD�

� IZT

(eq. 31)

NCP1034

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PR � �VINmax � VCC� � �ICS � ICD

�� IZT� (eq. 32)

PD � �VINmax � VZT

R�

ICS

�� � VZT (eq. 33)

PD � �VINmax � VZT

R�

ICS

�� � VZT (eq. 34)

PT � �VINmax � VCC� � �ICS � ICD

� (eq. 35)

Table 2. POWER SUPPLY REGULTOR EXAMPLES

Components MOSFETsQG(TOT)

(nC)f

(kHz)VINmax

(V)VINmin

(V)ISUPPLYmax

(mA)RBIAS

(k�) ZD Transistor

LS−FET NTD24N06 24 200 60 36 8.7 2.6 MMSZ4699 −

HS−FET NTD3055 7.1

LS−FET NTD24N06 24 300 60 20 16.9 10 MMSZ4699 MJD31

HS−FET NTD24N06 24

PCB LayoutThe layout of high−frequency and high−current switching

converters has a large impact on the circuit parameters. It isimportant, therefore, to pay close attention to the PCBlayout.

The input capacitor, MOSFETs, inductor and outputcapacitor should be placed as close as possible to oneanother. This is suitable to reduce EMI and to minimize VSovershoots. Connecting the signal and power ground at one

point near the output connector improves load regulation.Connection between the source pin of the low side MOSFETand the IC should be very short with wide traces andoptimally using two layers to achieve minimum inductancebetween them.

The blocking and bootstrap capacitors should be placed asclose as possible to the IC. The feedback and compensationnetwork should be close to the IC to minimize noise.

TYPICAL APPLICATION

Figure 33. Single Output Buck Converter from 38 V − 58 V to 5 V/5 A @ 200 kHz

12

5

15

4

16

1

14

10

11

13

7

6

2

3

R710k

R620k

C5

220nR53k9

VCC

SYNC

RT

UVLO

OCSET

GND

HDRV

VS

OCIN

LDRV

PGND

FB

COMP

SS/SD

C10

100n

D11N4148

C4

100n

R4110k

IC1NCP1034SMD

8 9

DRVVCC VB

R3

4k7

C7

330p

C6

12n

R8

10k

48 V

�20

%

C1A2u2

C9

47�

C9B

47�

Q2NTD3055

Q3NTD24N06

L1

13�

R25k6

R116k9

R91k2

C8

1n8

GND GND GND GND GND

GND

GND

GND

C1B2u2

C9C

47�

GND

R10

10k

D2 C2100n

C3 100n

X1−1

X1−2

X2−2

X2−1R15

0R

R11A 10k

R11B 10k

R11C 10k

R11D 10k

R11E 10k

MMSZ4699

5V@

5A, 2

00kH

z

NCP1034

www.onsemi.com21

50

55

60

65

70

75

80

85

90

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

VIN = 58 V

48 V

38 V

Figure 34. Efficiency and Power Loss of Circuit at Figure 33IOUT (A)

EF

FIC

IEN

CY

(%

)

NCP1034

www.onsemi.com22

Bill of Materials

Designator Qty Description Value Tolerance Footprint ManufacturerManufacturerPart Number

R9 1 Resistor 1k2 1% 1206 Vishay CRCW10261K20FKEA

R5 1 Resistor 3k9 1% 1206 Vishay CRCW10263K90FKEA

R3 1 Resistor 4k7 1% 1206 Vishay CRCW10264K60FKEA

R2 1 Resistor 5k6 1% 1206 Vishay CRCW10265K60FKEA

R1 1 Resistor 16k9 1% 1206 Vishay CRCW102616K9FKEA

R6 1 Resistor 20k 1% 1206 Vishay CRCW102620K0FKEA

R11A, R11B,R11C, R11D,

R11E

5 Resistor 12k 1% 1206 Vishay CRCW102612K0FKEA

R4 1 Resistor 110k 1% 1206 Vishay CRCW1206110KFKEA

R7, R8, R10 3 Resistor 10k 1% 1206 Vishay CRCW120610K0FKEA

C8 1 Ceramic Capacitor 1n8 10% 1206 Kemet C1206C182K5FA−TU

C6 1 Ceramic Capacitor 12n 10% 1206 Kemet C1206C123K5FACTU

C5 1 Ceramic Capacitor 220n 10% 1206 Kemet C1206C224K5RACTU

C7 1 Ceramic Capacitor 330p 10% 1206 Kemet −

C2, C3, C4, C10 4 Ceramic Capacitor 100n 10% 1206 Kemet C1206F104K1RACTU

C9A, C9B, C9C 3 Ceramic Capacitor 47�/6.3V 20% 1210 Kemet C1210C476M9PAC7800

C1A, C1B 2 Ceramic Capacitor 2.2�/100V 10% 1210 Murata GRM32ER72A225KA35L

L1 1 Inductor SMD 13� 20% 13x13 Würth 744355131

D1 1 Switching Diode MMSD4148 − SOD123 onsemi MMSD4148T1G

D2 1 Zener Diode 12V MMSZ4699 − SOD123 onsemi MMSZ4699T1G

Q2 1 Power N−MOSFET NTD3055 − DPAK onsemi NTD3055−150G

Q3 1 Power N−MOSFET NTD24N06 − DPAK onsemi NTD24N06T4G

IO1 1 Synchronous PWMBuck Controller

NCP1034 − SOIC16 onsemi NCP1034DR2G

NCP1034

www.onsemi.com23

Figure 35. Top Layer Figure 36. Bottom Layer

Figure 37. Top Side Components Figure 38. Bottom Side Components

NCP1034

www.onsemi.com24

70m

m_

44 mm_

Figure 39. Typical Application Board Photos

ORDERING INFORMATION

Device Package Shipping†

NCP1034DR2G SOIC−16(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

SOIC−16CASE 751B−05

ISSUE KDATE 29 DEC 2006SCALE 1:1

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSIONSHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE DDIMENSION AT MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATINGPLANE

F

JM

R X 45�

G

8 PLP−B−

−A−

M0.25 (0.010) B S

−T−

D

K

C

16 PL

SBM0.25 (0.010) A ST

DIM MIN MAX MIN MAXINCHESMILLIMETERS

A 9.80 10.00 0.386 0.393B 3.80 4.00 0.150 0.157C 1.35 1.75 0.054 0.068D 0.35 0.49 0.014 0.019F 0.40 1.25 0.016 0.049G 1.27 BSC 0.050 BSCJ 0.19 0.25 0.008 0.009K 0.10 0.25 0.004 0.009M 0 7 0 7 P 5.80 6.20 0.229 0.244R 0.25 0.50 0.010 0.019

� � � �

6.40

16X0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

STYLE 1:PIN 1. COLLECTOR

2. BASE3. EMITTER4. NO CONNECTION5. EMITTER6. BASE7. COLLECTOR8. COLLECTOR9. BASE

10. EMITTER11. NO CONNECTION12. EMITTER13. BASE14. COLLECTOR15. EMITTER16. COLLECTOR

STYLE 2:PIN 1. CATHODE

2. ANODE3. NO CONNECTION4. CATHODE5. CATHODE6. NO CONNECTION7. ANODE8. CATHODE9. CATHODE

10. ANODE11. NO CONNECTION12. CATHODE13. CATHODE14. NO CONNECTION15. ANODE16. CATHODE

STYLE 3:PIN 1. COLLECTOR, DYE #1

2. BASE, #13. EMITTER, #14. COLLECTOR, #15. COLLECTOR, #26. BASE, #27. EMITTER, #28. COLLECTOR, #29. COLLECTOR, #3

10. BASE, #311. EMITTER, #312. COLLECTOR, #313. COLLECTOR, #414. BASE, #415. EMITTER, #416. COLLECTOR, #4

STYLE 4:PIN 1. COLLECTOR, DYE #1

2. COLLECTOR, #13. COLLECTOR, #24. COLLECTOR, #25. COLLECTOR, #36. COLLECTOR, #37. COLLECTOR, #48. COLLECTOR, #49. BASE, #4

10. EMITTER, #411. BASE, #312. EMITTER, #313. BASE, #214. EMITTER, #215. BASE, #116. EMITTER, #1

STYLE 5:PIN 1. DRAIN, DYE #1

2. DRAIN, #13. DRAIN, #24. DRAIN, #25. DRAIN, #36. DRAIN, #37. DRAIN, #48. DRAIN, #49. GATE, #4

10. SOURCE, #411. GATE, #312. SOURCE, #313. GATE, #214. SOURCE, #215. GATE, #116. SOURCE, #1

STYLE 6:PIN 1. CATHODE

2. CATHODE3. CATHODE4. CATHODE5. CATHODE6. CATHODE7. CATHODE8. CATHODE9. ANODE

10. ANODE11. ANODE12. ANODE13. ANODE14. ANODE15. ANODE16. ANODE

STYLE 7:PIN 1. SOURCE N‐CH

2. COMMON DRAIN (OUTPUT)3. COMMON DRAIN (OUTPUT)4. GATE P‐CH5. COMMON DRAIN (OUTPUT)6. COMMON DRAIN (OUTPUT)7. COMMON DRAIN (OUTPUT)8. SOURCE P‐CH9. SOURCE P‐CH

10. COMMON DRAIN (OUTPUT)11. COMMON DRAIN (OUTPUT)12. COMMON DRAIN (OUTPUT)13. GATE N‐CH14. COMMON DRAIN (OUTPUT)15. COMMON DRAIN (OUTPUT)16. SOURCE N‐CH

16

8 9

8X

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

98ASB42566BDOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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