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Dimmable Quasi-ResonantPrimary Side Current-ModeController for LED Lighting
The NCL30081 is a PWM current mode controller targeting isolatedflyback and non−isolated constant current topologies. The controlleroperates in a quasi−resonant mode to provide high efficiency. Thanksto a novel control method, the device is able to precisely regulate aconstant LED current from the primary side. This removes the needfor secondary side feedback circuitry, biasing and an optocoupler.
The device is highly integrated with a minimum number of externalcomponents. A robust suite of safety protection is built in to simplifythe design. This device is specifically intended for very compact spaceefficient designs. It supports step dimming by monitoring the AC lineand detecting when the line has been toggled on−off−on by the user toreduce the light intensity in 5 steps down to 5% dimming.
Features
• Quasi−resonant Peak Current−mode Control Operation
• Primary Side Sensing (no optocoupler needed)
• Wide VCC Range
• Precise LED Constant Current Regulation ±1% Typical
• Line Feed−forward for Enhanced Regulation Accuracy
• Low LED Current Ripple
• 250 mV ±2% Guaranteed Voltage Reference for Current Regulation
• ~ 0.9 Power Factor with Valley Fill Input Stage
• Low Start−up Current (10 �A typ.)
• Small Space Saving Low Profile Package
• 5 State Quasi−log Dimmable
• Wide Temperature Range of −40 to +125°C
• Pb−free, Halide−free MSL1 Product
• Robust Protection Features♦ Over Voltage / LED Open Circuit Protection♦ Secondary Diode Short Protection♦ Output Short Circuit Protection♦ Shorted Current Sense Pin Fault Detection♦ Latched and Auto−recoverable Versions♦ Brown−out♦ VCC Under Voltage Lockout♦ Thermal Shutdown
Typical Applications• Integral LED Bulbs
• LED Power Driver Supplies
• LED Light Engines
www.onsemi.com
PIN CONNECTIONS
See detailed ordering and shipping information in the packagedimensions section on page 30 of this data sheet.
ORDERING INFORMATION
TSOP−6SN SUFFIXCASE 318G
MARKING DIAGRAM
VIN
VCC
DRV
ZCD
GND
CS
(Top View)
1
1
AAx = Specific Device Codex = G or HA = Assembly LocationY = YearW = Work Week� = Pb−Free Package
Figure 1. Typical Application Schematic for NCL30081
Aux
1
2
3 4
5
6
.
.
.
Table 1. PIN FUNCTION DESCRIPTION
Pin No Pin Name Function Pin Description
1 ZCD Zero Crossing Detection Connected to the auxiliary winding, this pin detects the core reset event.
2 GND − The controller ground
3 CS Current sense This pin monitors the primary peak current
4 DRV Driver output The current capability of the totem pole gate drive (+0.3/−0.5 A) makes it suit-able to effectively drive a broad range of power MOSFETs.
5 VCC Supplies the controller This pin is connected to an external auxiliary voltage.
6 VIN Input voltage sensingBrown−Out
This pin observes the HV rail and is used in valley selection. This pin alsomonitors and protects for low mains conditions.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC unless otherwise noted.2. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC JESD22−A114−F and
Machine Model Method 200 V per JEDEC JESD22−A115−A.3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78 except for VIN pin which passes 60 mA.
Valley thresholds1st to 2nd valley transition at LL and 2nd to 3rd valley HL2nd to 1st valley transition at LL and 3rd to 2nd valley HL2nd to 4th valley transition at LL and 3rd to 5th valley HL4th to 2nd valley transition at LL and 5th to 3rd valley HL4th to 7th valley transition at LL and 5th to 8th valley HL7th to 4th valley transition at LL and 8th to 5th valley HL7th to 11th valley transition at LL and 8th to 12th valley HL11th to 7th valley transition at LL and 12th to 8th valley HL11th to 13th valley transition at LL and 12th to 15th valley HL13th to 11th valley transition at LL and 15th to 12th valley HL
The NCL30081 implements a current−mode architectureoperating in quasi−resonant mode. Thanks to proprietarycircuitry, the controller is able to accurately regulate thesecondary side current of the flyback converter withoutusing any opto−coupler or measuring directly the secondaryside current.• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peakcurrent−mode control, the NCL30081 optimizes theefficiency by switching in the valley of the MOSFETdrain−source voltage. Thanks to a smart controlalgorithm, the controller locks−out in a selected valleyand remains locked until the input voltage or the outputcurrent set point significantly changes.
• Primary Side Constant Current Control: thanks to aproprietary circuit, the controller is able to compensatefor the leakage inductance of the transformer and allowaccurate control of the secondary side current.
• Line Feed−forward: compensation for possiblevariation of the output current caused by system slewrate variation.
• Open LED protection: if the voltage on the VCC pinexceeds an internal limit, the controller shuts down andwaits 4 seconds before restarting switching.
• Brown−Out: the controller includes a brown−outcircuit with a validation timer which safely stops thecontroller in the event that the input voltage is too low.The device will automatically restart if the line recovers.
• Cycle−by−cycle peak current limit: when the currentsense voltage exceeds the internal threshold VILIM, theMOSFET is turned off for the rest of the switching cycle.
• Winding Short−Circuit Protection: an additionalcomparator with a short LEB filter (tBCS) senses the CSsignal and stops the controller if VCS reaches 1.5 xVILIM. For noise immunity reasons, this comparator isenabled only during the main LEB duration tLEB.
• Output Short−circuit protection: If a very lowvoltage is applied on ZCD pin for 90 ms (nominal), thecontrollers assume that the output or the ZCD pin isshorted to ground and enters shutdown. The auto−restart version (B suffix) waits 4 seconds, then thecontroller restarts switching. In the latched version (Asuffix), the controller is latched as long as VCC staysabove the VCC(reset) threshold.
• Step dimming: Each time the IC detects a brown−outcondition, the output current is decreased by discrete steps.
During the on−time of the MOSFET, the bulk voltageVbulk is applied to the magnetizing and leakage inductors Lpand Lleak and the current ramps up.
When the MOSFET is turned−off, the inductor currentfirst charges Clump. The output diode is off until the voltageacross Lp reverses and reaches:
Nsp�Vout � Vf� (eq. 1)
The output diode current increase is limited by the leakageinductor. As a consequence, the secondary peak current isreduced:
ID,pk �IL,pk
Nsp(eq. 2)
The diode current reaches its peak when the leakage inductoris reset. Thus, in order to accurately regulate the outputcurrent, we need to take into account the leakage inductorcurrent. This is accomplished by sensing the clampingnetwork current. Practically, a node of the clamp capacitoris connected to Rsense instead of the bulk voltage Vbulk.Then, by reading the voltage on the CS pin, we have animage of the primary current (red curve in Figure 43).
When the diode conducts, the secondary current decreaseslinearly from ID,pk to zero. When the diode current has
turned off, the drain voltage begins to oscillate because ofthe resonating network formed by the inductors (Lp+Lleak)and the lump capacitor. This voltage is reflected on theauxiliary winding wired in flyback mode. Thus, by lookingat the auxiliary winding voltage, we can detect the end of theconduction time of secondary diode. The constant currentcontrol block picks up the leakage inductor current, the endof conduction of the output rectifier and controls the draincurrent to maintain the output current constant.
We have:
Iout �VREF
2NspRsense(eq. 3)
The output current value is set by choosing the senseresistor:
Rsense �Vref
2NspIout(eq. 4)
From Equation 3, the first key point is that the outputcurrent is independent of the inductor value. Moreover, theleakage inductance does not influence the output currentvalue as the reset time is taken into account by the controller.
time
time
Figure 43. Flyback Currents and Auxiliary Winding Voltage in DCM
Internal Soft−StartAt startup or after recovering from a fault, there is a small
internal soft−start of 40 �s.In addition, during startup, as the output voltage is zero
volts, the demagnetization time is long and the constant
current control block will slowly increase the peak currenttowards its nominal value as the output voltage grows.Figure 44 shows a soft−start simulation example for a 9 WLED power supply.
Figure 44. Startup Simulation Showing the Natural Soft−start
0
4.00
8.00
12.0
16.0
1
0
200m
400m
600m
800m
2
604u 1.47m 2.34m 3.21mtime in seconds
4.07m
0
200m
400m
600m
800m
3
4
Iout
VCS
Vout
VControl
(A)
(V)
(V)
Cycle−by−Cycle Current LimitWhen the current sense voltage exceeds the internal
threshold VILIM, the MOSFET is turned off for the rest of theswitching cycle (Figure 45).
Winding and Output Diode Short−Circuit ProtectionIn parallel with the cycle−by−cycle sensing of the CS pin,
another comparator with a reduced LEB (tBCS) and a higherthreshold (1.5 V typical) is able to sense windingshort−circuit and immediately stops the DRV pulses. Thecontroller goes into auto−recovery mode in version B.
In version A, the controller is latched. In latch mode, theDRV pulses stop and VCC ramps up and down. The circuitun−latches when VCC pin voltage drops below VCC(reset)threshold.
Figure 45. Winding Short Circuit Protection, Max. Peak Current Limit Circuits
S
R
Q
CS
Rsense
LEB1 +
−
S
R
Q
VCC
aux
Vccmanagement
Vdd
grandreset
DRV
Ipkmax
PWMreset
VCCstop
+
−
LEB2 WOD_SCP
Vcontrol
+
−
STOP
from Fault Management Block
OVP
UVLO
S
R
Q
grandreset
OVP
8_HICC
OFF WOD_SCP
latch
latch
8_HICC
VILIMIT
VCS(stop)
Q
Q
Q
Step DimmingThe step dimming function decreases the output current
from 100% to 5% of its nominal value in discrete steps.There are 5 steps in total. Table 4 shows the different stepsvalue and the corresponding output current set−point. Eachtime a brown−out is detected, the output current is decreasedby decreasing the reference voltage VREF setting the outputcurrent value.
When the 5% dimming step is reached, if a brown−outevent occurs, the controller restarts at 100% of the outputcurrent.
Table 4. DIMMING STEPS
Dimming Step Iout Perceived Light
ON 100% 100%
1 70% 84%
2 40% 63%
3 25% 50%
4 10% 32%
5 5% 17%
Note:The power supply designer must ensure that VCC stays
high enough when the light is turned−off to let the controllermemorize the dimming step state.
The power supply designer should use a split VCC circuitfor step dimming with a capacitor allowing providingenough VCC for 1 s (47 �F to 100 �F capacitor).
The step dimming state is memorized by the controlleruntil VCC crosses VCC(reset).
VCC Over Voltage Protection (Open LED Protection)If no output load is connected to the LED power supply,
the controller must be able to safely limit the output voltageexcursion.
In the NCL30081, when the VCC voltage reaches theVCC(OVP) threshold, the controller stops the DRV pulses andthe 4−s timer starts counting. The IC re−start switching afterthe 4−s timer has elapsed as long as VCC ≥ VCC(on). This isillustrated in Figure 48.
Figure 48. Open LED Protection Chronograms
0
10.0
20.0
30.0
40.0
1
0
10.0
20.0
30.0
40.0
2
0
200m
400m
600m
800m
3
1.38 3.96 6.54 9.11 11.7time in seconds
0
2.00
4.00
6.00
8.00
4
VCC(on)
VCC(OVP)
VCC(off)
Vout
Iout
VCC
OVP
(V)
(A)
(V)
(V)
Valley LockoutQuasi−Square wave resonant systems have a wide
switching frequency excursion. The switching frequencyincreases when the output load decreases or when the inputvoltage increases. The switching frequency of such systemsmust be limited.
The NCL30081 changes valley as the input voltageincreases and as the output current set−point is varied(thermal fold−back and step dimming). This limits theswitching frequency excursion. Once a valley is selected,the controller stays locked in the valley until the input
voltage or the output current set−point varies significantly.This avoids valley jumping and the inherent noise caused bythis phenomenon.
The input voltage is sensed by the VIN pin. The internallogic selects the operating valley according to VIN pinvoltage (Figure 49) and the dimming state imposed by theStep Dimming feature.
By default, when the output current is not dimmed, thecontroller operates in the first valley at low line and in thesecond valley at high line.
Zero Crossing Detection BlockThe ZCD pin allows detecting when the drain−source
voltage of the power MOSFET reaches a valley.A valley is detected when the voltage on pin 1 crosses
below the VZCD(THD) internal threshold.At startup or in case of extremely damped free
oscillations, the ZCD comparator may not be able to detect
the valleys. To avoid such a situation, the NCL30081features a Time−Out circuit that generates pulses if thevoltage on ZCD pin stays below the VZCD(THD) thresholdfor 6.5 �s.
The time−out also acts as a substitute clock for the valleydetection and simulates a missing valley in case of toodamped free oscillations.
Figure 50. Time−out Chronograms
43
14
12
15
16
17
low
high
Clk
TimeOut
low
high
low
high
low
high
ZCD comp
2nd,
VZCD
The 3rd valley is not detectedby the ZCD comp
Time−out circuit adds a pulse toaccount for the missing 3rd valley
The 2nd valley is detectedBy the ZCD comparator
VZCD(THD)
The 3rd valleyis validated
3rd
Normally with this type of time−out function, in the eventthe ZCD pin or the auxiliary winding is shorted, thecontroller could continue switching leading to improperregulation of the LED current. Moreover during an outputshort circuit, the controller will strive to maintain constantcurrent operation.
To avoid these scenarios, a protection circuit consisting ofa comparator and secondary timer starts counting when theZCD voltage is below the VZCD(short) threshold. If this timerreaches 90 ms, the controller detects a fault and shutdown.The auto−restart version (B suffix) waits 4 seconds, then thecontroller restarts switching. In the latched version(A suffix), the controller is latched as long as VCC staysabove the VCC(reset) threshold.
Line Feed−forwardBecause of internal and external propagation delays, the
MOSFET is not turned−off immediately when the currentset−point is reached. As a result, the primary peak current isslightly higher than expected resulting in a small outputcurrent error which can be compensated for duringcomponent selection.
Normally this error would increase if the input linevoltage increased because the slew rate through the primaryinductance would increase. To compensate the peak currentincrease brought by the variation, a positive voltageproportional to the line voltage is added to the current sensesignal. The amount of offset voltage can be adjusted usingthe RLFF resistor as shown in Figure 51. The offset voltageis applied only during the MOSFET on−time and when Ioutis above 6% of the nominal output current.
Bulk rail
VIN
CS
Q_drv
Offset_OK
Figure 51. Line Feed−forward Schematic
VDD
ICS(offset) RLFF
Rsense
Brown−outIn order to protect the supply against a very low input
voltage, the NCL30081 features a brown−out circuit with afixed ON/OFF threshold. The controller is allowed to startif a voltage higher than 1 V is applied to the VIN pin and
shuts−down if the VIN pin voltage decreases and staysbelow 0.9 V for 50 ms nominal. Exiting a brown−outcondition overrides the hiccup on VCC (VCC does not waitto reach VCC(off)) and the IC immediately goes into startupmode (ICC = ICC(start)).
CS Pin Short Circuit ProtectionNormally, if the CS pin or the sense resistor is shorted to
ground, the Driver will not be able to turn off, leading topotential damage of the power supply. To avoid this, theNCL30081 features a circuit to protect the power supply
against a short circuit of the CS pin. When the MOSFET ison, if the CS voltage stays below VCS(low) after the adaptiveblanking timer has elapsed, the controller shuts down andwill attempt to restart on the next VCC hiccup.
+
−
CS
Q_drv
CS_short
S
R
Q
UVLOBO_NOK
AdaptativeBlanking Time
Figure 54. CS Pin Short Circuit Protection Schematic
Q
VCS(low)
VVIN
Fault Management
OFF ModeThe circuit turns off whenever a major condition prevents
it from operating:• Incorrect feeding of the circuit: “UVLO high”. The
UVLO signal becomes high when VCC drops belowVCC(off) and remains high until VCC exceeds VCC(on).
• VCC OVP
• Output diode short circuit protection: “WOD_SCPhigh”
• Output / Auxiliary winding Short circuit protection:“Aux_SCP high”
• Die over temperature (TSD)
• Brown−Out: “BO_NOK” high
• Pin CS short circuited to GND: “CS_short high”
In this mode, the DRV pulses are stopped and thecontroller turn−off some circuits to decrease the internalconsumption. VCC voltage decrease through the controllerown consumption (ICC1).
For the output diode short circuit protection, the output /aux. winding short circuit protection and the VCC OVP, thecontroller waits 4 seconds (auto−recovery timer) and theninitiates a startup sequence (VCC ≥ VCC(on)) beforere−starting switching.
Latch ModeThis mode is activated by the output diode short−circuit
protection (WOD_SCP) and the Aux_SCP in version Aonly.
In this mode, the DRV pulses are stopped and thecontroller is latched. There are hiccups on VCC.
Controller is reset, ICC = ICC(start)Controller is ON, DRV is not switchingNormal switchingNo switching, ICC = ICC1, waiting for VCC to decrease to VCC(off)the auto−recovery timer is counting, VCC is ramping up and down between VCC(on) and VCC(off)
Controller is reset, ICC = ICC(start)Controller is ON, DRV is not switchingNormal switchingNo switching, ICC = ICC1, waiting for VCC to decrease to VCC(off)the auto−recovery timer is counting, VCC is ramping up and down between VCC(on) and VCC(off)Controller is latched off, VCC is ramping up and down between VCC(on) and VCC(off),only VCC(reset) can release the latch.
NOTES:1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, ORGATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS DAND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
c
STYLE 2:PIN 1. EMITTER 2
2. BASE 13. COLLECTOR 14. EMITTER 15. BASE 26. COLLECTOR 2
STYLE 3:PIN 1. ENABLE
2. N/C3. R BOOST4. Vz5. V in6. V out
STYLE 4:PIN 1. N/C
2. V in3. NOT USED4. GROUND5. ENABLE6. LOAD
XXX M�
�
XXX = Specific Device CodeA =Assembly LocationY = YearW = Work Week� = Pb−Free Package
STYLE 5:PIN 1. EMITTER 2
2. BASE 23. COLLECTOR 14. EMITTER 15. BASE 16. COLLECTOR 2
2. DRAIN3. SOURCE4. DRAIN5. DRAIN6. HIGH VOLTAGE GATE
STYLE 10:PIN 1. D(OUT)+
2. GND3. D(OUT)−4. D(IN)−5. VBUS6. D(IN)+
1
1
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to device data sheetfor actual part marking. Pb−Free indicator, “G” or microdot “�”, may or may not be present.
XXXAYW�
�
1
STANDARDIC
XXX = Specific Device CodeM = Date Code� = Pb−Free Package
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