Low Power High Performance Multiplier C. N.Marimuthu 1 , P. Thangaraj 2 , 1 HOD – E C E, Maharaja Engineering College, Avinashi, Anna University, 2 Professor & Head, CT Dept, Kongu Engineering College, Perundurai, Anna University, Tamil nadu , India [email protected]1 & [email protected]2 Abstract There are different entities that one would like to optimize when designing a VLSI circuit. These entities can often not be optimized simultaneously, only improve one entity at the expense of one or more others The design of an efficient integrated circuit in terms of power, area, and speed simultaneously, has become a very challenging problem. Power dissipation is recognized as a critical parameter in modern VLSI design field. In Very Large Scale Integration, Low power VLSI design is necessary to meet MOORE’S law and to produce consumer electronics with more back up and less weight. Multiplication occurs frequently in finite impulse response filters, fast Fourier transforms, discrete cosine transforms, convolution, and other important DSP and multimedia kernels. The objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of total power dissipation. In this paper, we propose a high speed low-power multiplier adopting the new SPST implementing approach. This multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. The modified booth encoder will reduce the number of partial products generated by a factor of 2. The SPST adder will avoid the unwanted addition and thus minimize the switching power dissipation. The proposed high speed low power multiplier can attain 30% speed improvement and 22% power reduction in the modified booth encoder when compared with the conventional array multipliers. Keywords: array multiplier, booth encoder, low power, spurious power suppression technique 1. Introduction Power dissipation is recognized as a critical parameter in modern VLSI design field. To satisfy MOORE’S law and to produce consumer electronics goods with more backup and less weight, low power VLSI design is necessary. Dynamic power dissipation which is the major part of total power dissipation is due to the charging and discharging capacitance in the circuit. The golden formula for calculation of dynamic power dissipation is Pd = C L V 2 f. Power reduction can be achieved by various manners. They are reduction of output Capacitance C L , reduction of power supply voltage V, reduction of switching activity and clock frequency f. Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors today, especially since the media processing took off. In the past multiplication was generally implemented via a sequence of addition, subtraction, and shift operations. Multiplication can be considered as a series of repeated additions. The number to be added is the multiplicand, the number of times that it is added is the multiplier, and the result is the product. Each step of addition generates a partial product. In most computers, the operand usually contains the same number of bits. When the operands are interpreted as integers, the product is generally twice the length of operands in order to preserve the information content. This repeated addition method that is suggested by the arithmetic definition is slow that it is almost always replaced by an algorithm that makes use of positional representation. It is possible to decompose multipliers into two parts. The first part is dedicated to the generation of partial products, and the second one collects and adds them. The basic multiplication principle is two fold i.e, evaluation of partial products and accumulation of the shifted partial products. It is performed by the successive additions of the columns of the shifted partial product matrix. The ‘multiplier’ is successfully shifted and gates the appropriate bit of the ‘multiplicand’. The delayed, gated instance of the multiplicand must all be in the same column of the shifted partial product matrix. They are then added to form the product bit for the particular form. Multiplication is therefore a multi operand operation. To extend the multiplication to both signed and unsigned ICGST-PDCS, Volume 8, Issue 1, December 2008 31
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Nasal airway obstruction and its management
Dr. T. Balasubramanian
6/3/2010 Otolaryngology online drtbalu
Nasal air way obstruction and its management
Introduction:
Nasal obstruction is an important symptom of many underlying disorders, and is the
most common cause for visiting an otolaryngologist. It should be borne in mind that
nasal obstruction is a symptom and not a diagnosis. These patients hence should be
evaluated for both subjective / objective nasal obstruction. Nasal patency these days
can be evaluated objectively based on the anatomy of the nasal cavity and physiology
of nasal air flow which can be studied using a Rhinomanometer.
Subjective feeling of nasal block could be due to the following factors:
1. Sensitivity of pressure receptors in the nose
2. Sensitivity of thermal receptors in the nose
3. Sensitivity of pain receptors in the nose
4. Presence of excessive secretions in the nose
The cause for nasal obstruction is considered to be multifactorial which includes both
subjective and objective causes.
Anatomic causes of nasal block:
Nasal valve area problems: Nasal valve area is considered to be the narrowest
portion of the human airway. Anatomically it has two components i.e. External and
internal nasal valves. The anatomy of internal nasal valve was first described by
Mink in 1903.
Boundaries of internal nasal valve include:
1. Dorsal portion of nasal septum medially
2. Inner caudal edge of upper lateral cartilage laterally
3. Anterior head of inferior turbinate posteriorly
The internal nasal valve area is supposedly the narrowest portion of human airway
has a cross sectional area of approximately 40 – 60 mm2. This area accounts for
nearly 2/3 of the whole airway resistance. Hence collapse / stenosis of this area
accounts for one of the commoner causes of nasal block.
External nasal valve is also known as nasal vestibule. It is bounded by the caudal
edge of the lateral crus of the lower lateral cartilage, fibrofatty tissue over the ala and
the membranous septum.
Diagram showing the nasal valve areas
The nasal vestibule should be considered to be the first component of the nasal
resistance mechanism. If the nasal airflow rate exceeds 30 litres / minute, the
vestibule of nose collapses causing a reduction in the rate of nasal airflow. This
collapse of ala increases the nasal resistance.
On inspiration, the increased velocity of air flowing through the nasal valve area will
cause a drastic decrease in the introluminal pressure causing a vacuum effect on the
upper lateral cartilages. This inward pull causes collapse of upper lateral cartilage
(Bernoulli's principle). Total collapse of the internal nasal valve area duing this
scenario is prevented only by the reselience of the upper and lower lateral cartilages.
Collapse of external nasal valve area (alar area) is by contraction of dilator nari
muscles during inspiration. During expiration the positive pressure prevailing inside
the nasal cavity keeps the nasal valve area open.
Causes of nasal obstruction:
1. Previous trauma / rhinoplasty surgical procedure are the common causes of
nasal obstruction due to weakening of nasal valves
2. If there is associated nasal septal deviation then nasal obstruction becomes
exponentially increased
3. Mucociliary clearance mechanism in patients with deviated nasal septum is
slowed considerably when compared to that of normal individuals. Stagnant
secretions inside the nasal cavity may aggravate nasal obstruction
4. Penumatization of middle turbinate (Concha bullosa) an anatomical variant can
cause significant amount of obstruction in the middle meatal area. Massive concha
may cause middle meatal nasal obstructive syndrome leading on to symptoms like
headache, nasal block and anosmia. Commonly majority of these patients also have
deviated nasal septum which may aggravate nasal block.
5. Neuromuscular causes like facial palsy and aging. Facial palsy may cause
paralysis of dilator naris leading on to nasal obstruction. Aging on the other hand
could weaken the fibroareolar tissues present in the lateral nasal wall leading to
collapse of nasal valve area leading on to nasal obstruction.