NASA RTSX-SU Test Update May 10 th, 2006 Presented by Daniel Elftmann.

NASA RTSX-SU Test Update

May 10th, 2006

Presented by Daniel Elftmann

2May 10th, 2006NASA RTSX-SU KU3/KU4 Test Update

NASA RTSX-SU Tests Overview

KU1/KU2 KM1/KM2 KM3/KM4 KU3/KU4

Part # RTSX32SU - CQ208 RT54SX32S - CQ208 RT54SX32S - CQ208 RTSX32SU - CQ208

Package CQ208 CQ208 CQ208 CQ208

Foundry UMC MEC MEC UMC

Silicon Rev Original PolyResize

Algo Original New Modified New UMA

Software SAL

Quantity 300 300 300 300

Pattern NASA1 NASA1 NASA1 NASA2

Definitions:

Modified New Algorithm = Targets low current antifuses; increase soak timeUMA (UMC Modified Algorithm) = Targets low current antifuses; increase soak timeSAL (S-Antifuse Loading) = Reduces peak currents by adding capacitanceNASA2 = Pattern that focuses on single and double cases of S-Antifuses and B-Antifuses


KU3/4 - Testing Conditions

Operating Temperature LTOL: TA = -55ºC TJ = -20ºC HTOL: TA = 125ºC TJ = 146ºC

Stimulus for DUTs are generated by the NASA Driver card on each burn-in board CLKA / CLKB = 8 MHz (HTOL) CLKA / CLKB = 16 MHz (LTOL)

Power Supplies NASA Driver card = 5.0V VCCA = 2.5V to 3.0V (view Test Plan Summary) VCCI = 4.0V


KU3/4 - Test Plan Summary

Cumulative Hours Step

KU3 (150 units) KU4 (150 units)

TA (ºC) VCCA (V) TA (ºC) VCCA (V)

250 1 -55 2.50 125 2.50

500 2 -55 2.50 125 2.50

750 3 125 2.50 -55 2.50

1,000 4 125 2.50 -55 2.50

1,250 5 -55 2.75 125 2.75

1,500 6 -55 2.75 125 2.75

1,750 7 125 2.75 -55 2.75

2,000 8 125 2.75 -55 2.75

2,250 9 -55 3.00 125 3.00

2,500 10 -55 3.00 125 3.00

2,750 11 125 3.00 -55 3.00

3,000 12 125 3.00 -55 3.00


KU3/4 - Test Vehicle & Device Utilization

KU3/4 Test Vehicle InformationDevice: RTSX32SU – CQ208Wafer Lot / Date code: D1JW21 / 0519Per lot size: 150 + 2 (spares) + 1 (control unit)

Device Utilization Post-Combiner device utilization:

SEQUENTIAL Used: 1080 Total: 1080 (100.00%)

COMB Used: 1800 Total: 1800 (100.00%)

LOGIC Used: 2880 Total: 2880 (100.00%) (seq+comb)

IO w/ Clocks Used: 34 Total: 170

CLOCK Used: 2 Total: 2

HCLOCK Used: 0 Total: 1

IO Config (No internal pullup/down, all high slew) 2 clkbufs – TTL 12 outbufs – TTL 10 outbufs – CMOS 10 outbufs – PCI


KU3/4 - Antifuse Utilization

Antifuse

Type

No. of Utilized

AntifusesAntifuse location

Total Dynamic Antifuses

(11,114)

F 2880 Antifuse between freeway & output track

G 0 Antifuse between output track & 2nd, 3rd, & 4th freeway on the net

H 0 Antifuse between two horizontal tracks

V 0 Antifuse between two vertical tracks

W 7 Antifuse between horizontal segment & 2nd freeway on the net

X 1779 Antifuse between horizontal segment & freeway

B 2672 Antifuse between Local Track and input

S 2816 Antifuse between output track & input (semi-direct)

I 928 Antifuse between horizontal segment & input

K 32 Antifuse between input & horizontal NCLK0 or NCLK1, or QCLK

Total Static

Antifuses

(24,556)

J 18891 Antifuse between input & horizontal NVCC or NGND

M 32 Antifuse for I/O configuration options

Q 0 Silicon Signature antifuse in silicon signature words

T 0Antifuse between output track & input that is used early in programming sequence to tie-off floating output track

Y 5169 Antifuse between horizontal segment & vertical NVCC or NGND

Z 464 Antifuse between freeway & horizontal NVCC or NGND

• Single S-Antifuses nets = 0 (SAL eliminated 1080 Single S-Antifuse nets)• Nets with Single B-Antifuse inputs = 896• Critical K-Antifuse = 0


KU3/4 - FIT Rate Calculations

High Perceptivity

Medium Perceptivity

Low Perceptivity

(Note: Calculator can be obtained from Actel upon request)


KU3/4 - Test Vehicle Design(Combinatorial Delay Circuit)

All Combinatorial (C-Cells) logic utilized in perceptive delay line circuits to achieve both high Single S-antifuse and Double S-Antifuse count Single S-Antifuses will be eliminated by SAL Designer Software enhancement!!! Common delay line input (CLKA) with 16 delay line outputs Circuit is perceptive to shifts in delay for any utilized B-Antifuse or S-Antifuse

INVD DB

1

0

1

0

1

0

D0

D1

D2

D3

A0

B0

A1

B1

A

Y

Double B-Antifuse (DB) CMFC Macro Function

1

0

1

0

1

0

D0

D1

D2

D3

A0

B0

A1

B1

A

Y

Single B-Antifuse (SB) CMFE Macro Function

SB DB SB DBCLKA


KU3/4 - Combinatorial Delay Circuit ChipEdit Layout

Type 1 SuperCluster12 of these


Cluster 1 Cluster 1 Cluster 2 Cluster 1

x 4x 12

Delay line length 30 x 4 = 120 Delay line length 30 x 3 = 90


KU3/4 - Test Vehicle Design(Sequential Delay Circuit)

Sequential (R-Cells) logic utilization to achieve high S-Antifuse count Single S-Antifuse all eliminated by SAL Designer Software enhancement!!! Circuit acts like dominoes

CLKB sets the line low by making CLR of Q1 active and propagates to the rest of the line

CLKB sets the line high by de-activating CLR of Q1, making SET active and propagates to the rest of the line

Common delay line input (CLKB) with 16 delay line outputs

C C C C

C R C C C

C C C C

rcell_in

rcell_out1

R-Cell Routing

R R

R

R R

F-X-I or F-S net segmentF-X-I Antifuse net segment

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

DR-cell In

rcell_out(1)

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

rcell_out(2)

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

rcell_out(n-1)

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

Q

QSET

CLR

D

rcell_out(n)

Q1 Q2 Q90

Qn

CLKB


KU3/4 - Sequential Delay CircuitChipEdit Layout



Cluster 1 Cluster 1 Cluster 2 Cluster 1

x 4x 12

Delay line length 30 x 2 = 60 Delay line length 30 x 3 = 90


KU3/4 - ATE Coverage

Static ICCI, ICCA, IPP, IKS, ISV

Delay measurements for falling & rising edges 0.25 ns resolution

VIH & VIL

VOH & VOL

Input Leakage

Output Leakage


KU3/4 – Current Status

KU3 Device Programming – Completed

Programming yield = 158/160 (98.75%) Yield loss was due to “Invalid Electronic Signature”

Tri-temperature Testing – Completed (All Passed) Step 1 ( 0 to 250 hours LTOL) – Completed (All Passed) Step 2 (250 to 500 hours LTOL) – In Progress (due on 05/13)

KU4 Device Programming – In Progress


KU3 (250 hrs LTOL) – ICCA

Measured ICCA for all KU3 Units can be seen in the graph below:

Delta ICCA for all devices post 250 hrs LTOL ranges from -800 uA to 280 uA


KU3 (250hrs LTOL) – ICCI

Measured ICCI for all KU3 Units can be seen in the graph below:

Delta ICCI for all devices post 250 hrs LTOL ranges from -320 uA to 210 uA


KU3 (250 hrs LTOL) – Delta Delay Distribution

Delta delay distribution for all delay lines post 250 hrs LTOL ranges from -0.5 ns to 0.5 ns

NASA RTSX-SU Test Update May 10 th, 2006 Presented by Daniel Elftmann.

Documents

santifuse slide

high santifuse

nasa rtsxsu test update

double santifuse

high single santifuse

utilized bantifuse

silicon signature antifuse

single santifuse nets