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IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 37, NO. 9, SEPTEMBER 2009 1705 Nanoscale Roughness Effects at the Interface of Lithography and Plasma Etching: Modeling of Line-Edge-Roughness Transfer During Plasma Etching George Kokkoris, Vassilios Constantoudis, and Evangelos Gogolides Abstract—We present 3-D modeling results on resist line-edge- roughness (LER) transfer to underlying films during plasma etching. After generating random fractal resist sidewalls with controlled roughness parameters, we model and contrast the nanoscale roughness phenomena for both resist and underlayer sidewalls in a two-layer stack using two different plasma processes in three scenarios: 1) pattern transfer; 2) resist trimming; and 3) resist trimming followed by pattern transfer. In the pattern transfer process, etching is considered ion driven and anisotropic. The protrusions of the rough, trimmed or nontrimmed, resist sidewall act as a shadowing mask for the incident ions. It is found that shadowing of ions is enough to induce the, well known by experiments, striations at the sidewalls of both the underlayer and the resist. Pattern transfer induces a decrease of rms roughness but has no important effects on the correlation length. In the trimming process, the evolution of the resist sidewall is modeled with an isotropic etching process not affecting the underlayer. The trimming process causes a decrease of the rms value of the resist sidewall and an increase of its correlation length and roughness exponent. For sufficiently long trimming times, the change of LER parameters becomes less intense. In the case of trimming followed by pattern transfer, the striations of the underlayer widen with trimming time, and pattern transfer further reduces all LER parameters. The effect of trimming on the rms roughness of the underlayer is important in the case of initially anisotropic resist sidewall. For both trimming and pattern transfer, a stronger relative reduction on rms roughness of both the resist and the underlayer sidewalls is obtained for smaller correlation length and larger rms roughness of the initial resist. Index Terms—Etching, modeling, plasma materials-processing applications, rough surfaces. I. I NTRODUCTION P LASMA ETCHING and lithography are two of the main driving forces in the amazing race of semiconductor manu- facturing toward devices with features at nanoscale dimensions, due to their proven ability to print out patterns below 50 nm. The success of these processes is evaluated with the fidelity Manuscript received January 22, 2009; revised March 31, 2009 and May 15, 2009. First published July 28, 2009; current version published September 10, 2009. This work was supported in part by the E.U. FP7-ICT Project (STREP) MD3 “Material Development for Double exposure and Double patterning.” The authors are with the Institute of Microelectronics, National Center for Scientific Research “Demokritos,” 15310 Attiki, Greece (e-mail: gkok@imel. demokritos.gr; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPS.2009.2024117 of the dimensions of the fabricated patterns to the nominal ones. When this pattern is a linear feature (line), as is usual in integrated circuit manufacturing, the critical dimension (CD) to be reproduced reliably is the width of the line. Due to the random character of lithography and plasma etching processes, deviations of the line widths from their nominal value are expected to occur along the line at the nanoscale. In the jargon of semiconductor industry, these deviations are called line width roughness (LWR) and are, not surprisingly, related to the deviations of the edge points of the line from their linear fit. The latter are called line edge roughness (LER) due to their appearance in 2-D top–down images obtained by CD scanning electron microscopy (CD-SEM) [1]. The 3-D origin of both LWR and LER is the roughness of the line sidewalls. As the CD values of line features are shrinking below 50 nm, line sidewall roughness, which is also at the nanoscale, becomes an important fraction of feature width and, thus, a candidate factor for degradation of device performance. Indeed, several recent experimental and modeling works indicated the harmful effects that LER (or LWR) may have on the voltage threshold shift or on the OFF-state leakage current in a typical MOSFET or a more advanced FinFET device as CD values decrease, making the LER/LWR issue one of the great challenges for next-generation lithography [2]– [15]. This realization triggered the proliferation of LER/LWR studies during the last years, with the vast majority of these dealing with the resist LER just after lithography and before plasma etching steps were applied. This focus was based on the assumption that the etching steps did not modify signif- icantly LER during pattern transfer. However, recent experi- mental studies have shown that this may not be the case, and consequently, more attention should be paid on the effects of plasma etching on LER during the transfer of resist feature to underlayer films used in the fabrication of transistor gates. A first indication of LER reduction during plasma etching was given by Namatsu et al. [16]. Next, Mahorowala et al. [17] and Goldfarb et al. [18] performed measurements of sidewall roughness with a conventional atomic force microscope (AFM) and showed that the postlithography plasma etching steps ap- plied for bottom antireflective coating opening and subsequent substrate removal may cause reduction of the roughness on resist and substrate sidewalls after etching with respect to the initial sidewall roughness of the developed resist feature. 0093-3813/$26.00 © 2009 IEEE
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Nanoscale Roughness Effects at the Interface of Lithography and Plasma Etching: Modeling of Line-Edge-Roughness Transfer During Plasma Etching

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Page 1: Nanoscale Roughness Effects at the Interface of Lithography and Plasma Etching: Modeling of Line-Edge-Roughness Transfer During Plasma Etching

IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 37, NO. 9, SEPTEMBER 2009 1705

Nanoscale Roughness Effects at the Interface ofLithography and Plasma Etching: Modeling

of Line-Edge-Roughness TransferDuring Plasma Etching

George Kokkoris, Vassilios Constantoudis, and Evangelos Gogolides

Abstract—We present 3-D modeling results on resist line-edge-roughness (LER) transfer to underlying films during plasmaetching. After generating random fractal resist sidewalls withcontrolled roughness parameters, we model and contrast thenanoscale roughness phenomena for both resist and underlayersidewalls in a two-layer stack using two different plasma processesin three scenarios: 1) pattern transfer; 2) resist trimming; and3) resist trimming followed by pattern transfer. In the patterntransfer process, etching is considered ion driven and anisotropic.The protrusions of the rough, trimmed or nontrimmed, resistsidewall act as a shadowing mask for the incident ions. It is foundthat shadowing of ions is enough to induce the, well known byexperiments, striations at the sidewalls of both the underlayer andthe resist. Pattern transfer induces a decrease of rms roughnessbut has no important effects on the correlation length. In thetrimming process, the evolution of the resist sidewall is modeledwith an isotropic etching process not affecting the underlayer. Thetrimming process causes a decrease of the rms value of the resistsidewall and an increase of its correlation length and roughnessexponent. For sufficiently long trimming times, the change ofLER parameters becomes less intense. In the case of trimmingfollowed by pattern transfer, the striations of the underlayer widenwith trimming time, and pattern transfer further reduces allLER parameters. The effect of trimming on the rms roughnessof the underlayer is important in the case of initially anisotropicresist sidewall. For both trimming and pattern transfer, a strongerrelative reduction on rms roughness of both the resist and theunderlayer sidewalls is obtained for smaller correlation length andlarger rms roughness of the initial resist.

Index Terms—Etching, modeling, plasma materials-processingapplications, rough surfaces.

I. INTRODUCTION

P LASMA ETCHING and lithography are two of the maindriving forces in the amazing race of semiconductor manu-

facturing toward devices with features at nanoscale dimensions,due to their proven ability to print out patterns below 50 nm.The success of these processes is evaluated with the fidelity

Manuscript received January 22, 2009; revised March 31, 2009 and May 15,2009. First published July 28, 2009; current version published September 10,2009. This work was supported in part by the E.U. FP7-ICT Project (STREP)MD3 “Material Development for Double exposure and Double patterning.”

The authors are with the Institute of Microelectronics, National Center forScientific Research “Demokritos,” 15310 Attiki, Greece (e-mail: [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPS.2009.2024117

of the dimensions of the fabricated patterns to the nominalones. When this pattern is a linear feature (line), as is usualin integrated circuit manufacturing, the critical dimension (CD)to be reproduced reliably is the width of the line. Due to therandom character of lithography and plasma etching processes,deviations of the line widths from their nominal value areexpected to occur along the line at the nanoscale. In the jargonof semiconductor industry, these deviations are called linewidth roughness (LWR) and are, not surprisingly, related to thedeviations of the edge points of the line from their linear fit.The latter are called line edge roughness (LER) due to theirappearance in 2-D top–down images obtained by CD scanningelectron microscopy (CD-SEM) [1].

The 3-D origin of both LWR and LER is the roughnessof the line sidewalls. As the CD values of line features areshrinking below 50 nm, line sidewall roughness, which is alsoat the nanoscale, becomes an important fraction of featurewidth and, thus, a candidate factor for degradation of deviceperformance. Indeed, several recent experimental and modelingworks indicated the harmful effects that LER (or LWR) mayhave on the voltage threshold shift or on the OFF-state leakagecurrent in a typical MOSFET or a more advanced FinFETdevice as CD values decrease, making the LER/LWR issueone of the great challenges for next-generation lithography [2]–[15]. This realization triggered the proliferation of LER/LWRstudies during the last years, with the vast majority of thesedealing with the resist LER just after lithography and beforeplasma etching steps were applied. This focus was based onthe assumption that the etching steps did not modify signif-icantly LER during pattern transfer. However, recent experi-mental studies have shown that this may not be the case, andconsequently, more attention should be paid on the effects ofplasma etching on LER during the transfer of resist feature tounderlayer films used in the fabrication of transistor gates. Afirst indication of LER reduction during plasma etching wasgiven by Namatsu et al. [16]. Next, Mahorowala et al. [17] andGoldfarb et al. [18] performed measurements of sidewallroughness with a conventional atomic force microscope (AFM)and showed that the postlithography plasma etching steps ap-plied for bottom antireflective coating opening and subsequentsubstrate removal may cause reduction of the roughness onresist and substrate sidewalls after etching with respect tothe initial sidewall roughness of the developed resist feature.

0093-3813/$26.00 © 2009 IEEE

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1706 IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 37, NO. 9, SEPTEMBER 2009

Moreover, they found that, in most cases, plasma etching affectsstrongly the sidewall morphology and induces striations on bothresist and substrate sidewalls, which become more distinctiveand well defined when the etching process is more “physical”than “chemical.” The formation of such striations on the side-walls of etched features had also been observed by other groups[16], [19]–[22]. The LER reduction during pattern transferhas been confirmed and investigated more systematically veryrecently by Foucher et al. [23] and Pargon et al. [24], who usedthe new tool of CD-AFM microscope (3-D AFM) for a directmeasurement of the whole sidewall roughness.

The origins of both sidewall striation formation and rough-ness reduction after plasma etching have not been clarifiedyet. As regards striation formation, the proposed interpretationconsiders that plasma first induces striations on resist sidewall,which next becomes the template for striation formation on theunderlayer sidewall [16]–[18], [21], [22]. The appearance ofstriations on the resist sidewall has been attributed to localizedagglomeration of the resist and selective evaporation of itscomponents accompanied with plasma polymer deposition (incase of fluorocarbon plasmas) on the top of the resist feature;the thickness variation of the polymer on the edge whichinduces micromasking and/or the angle dependence of ionsputtering yield coupling with the rough morphology may leadto local variations in the etching yield and hopefully to striationformation [18], [21], [22]. The etching-induced reduction of thesidewall roughness has been related to the more rapid etchingof surface protruding features by ion bombardment, leading tothe sidewall smoothing [24].

The final outcome for the LER transfer during the plasmaetching steps depends on the materials of the stack and theplasma chemistry and conditions; the number of knobs is ratherlarge. A modeling approach could be to focus on a specificstack and specific plasma chemistry and try to find the originand the mechanisms of phenomena. The large number of knobsand the lack of a standard recipe make this focus difficult, eventhough this approach has a potential to quantitative results. Inthis paper, our ambition is to approach the problem of LERtransfer from a different and more generic point of view. Ouraim is to capture the fundamental mechanisms of LER transferwhich are common in all stack materials, plasma chemistries,and conditions. Thus, simple geometric models for both resisttrimming and pattern transfer are applied in a two-layer stackconsisting of the resist and an underlayer. Our expectation is toapproach a complex problem in a complex environment, suchas the plasma environment, with simple ideas.

In particular, we approximate the pattern transfer processwith an anisotropic etching process where both the resist andunderlayer sidewalls are determined only by the shadowing ofthe incident ions by the protrusions of the initial resist sidewall.The initial resist sidewall is modeled with a fractal self-affinesurface whose roughness parameters (rms value, correlationlength, and roughness exponent or fractal dimension) can bevaried at will. This offers us the opportunity to perform athorough examination of the role of the initial postlithographysidewall roughness. In addition, we approximate resist trim-ming, a recently developed technique for the postlithographyreduction of the CD [25], [26], with an isotropic etching process

(a realistic approximation for processes with zero bias), andexamine the effects of trimming time on the sidewall roughnessof both the resist and the post-pattern-transfer underlayer. Theimpact of resist trimming on LER transfer is still unclear andunder investigation [24], [27], [28].

Up to date, the simulation works have considered eitherthe impact of etching process on the sidewall roughness ofpattern features only [29], [30] or the formation of roughnesson the sidewall of an underlayer without taking into accountthe roughness of the resist sidewall [31]. There are also othermodeling approaches which approximate only pattern transferby a phenomenological isotropic movement of the rough edgesof top-down SEM images [32]–[36].

In comparison with previous works, the modeling approachin this paper performs the following: 1) It takes into accountthe full setup of the process, i.e., a rough (and not smooth)resist sidewall on top of an underlayer; 2) takes into accountresist trimming process; and 3) allows thorough examination ofthe role of the initial postlithography sidewall roughness by theproduction of modeled fractal self-affine surfaces.

The rest of this paper is structured as follows. The nextsection describes the modeling methodology. Section III in-cludes the results: In particular, the effects of the etching stepson the sidewall morphologies and on the LER parameters arepresented. The final section summarizes the main conclusionsof this paper.

II. MODELING METHODOLOGY

We consider a stack of two films, with the top one being aresist film patterned with lithography and an underlying film onwhich the resist pattern (a line) should be transferred [Fig. 1(a)].Due to the randomness of lithography, the sidewalls of theresist line are expected to exhibit roughness, and the questionto be addressed is how this roughness is transferred to theunderlayer after the (optional) trimming [Fig. 1(b)] and thepattern transfer process [Fig. 1(c)]. The question is investigatedhere with a modeling approach consisting of three steps shownin the flowchart of Fig. 2 and described in the next sections.

A. Algorithm for the Generation of Model Resist Sidewalls

Several experimental and modeling studies have shown thatthe power spectral density and the height–height correlationfunction of postlithography resist LER exhibit a scale-limitedregion of power law behavior which is the hallmark of fractalself-affine behavior. In addition, the same behavior is shownby experimental horizontal resist surfaces after lithographicdevelopment. Thus, it seems reasonable to model the initialresist sidewall with a (2 + 1)-D surface exhibiting statisticalfractal self-affine behavior for a limited range of scales.

The most usual way of generating such surfaces is a convo-lution algorithm based on the Wiener–Khinchine theorem andinverse fast Fourier transform. More details about this methodcan be found elsewhere [37], [38]. The inputs of the generatingalgorithm are the dimensions of the surface and the roughnessparameters describing it. For fractal self-affine surfaces, a tripletof parameters is considered adequate for their characterization[1], [37], [38]. The first is the rms value w of surface points,

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KOKKORIS et al.: ROUGHNESS EFFECTS AT THE INTERFACE OF LITHOGRAPHY AND PLASMA ETCHING 1707

Fig. 1. Setup of the model and processes. The stack (a) after lithographyand before (optional) trimming, (b) after trimming (isotropic etching) andbefore pattern transfer, and (c) after trimming and pattern transfer (anisotropicetching).

Fig. 2. Flowchart of our modeling approach.

which quantifies the vertical surface fluctuations. The secondis the correlation length ξ indicating the range inside whichthe correlations between surface points are extended and theself-affine symmetry holds. For distances larger than this range,surface points can be considered uncorrelated, and the statisticalquantities describing surface roughness remain invariant. Thethird parameter is the roughness exponent α, which measuresthe relative contribution of high-frequency fluctuations to totalsurface roughness, and is related to the fractal dimension dF of

the surface through the relationship dF = 3 − α. In the gener-ation procedure followed here, all these roughness parameterscan be easily controlled and changed at will. The output of thealgorithm is a random self-affine surface characterized by theroughness parameters determined in the input.

B. Model for the Resist Trimming

The etching of the sidewall by the trimming process isapproximated by an isotropic etching process, which is closeto cases of trimming with zero bias and no polymerizingchemistries (e.g., O2 plasma). The self-affine (2 + 1)-D sur-faces produced, as described in Section II-A, are moving underan isotropic etching rate. The evolution of the morphologydepends only on the local slope of the sidewall surface.

The level set method [39], [40], which is based on thenotion of the implicit functions, is used for the evolution of thesurfaces.

The central mathematical idea of the level set method liesin the consideration that the moving boundary is embedded inthe level set function ϕ and represents a specific contour of ϕ,namely, the zero contour. The basic equation of the methoddescribing the evolution of the level set function is the initialvalue problem

ϕt + F |∇ϕ| = 0, with ϕ(x, t = 0) = g(x) (1)

where g(x) is the initial condition and F at x is generally thecoordinate of velocity on the normal direction of the contourof ϕ passing through x. The solution of (1) requires the initialcondition and the velocity F . Thus, the implementation of thelevel set method in plasma etching problems entails, besides thesolution of (1), several computational tasks [41]. Nevertheless,in our case, due to the isotropy of the etching process, theimplementation is simpler: F is the isotropic etching rate whichis constant for every elementary surface.

C. Model for the Pattern Transfer

The etching during pattern transfer is considered purelyanisotropic, driven by the ions through a sputtering or an ion-enhanced process for both the resist and the underlayer. Iontrajectories are assumed perpendicular to the underlayer, andthe resist sidewall has no slope. The later assumption maybe relaxed by tilting the sidewall for a few degrees, althoughwe report no results here. In addition, the sputtering or ion-enhanced yield of the resist and the underlayer does not dependon the angle of incidence of ions.

The angle dependence of the sputtering yield is ignored forthree reasons. The first is that this dependence is actually notknown. The commonly used dependences have been extractedfor cases where the ions hit the surface of a bulk material witha given angle of incidence [42] and not sidewall protrusionsof varying thickness [see Fig. 3(a)]. Obviously, the sputteringyield depends not only on the local incidence angle of ionsbut also on the mechanical strength of the protrusions definedby their thickness. In this spirit, it has been argued that theetching rate of protruding features is larger than that of recessedones, and this difference has been used for the explanation of

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1708 IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 37, NO. 9, SEPTEMBER 2009

Fig. 3. (a) Cross section of the stack before pattern transfer. With black,the visible-to-ion resist layer at t = 0 is denoted. (b) Thickness of the resistmaterial above the underlayer [for the cross section of (a)], which essentially isthe CHD of the protrusions. (c) Shape of the underlayer after pattern transfer.The shape is identical with the CHD of (b) in the case of unit etching selectivity.

sidewall roughness reduction during ion bombardment [24].The second reason is that what counts for the LER transferprocess is not the local etching rates but their average valuecalculated during the etching of the resist protrusions. Dueto the randomness of the sidewall morphology, it can besupported that this averaging sweeps out the effects of localetching rates and, consequently, the impact of incidence angleon LER transfer. The third reason is that possible inclusionof the angle dependence of the sputtering yield would in-crease the computation time disproportionally to the benefit wemight have.

In the context of this simple model for pattern transfer, themorphology of the resist is defined only by the shadowingof incident ions: Ions reduce the—visible to their trajectory—protrusions of the resist sidewall. In Fig. 3(a), a cross sectionof the stack (resist and underlayer) before pattern transferis shown. The resist evolution during the pattern transfer isaccomplished as follows: A scan from A to C is performed,and the height of the visible-to-ions resist layer is reducedproportionally to the resist etching rate (i.e., for t = 0, the thinblack regions of the resist layer in Fig. 3(a) are removed).

Shadowing of ions also defines the morphology of the un-derlayer. As shown in Fig. 3(a), at point A of the underlayer,etching starts at t = 0, while at point B, etching will startafter the whole thickness of material above B is removed. Thethickness of the resist material above each point from A toC is shown in Fig. 3(b). This thickness function is essentiallythe cumulative height distribution (CHD) function of the resistprotrusions.

In order to explain the methodology for the pattern transfermodel and without the loss of generality, we assume unitselectivity. Then, point A of the underlayer will move a distanceequal to the full resist thickness as no material exists aboveA [Fig. 3(c)]. Point B will only move a distance equal to theresist thickness minus the thickness above B [LB in Fig. 3(b)].As shown in Fig. 3(a) and (b), the shape of the underlayer isidentical to the shape of the CHD of the resist protrusions.

Fig. 4. Two-dimensional CHD of a typical resist sidewall with w = 2 nm,ξ = 5 nm, and α = 0.5. The value of the CHD at a specific point (x, y) is thethickness of the resist material that should be removed for the exhibition of thispoint to ion bombardment. In the case of unit selectivity, this CHD is identicalto the shape of the underlayer sidewall after pattern transfer. Note that x-axisis magnified about 30 times; thus, the shown slope of the underlayer sidewallis not real. Notice the variations of the CHD along the y-axis, which seem toplay the role of mask for the formation of striations on sidewalls during patterntransfer (cf. Section III-A).

Even in cases of nonunit selectivity (as in the results pre-sented in Section III), the shape of the underlayer is a multipleof the CHD of the resist protrusions. Thus, if we constructthe CHD of the resist protrusions along the y-axis, i.e., alongthe resist line, we can straightforwardly predict the shapeof the underlayer sidewall. An example of the combination ofthe CHDs for all the cross sections [Fig. 3(a)] of the resist isshown in Fig. 4: It is essentially a 2-D CHD along both x- andy-axes, exhibiting a wavy structure with wave vector alongthe y-axis. The amplitude of waves is proportional to the rmsroughness of the resist sidewall, and the wavelength is relatedto the correlation length of the initial resist. The formation ofstriations is obvious and comes from wavy variations of theCHD along the y-axis.

Due to the semianalytic component of the algorithm de-scribed earlier, model simulations, despite their 3-D nature, arevery fast even for large sidewall dimensions.

III. RESULTS

Before presenting the results, the conditions of the calcula-tions are summarized. First, concerning the trimming process,a typical trimming rate of 1.5 nm/s was used in the calculations;generally, the magnitude of the etching rate can result fromSEM images or 3-D AFM images for different trimming times.Second, the thicknesses of both films of the stack are consideredequal to 300 nm. The etching selectivity of the underlayerover the resist is 3/1. The roughness parameters of the initialpostlithography resist sidewall are noted by wR,initial, ξR,initial,and αR,initial; those of the underlayer sidewall after patterntransfer are noted by wU,notrim, ξU,notrim, and αU,notrim; andthose of the resist sidewall after trimming are noted by wR,trim,

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KOKKORIS et al.: ROUGHNESS EFFECTS AT THE INTERFACE OF LITHOGRAPHY AND PLASMA ETCHING 1709

Fig. 5. [First row, (a), (b), and (c)] Morphology of the resist sidewall after trimming (if any), [second row, (d), (e), and (f)] the resist sidewall after trimming andpattern transfer, and [third row, (g), (h), and (i)] the underlayer sidewall after trimming and pattern transfer. The roughness parameters of the initial resist sidewallbefore trimming (a) are wR,initial = 2 nm, ξR,initial = 5 nm, and αR,initial = 0.5. Each column shows the effect of pattern transfer, and each row shows theeffect of trimming time (0, 10, and 30 s) on the morphologies. Notice the isotropic character of the resist surfaces after trimming with craters whose diameterincrease with trimming time (first row) as well as the anisotropy of the resist and underlayer after pattern transfer with striations which widen with trimming time(second and third rows).

ξR,trim, and αR,trim, while wU,trim, ξU,trim, and αU,trim standfor the roughness parameters of the underlayer sidewall afterresist trimming and pattern transfer.

A. Effects of Etching Steps on Sidewall Morphologies

The effects of both trimming (isotropic etching) on the mor-phology of the resist sidewall and pattern transfer (anisotropicetching) on the morphology of the resist and underlayer side-walls are shown in Fig. 5. Each column in Fig. 5 includesthe resist sidewall surface after trimming (first row) and afterpattern transfer (second row), as well as the underlayer sidewallsurface after pattern transfer (third row) for a specific trimmingtime. The results for trimming times of 0, 10, and 30 s areshown.

One can easily see that the isotropic etching during trimmingeliminates the high-frequency fluctuations and causes graduallythe formation of craters (holes) on the sidewall surface, whosediameter increases versus trimming time or resist thicknessloss (see first row in Fig. 5). A quantitative assessment of thisbehavior will be given in Section III-B2.

On the contrary to isotropic surfaces after trimming, thesidewalls of the resist and underlayer after anisotropic etchingexhibit anisotropy, which is associated with the formation ofstriations along etching (ion flux) direction; the latter widenwith trimming time (see along the second and the third row).The striations are more well defined on the underlayer side-walls, while on the resist surfaces, the striations are accom-panied with the presence of holes which are not affected bythe anisotropic etching. This finding is a generalization of theresults of our previous modeling work [32] and is in agreementwith several experimental results [16]–[20]. It has to be noticedthat the formation of striations on the underlayer surface isthe result of simple shadowing of ions from resist morphologyand actually follows the fluctuations of the CHD of the resistsidewall along the edge of resist line (see Fig. 4). This meansthat the striations on underlayer sidewall do not seem to requirethe presence of striations on the resist sidewall, which would actas a template for their formation. The resist striations appearin parallel with the striation formation on underlayer duringpattern transfer and cannot be considered having a cause-and-effect relationship with it. This modeling result seems to be in

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agreement with the experimental finding of Mahorowala et al.(see , Figs. 4(b) and 5(b)[17]) according to which striationsoccur on the sidewall of an underlying film (SiO2) evenwhen there is no template for these on the overlaying resistsidewall.

Not surprisingly, the striations on resist sidewall may en-hance and make the striations on the underlayer film morepronounced and well defined, but the very existence of thelatter seems to be a result of simple shadowing of ions by resistsidewall morphology.

Another outcome of Fig. 5 is that the formation of striationsis not affected by the preceding trimming step. Striations existfor all trimming times (third row of Fig. 5). The formation ofstriations is also not affected by the roughness parameters of theresist sidewall before etching [32]. Finally, striation formationis not a result of an angle-dependent sputtering yield, whichundoubtedly could be important when bombarding non-resist-masked and initially flat surfaces with a grazing angle incidention beam [42], [43].

The importance of predicting the structure of the underlayersidewall after pattern transfer is related to the most crucialaspect of LER issue, i.e., its effects on microelectronic andoptoelectronic devices. The 3-D modeling of these effectsrequires a sufficient representation of the gate sidewall afteretching steps. Our modeling results, in harmony with experi-mental ones, show that etching steps induce anisotropy on gatesidewall, which should be taken into account in the modeling ofsidewall roughness effects on electrical transistor performance.

B. Effects of Etching Steps on the Roughness Parameters

1) Impact of Initial Lithography Resist Roughness on EtchedSidewall Roughness: In order to estimate the effects of theroughness parameters of the initial postlithography resist side-wall (wR,initial, ξR,initial, and αR,initial), the roughness param-eters of the underlayer sidewall after pattern transfer (wU,notrim,ξU,notrim, and αU,notrim), the resist sidewall after trimming(wR,trim, ξR,trim, and αR,trim), and the underlayer sidewallafter resist trimming and pattern transfer (wU,trim, ξU,trim,and αU,trim), a series of runs with different initial roughnessparameters for the resist sidewall was performed. In fact, wevaried the initial resist rms roughness wR,initial from 1 to 5 nm,and for each value of wR,initial, two initial correlation lengthsξR,initial (5 and 20 nm) were examined. In all cases, theroughness exponent was kept fixed to 0.5. In addition, the trim-ming time was considered constant and equal to 30 s (the lostthickness was ∼30 × 1.5 = 45 nm). The results of these runsare shown in Fig. 6 and are the averages over ten runs for eachchoice of initial roughness parameters.

Effects of pattern transfer on underlayer roughness: Letus present first the results for the pattern transfer alone withno previous resist trimming step. These are shown with theopen squares in all diagrams of Fig. 6. Fig. 6(a) and (b) showsthe ratios wU,notrim/wR,initial versus wR,initial for ξR,initial =5 nm and ξR,initial = 20 nm, respectively. We can see that, inboth cases and for all wR,initial, the ratio wU,notrim/wR,initial

is clearly lower than 1 (0.25–0.35 for ξR,initial = 5 nm and0.4–0.5 when ξR,initial = 20 nm). This means that, in our mod-

eling approach, the roughness of the underlayer after patterntransfer is much lower than that of the initial postlithographyresist sidewall, and the less rough the resist sidewall is, the lessrough the underlayer sidewall becomes. By the comparison ofthe open symbols in Fig. 6(a) and (b), we conclude that thispattern-transfer-induced LER reduction is more significant atsmall correlation lengths. On the other hand, the increase ofwR,initial causes only a slight reduction of the ratio.

Fig. 6(c) and (d) shows the dependence of the underlayer cor-relation length after pattern transfer ξU,notrim on wR,initial forξR,initial = 5 nm and ξR,initial = 20 nm, respectively. For bothcorrelation lengths, ξU,notrim increases slightly, with wR,initial

remaining close to the initial value ξR,initial particularly forlarge wR,initial.

Effects of trimming process on resist roughness: The re-sults for the dependence of the ratio wR,trim/wR,initial and ofthe ξR,trim on wR,initial are shown in Fig. 6(a) for ξR,initial =5 nm and in Fig. 6(b) for ξR,initial = 20 nm with the fullcircular symbols. Again, wR,trim/wR,initial is lower than one,i.e., trimming reduces resist rms roughness. This reductiondepends strongly on ξR,initial and is larger for small valuesof it [compare Fig. 6(a) and (b)]. In both cases, the values ofwR,trim/wR,initial lie clearly above those after pattern transfer(ratio wU,notrim/wR,initial) and decrease with wR,initial.

In Fig. 6(c) and (d), ξR,trim versus wR,initial for two values ofξR,initial (5 and 20 nm) are shown (full circles again). ξR,trim

increases and gets higher values for both values of ξR,initial.Similarly to what happens to rms ratio, ξR,trim is clearly largerthan ξU,notrim.

Effects of trimming process and pattern transfer on under-layer roughness: The behavior of the ratio wU,trim/wR,initial

versus wR,initial for ξR,initial = 5 nm and 20 nm is shownin Fig. 6(a) and (b) with the full upper triangles. It followsthe behavior of the notrim ratio wU,notrim/wR,initial, withthe values of trim ratio wU,trim/wR,initial being only a littlesmaller than those of wU,notrim/wR,initial. Thus, it seems thatthe resist trimming step has no noticeable effects on LERreduction after pattern transfer. However, as we will show inthe next subparagraph, this conclusion is not generic and de-pends on the isotropy of the initial resist sidewall morphology.Postlithography resist sidewalls with anisotropic morphologyboost significantly the beneficial role of trimming step in LERreduction during pattern transfer.

Fig. 6(c) and (d) shows the dependence of ξU,trim onwR,initial for ξR,initial = 5 nm and 20 nm, respectively. ξU,trim

increases with wR,initial at small ξR,initial, while at higherξR,initial, this increasing trend disappears and ξU,trim becomesalmost independent of wR,initial [see Fig. 6(b)]. In addition,ξU,trim is smaller than ξR,trim, i.e., pattern transfer (anisotropicetching) reduces ξ, and larger than ξU,notrim, i.e., the interven-tion of the resist trimming step increases ξ.

The outcome from the former study regarding the impactof the initial lithography resist roughness is that all etch-ing processes (pattern transfer, trimming, and their sequentialcombination) are more effective on the reduction of w whenξR,initial is lower and/or wR,initial is higher.

2) Impact of Trimming Time: Fig. 7(a)–(c) shows the effectof the trimming process on the roughness parameters of an

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Fig. 6. Effect of postlithography rms roughness wR,initial on the postetched roughness parameters after 30-s trimming. The ratios wR,trim/wR,initial

(full circles), wU,notrim/wR,initial (open squares), and wU,trim/wR,initial (full upper triangles) versus wR,initial are shown for (a) ξR,initial = 5 nm and(b) ξR,initial = 20 nm. The correlation lengths ξR,trim (full circles), ξU,notrim (open squares), and ξU,trim (full upper triangles) are shown versus wR,initial

for (c) ξR,initial = 5 nm and (d) ξR,initial = 20 nm. In all cases, α = 0.5. Notice the following: 1) In all etching processes, we consider trimming, patterntransfer, and their sequential combination, and reduce the rms roughness of the corresponding sidewall (rms ratios in (a) and (b) lower than one); 2) the beneficialimpact of small ξR,initial on reducing all rms ratios [compare (a) with (b)]; 3) trimming increases the correlation length of the resist sidewall, whereas patterntransfer leaves it almost unchanged; and 4) all correlation lengths increase with wR,initial. This increasing trend is less intense when ξR,initial increases to20 nm and seems to cease to exist for ξU,trim.

isotropic resist sidewall (wR,trim, ξR,trim, and αR,trim, fullsquares) and of the underlayer sidewall after trimming andpattern transfer (wU,trim, ξU,trim, and αU,trim, open squares).In fact, Fig. 7(a) shows the ratios wR,trim/wR,initial andwU,trim/wR,initial versus trimming time with wR,initial takenequal to 2 nm. The other roughness parameters are ξR,initial =5 nm and αR,initial = 0.5.

One can see that wR,trim decreases [Fig. 7(a)], while ξR,trim

[Fig. 7(b)] and αR,trim [Fig. 7(c)] increase with trimming time;all changes gradually flatten out. This behavior means that trim-ming (isotropic etching) causes reduction of the perpendicularfluctuations of the resist sidewall (decrease of wR,trim) alongwith the formation of craters whose size enlarges with trimmingtime (increase of ξR,trim). The rise of roughness exponentαR,trim to values close to one after just a few seconds oftrimming reveals the elimination of high-frequency fluctuationsin trimmed surfaces. These results are consistent with the caseof isotropic evolution of rough self-affine curves [32].

Fig. 7 also shows that the step of pattern transfer (anisotropicetching) which follows the trimming process causes a decreaseof all roughness parameters. In all cases, this decrease reducesthe variation of roughness parameters with trimming time. Themost important time-variation reduction appears for the rmsratio wU,trim/wR,initial. Notice also that this ratio exhibits onlya slight decrease with resist trimming time. Thus, our modelingapproach seems to doubt the beneficial role of trimming processto LER reduction during pattern transfer. However, this resulthas limited applicability since it depends on our initial assump-tion that the initial postlithography resist sidewall has isotopicmorphology (i.e., its fluctuations do not present preferentialdirection). This is shown in Fig. 7(d) whose content is similarto that of Fig. 7(a), with the only difference that the initialresist sidewall has anisotropic morphlogy. This was modeledby considering that the initial resist sidewall hR,anis(y, z) is thesum of an isotropic self-affine surface hR,isotr(y, z) (generatedby the algorithm described in Section II-A) and of a completely

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Fig. 7. Effect of resist trimming time followed by anisotropic etching of 300-nm-thick underlayer on the LER parameters of the resist sidewall (full symbols)and the underlayer LER parameters (open symbols). In (a), (b), and (c), the initial postlithography resist sidewall has isotropic morphology and LER parameters:wR,initial = 2 nm, ξR,initial = 5 nm, and αR,initial = 0.5. (a) wR,trim/wR,initial and wU,trim/wR,initial versus trimming time. (b) The same as (a) for thecorrelation lengths (ξR,trim and ξU,trim) and (c) the same as (a) and (b) for the roughness exponent (αR,trim and αU,trim). Notice the similar trends of resistand underlayer sidewall roughness parameters after the sequential process. Notice also the much slower response of wU,trim which decreases very slightly withtrimming time. (d) The same as (a) but the initial resist sidewall has anisotropic morphology with preferential direction along etching direction. Notice the strongdependence of wU,trim on the trimming time, which reveals the crucial role of trimming in LER reduction during pattern transfer when the lithography resistsidewall presents anisotropic morphology.

anisotropic surface of curtainlike morphology: hR,anis(y, z) =A sin(2πy/λ). The anisotropic component participates in thetotal surface with an anisotropy weight factor fansi. That is

hR,init(z, y) = fanishR,anis(y, z) + (1 − fanis)hR,isotr(y, z).(2)

In Fig. 7(d), fanis = 0.6, total rms value wR,initial = 2 nm,ξR,isotr = 5 nm, αR,isot = 0.5, A = 2 nm, and λ = 20 nm. Inthis figure, one can easily see that, now, the trimming time hasa significant decreasing effect on the final underlayer roughnessafter pattern transfer in contrast to what is found when theresist sidewall has isotropic morhology. The beneficial role oftrimming to LER roughness is expected to enlarge with theincrease of the anisotropy parameter fanis.

IV. SUMMARY AND CONCLUSION

The transfer of resist LER to underlayers during plasma etch-ing steps has been one of the crucial, but less studied, aspectsof LER problem in microelectronics. However, its importance

is not limited to microelectronics, since it appears in any casethat a pattern is transferred to a substrate using a sacrificial resistfilm and the traditional combination of lithography and etchingprocesses.

In this paper, we presented the first results of a modelingapproach of the whole LER transfer process. Based on abstrac-tive models, the key features of this approach are the explicitconsideration of the postlithography resist sidewall roughnessand the inclusion of an optional resist trimming treatmentbefore pattern transfer. The aim was to investigate the effectsof pattern transfer, trimming time, and postlithography resistsidewall roughness parameters on the morphology of the resistand underlayer sidewalls.

The pattern transfer, approximated by an anisotropic etch-ing process, induces on both resist and underlayer sidewallsanisotropy in the form of striations, which are more intenseand well defined on the underlayer sidewalls. The origins of theformation of striations lie on the following: 1) the variationsof the CHD of the resist protrusions along the edge of resist–underlayer interface and 2) the shadowing effects that these

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protrusions cause to ions which etch the underlayer. The resisttrimming, approximated by an isotropic etching process, cre-ates craters on the resist surface.

Our modeling approach shows that both trimming and pat-tern transfer reduce rms roughness regardless of the initialresist sidewall LER parameters. In particular, the trimmingprocess affects significantly the resist sidewall roughness bydecreasing its rms value and increasing the correlation length(approximately of crater diameter) and the roughness exponent(elimination of high frequencies). The effect of trimming timeon the rms roughness of the underlayer sidewall becomesimportant in the case of initially anisotropic resist sidewall.

With respect to the effects of the initial postlithography resistsidewall LER parameters, the most striking result refers to therole of the initial resist correlation length. It was found thatlower initial correlation length leads to larger rms roughness re-duction to the underlayer. This means that lithographers shouldaim at lower correlation lengths in resist LER (molecular resistsor small diffusion lengths [44]), so that they maximize thereduction of rms roughness during its transfer to underlayers.

Concerning the evaluation of the models for trimming andpattern transfer described in this paper, we could say that thelist of phenomena not included is rather extended: nonverticalions or sidewalls, angle-dependent sputtering yield, polymer-ization on the resist surface, effects of photons, effect of bias,resist charging, effect of ions during trimming process, ionreflection, neutral etching during pattern transfer, shadowing ofneutral species, etc. We formulated simple models by takinginto account first-order geometrical effects which, however,are common for all chemistries, materials, and conditions, andmanaged to capture the main phenomena and trends. Giventhe complexity of the plasma environment, the lack in theliterature of a detailed simulation tool for dealing with LERproblem during etching steps, and the lack of well-designedseries of experiments with nontrivial equipment (3-D AFM) forthe model evaluation, the formulation of simple models withlow computational cost is a wise choice.

Future work in the lines of the modeling approach presentedin this paper can follow three directions. The first is to examinethe effects of parameters which were kept fixed in this paper,such as the selectivity of the underlayer with respect to theresist, the resist and underlayer thicknesses, the resist sidewallslope, etc. The second is to enrich our model with modules,simulating either other trimming processes or features of thepattern transfer process overlooked in this first approach. Thethird direction is the more detailed comparison with exper-imental results for the effects of both trimming and patterntransfer. At its present form, the developed model captures theexperimentally observed striation formation and LER reduc-tion, but more quantified comparison requires new experimentalmeasurements and results.

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George Kokkoris received the B.Sc. degree inchemical engineering from the National TechnicalUniversity of Athens, Athens, Greece, in 1998, theM.S. degree in microelectronics from the Nationaland Kapodistrian University of Athens, Athens, in2000, and the Ph.D. degree from the National Tech-nical University of Athens in 2005.

He has been with the Institute of Microelectronics,National Center for Scientific Research “Demokri-tos,” Attiki, Greece, since 1998. His research in-terests include modeling and simulation of plasma

processes for micro- and nanofabrication. He is the coauthor of 20 peer-reviewed journal articles.

Vassilios Constantoudis received the degreein physics from the Aristotelian University ofThessalonki, Thessaloniki, Greece, in 1989, andthe Ph.D. degree from the University of Athens,Athens, Greece, in 1999. His Ph.D. thesis was onthe nonlinear dynamics of magnetic systems.

He had a postgraduate studies with the Instituteof Theoretical and Physical Chemistry, National Hel-lenic Research Foundation, Athens, where he workedon the theory and applications of nonlinear andchaotic systems. After two years of postdoctoral

research with the National Technical University of Athens, Greece, wherehe worked on the applications of chaotic systems to molecular dissociationprocesses, he became a member of the plasma group in the Institute of Mi-croelectronics, National Center for Scientific Research “Demokritos,” Attiki,Greece. Since then, his main research interest has been on the problem of rough-ness characterization, formation, simulation, and application on nanoscale. Hehas investigated it in both microlithography and plasma etching processes. Heis a coauthor of 50 publications which have been cited by a third party morethan 200 times.

Evangelos Gogolides received the Diploma degreein chemical engineering from the National TechnicalUniversity of Athens, Athens, Greece, in 1985, andthe M.Sc. and Ph.D. degrees in chemical engineer-ing from the Massachusetts Institute of Technol-ogy, Cambridge, in 1987 and 1990, respectively. Histhesis work was on plasma processing and plasmaprocess simulation.

He did research on microlithography with MichaelHatzakis at the National Center for Scientific Re-search “Demokritos,” Attiki, Greece, where he is

currently the Director of Research. He is the author of more than 100 pub-lications and is the holder of seven patents. He is a Coordinator of severalresearch projects on next-generation lithography and nanofabrication usinglithography and plasma etching. His current research interests include micro-and nanopatterning and simulation for nanoelectronics, MEMS, bio-MEMS,micro(nano)fluidics, material surface nanotexture, and property modificationfor nano- and nanobio applications. He uses plasma technology as an enablingtechnology for such applications.

Dr. Gogolides was the Conference Program Chair for Micro and Nano Engi-neering Conference MNE-1997, a program and steering committee member ofMNE, and the Conference Chair for the 34th MNE 2008.